JP4415808B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device in which a low potential reference circuit, a high potential reference circuit, and a level shift circuit are provided in a first semiconductor layer on the main surface side of an SOI structure semiconductor substrate having a buried oxide film, and a manufacturing method thereof.

  A semiconductor device in which a low potential reference circuit, a high potential reference circuit, and a level shift circuit are provided in a first semiconductor layer on the main surface side of an SOI (Silicon On Insulator) structure semiconductor substrate having a buried oxide film, and a manufacturing method thereof For example, it is disclosed in Japanese Patent No. 3384399 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2004-6555 (Patent Document 2).

FIG. 10A is a circuit configuration diagram illustrating mainly the power portion of the motor control inverter disclosed in Patent Document 1. FIG. The power devices used to drive the three-phase motor Mo (here, IGBTs Q1 to Q6 and diodes D1 to D6 are shown) constitute a bridge circuit, and the structure of the power module housed in the same package I am doing. The main power supply V _CC is usually a high voltage of 100 to 400 VDC. When the high potential side of the main power supply V _CC is represented as V _CCH and the low potential side is represented as V _CCL , the potential of the gate electrode of the IGBT is higher than this in order to drive the IGBTs Q1 to Q3 connected to V _CCH. It becomes a potential. For this reason, a photocoupler (PC: Photo Coupler) and a high voltage IC (HVIC: High Voltage Integrated Circuit) 90 are used for the drive circuit. The input / output terminals (I / O: Input / Output) of the drive circuit are usually connected to a microcomputer, and the microcomputer controls the entire inverter.

  FIG. 10B is a block diagram of an internal configuration unit of the high voltage IC (HVIC) used in FIG.

The high voltage IC 90 shown in FIG. 10B includes a control circuit (CU: Control Unit), gate drive circuits GDU (Gate Drive Unit) 4 to 6 which are low potential reference circuits, and a gate drive circuit GDU1 which is a high potential reference circuit. 3 and a level shift circuit (LSU: Level Shift Unit). The control circuit CU exchanges signals with the microcomputer through the input / output terminal I / O, and generates a control signal indicating which IGBT in FIG. 10A is turned on and which is turned off. Gate drive circuits GDU (Gate Drive Unit) 4 to 6 which are low potential reference circuits drive IGBTs Q4 to Q6 connected to the low potential side V _CCL of the main power supply V _CC in FIG. The gate drive circuits GDU1 to GDU1 to 3 which are high potential reference circuits drive the IGBTs Q1 to Q3 connected to the high potential side V _CCH of the main power supply V _CC in FIG. The level shift circuit LSU is a signal V _CCL level of the control circuit CU, GDU1～3 signals alternate between the V _CCH level and the V _CCL level (SIN1~3, SOUT1~3) between mediate Work.

In a semiconductor device provided with a low potential reference circuit and a high potential reference circuit, such as the high voltage IC 90 shown in FIGS. 10A and 10B, the formation region of the low potential reference circuit and the formation of the high potential reference circuit are provided. A structure that separates the regions is employed. As the isolation structure, a junction isolation structure using a pn junction and a dielectric isolation structure using a dielectric such as SiO ₂ are generally used.

  FIG. 11 shows a conventional high voltage IC disclosed in Patent Document 2.

  A high voltage IC 91 shown in FIG. 11 is a semiconductor device provided with a low potential (GND) reference circuit, a high potential (floating) reference circuit, and a level shift circuit, and a GND reference circuit forming region, a floating reference circuit, A pn junction isolation is used to isolate the formation region of the level shift circuit.

  In the high breakdown voltage IC 91 using pn junction isolation shown in FIG. 11, a junction capacitor exists in each pn junction used for isolation, and a kind of capacitor is formed. Therefore, a voltage that changes sharply is applied to this capacitor. Then, a charging current (displacement current) flows over the entire surface of the pn junction. The charging current has a problem in that the parasitic transistors PTr1 and PTr2 shown in the figure are operated to cause malfunction of the circuit and element destruction.

  On the other hand, FIG. 12 shows a conventional high-voltage IC for driving an inverter using an SOI substrate and trench isolation as a high-voltage IC having a dielectric isolation structure.

  A high voltage IC 92 shown in FIG. 12 includes a low potential (GND) reference circuit, a high potential (floating) reference circuit, and a level shift circuit on the semiconductor layer 1 on the main surface side of the SOI structure semiconductor substrate 10 having the buried oxide film 3. Are provided respectively. The formation regions of the GND reference circuit, the floating reference circuit, and the level shift circuit are insulated (dielectric) separated by the buried oxide film 3 of the SOI substrate and the sidewall oxide film 4s of the trench 4.

  In the level shift circuit of the high breakdown voltage IC 92, a high breakdown voltage circuit element is required to connect the low potential reference circuit and the high potential reference circuit. The circuit element in the level shift circuit formation region shown in FIG. 12 has an SOI-RESURF structure.

As shown in FIG. 13, in this structure, the lateral breakdown voltage (L) is ensured by an SOI-RESURF structure formed by a surface p-type impurity layer and a buried oxide film 3 which are generally called. In addition, the vertical breakdown voltage (V) under the drain relaxes the electric field in both the low-concentration semiconductor layer 1 and the buried oxide film 3 between the drain and the buried oxide film 3.
Japanese Patent No. 3384399 JP 2004-6555 A

  In the high breakdown voltage IC 92 of FIG. 12, the formation regions of the GND reference circuit, the floating reference circuit, and the level shift circuit are surrounded by the buried oxide film 3 and the sidewall oxide film 4 s of the trench 4. Therefore, unlike the high breakdown voltage IC 91 using pn junction isolation shown in FIG. 11, no parasitic transistor operation occurs. However, in the high voltage IC 92 of FIG. 12, as shown in the figure, a kind of capacitors C1 to C3 are formed with the buried oxide film 3 interposed therebetween. Therefore, similarly to the high breakdown voltage IC 91 using the pn junction isolation of FIG. 11, when a suddenly changing voltage is applied to one circuit formation region insulated and isolated by the trench 4, a charging current (displacement current) flows. The depletion layer is opened and closed by capacitive coupling in another circuit formation region in the vicinity.

For example, when a noise pulse voltage due to switching is applied as V _UH of a floating reference circuit that operates at several 100 V to 1200 V, as shown in FIGS. 14A and 14B, in the GND reference circuit formation region, the main surface The depletion layer 1 e extends from the buried oxide film 3 in the semiconductor layer 1 on the side. In particular, when the resistivity of the semiconductor layer (support substrate) 2 under the buried oxide film 3 is large, the influence of the support substrate 2 is weak because the potential fixation is weak.

  14 (a) and 14 (b), the influence on the circuit element due to the expansion of the depletion layer 1e is large, for example, in an element having an active region in the substrate depth direction such as a bipolar transistor. The probability of doing will increase. In order to avoid the influence on the circuit element due to the spread of the depletion layer 1e, it is conceivable that the circuit is constituted by only the surface device, but this restricts the circuit design.

  Therefore, the present invention is a semiconductor device in which a low potential reference circuit, a high potential reference circuit, and a level shift circuit are provided on the surface layer portion of an SOI substrate, and a voltage that changes sharply is applied to any of the above circuits. However, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can suppress the influence on another circuit and ensure a degree of freedom in circuit design.

  According to the first to sixth aspects of the present invention, a low potential reference circuit, a high potential reference circuit, and a level shift circuit are provided in the surface layer portion of the first semiconductor layer on the main surface side of the SOI structure semiconductor substrate having a buried oxide film. This invention relates to the first semiconductor device.

  According to the first aspect of the present invention, the formation regions of the low potential reference circuit, the high potential reference circuit, and the level shift circuit are insulated and separated from each other by the first trench reaching the buried oxide film. A first impurity layer having the same conductivity type as the first semiconductor layer and having a high impurity concentration is formed on the buried oxide film, and includes at least one of the low potential reference circuit, the high potential reference circuit, and the level shift circuit. In the formation region, a second buried oxide film is formed in the first semiconductor layer, and the low potential reference circuit and the high potential reference circuit are formed in a surface layer portion of the first semiconductor layer by the second buried oxide film. In addition, at least one of the level shift circuits and the first impurity layer are insulated from each other.

  In the semiconductor device, the first trench in which the formation regions of the low potential reference circuit, the high potential reference circuit, and the level shift circuit formed in the first semiconductor layer on the main surface side of the SOI structure semiconductor substrate reach the buried oxide film. Therefore, parasitic transistor operation does not occur. In addition, since the first impurity layer having a high impurity concentration is formed on the buried oxide film in the first semiconductor layer, even if a voltage that changes sharply is applied to one circuit formation region insulated and separated by the trench. The spread of the depletion layer in another circuit formation region in the vicinity can be suppressed.

  As described above, the semiconductor device is a semiconductor device in which a low potential reference circuit, a high potential reference circuit, and a level shift circuit are provided in a surface layer portion of an SOI substrate. Even when a changing voltage is applied, a semiconductor device in which influence on another circuit is suppressed can be obtained.

  Here, among the circuit elements used in the above circuit, in order to increase the source-drain breakdown voltage of the circuit element, the distance between the source and the drain is increased, and the depletion layer extends from the buried oxide film. There are circuit elements (of SOI-RESURF structure) designed to fully deplete the gap. For such a circuit element, the first impurity layer formed on the buried oxide film suppresses the spread of the depletion layer from the buried oxide film, and thus lowers the source-drain breakdown voltage. However, in the semiconductor device, the second buried oxide film is formed in the first semiconductor layer in the formation region of at least one of the low potential reference circuit, the high potential reference circuit, and the level shift circuit, thereby And the first impurity layer are insulated from each other. For this reason, the formation region of at least one of the low potential reference circuit, the high potential reference circuit, and the level shift circuit into which the second buried oxide film is introduced is designed to completely deplete the source-drain region again. The circuit element can be used, and a decrease in the breakdown voltage of the circuit element can be suppressed.

  As described above, the semiconductor device is a semiconductor device in which a low potential reference circuit, a high potential reference circuit, and a level shift circuit are provided in the surface layer portion of the SOI substrate, and the degree of freedom in circuit design is ensured. A semiconductor device can be obtained.

  According to a second aspect of the present invention, the semiconductor device is suitable when the circuit on which the second buried oxide film is formed is the level shift circuit.

  In the level shift circuit, a high-voltage circuit element is required to connect the low-potential reference circuit and the high-potential reference circuit, and the source-drain is completely depleted by the expansion of the depletion layer from the buried oxide film. Designed circuit elements are often used. Therefore, by introducing the second buried oxide film in the formation region of the level shift circuit in which such circuit elements are formed, the depletion layer expansion suppressing effect by the first impurity layer and the breakdown voltage by the second buried oxide film are provided. The effect of suppressing the decrease can be efficiently exhibited.

  In order to realize complete depletion between the source and the drain in the circuit element as described in claim 3, the tip of the source diffusion region of the MOS transistor in the level shift circuit, or the source diffusion region and the drain It is preferable that the tip of the diffusion region reaches the second buried oxide film.

  According to a fourth aspect of the present invention, in the semiconductor device using an SOI structure semiconductor substrate, the first semiconductor layer is preferably of an n conductivity type.

  In the semiconductor device, for example, the low potential reference circuit can be a GND (ground) reference circuit, and the high potential reference circuit can be a floating reference circuit.

  According to a sixth aspect of the present invention, the semiconductor device is suitable for a high voltage IC for driving an inverter.

  The invention described in claims 7 to 9 is an invention relating to a manufacturing method of the first semiconductor device.

  The invention according to claim 7 is characterized in that the second buried oxide film, which is a feature of the semiconductor device, is formed by oxygen ion implantation. Thus, the semiconductor device can be easily formed, and an inexpensive semiconductor device can be obtained. As described in claim 8, the oxygen ion implantation can be performed before the formation of the first trench, or can be performed after the formation of the first trench as described in claim 9.

  In addition, about the effect of the 1st semiconductor device manufactured by the manufacturing method of the said Claims 7-9, it is as above-mentioned, The description is abbreviate | omitted.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 according to this embodiment. In the semiconductor device 100 of FIG. 1, the same parts as those of the semiconductor device (high voltage IC) 92 of FIG.

  A semiconductor device 100 shown in FIG. 1 is a high voltage IC for driving an inverter similar to the semiconductor device 92 of FIG. In the semiconductor device 100 of FIG. 1, as in the semiconductor device 92 of FIG. 12, a low potential (GND) reference circuit, a high potential is provided on the first semiconductor layer 1 on the main surface side of the SOI structure semiconductor substrate 11 having the buried oxide film 3. A potential (floating) reference circuit and a level shift circuit are provided. Further, the formation regions of the GND reference circuit, the floating reference circuit, and the level shift circuit are insulated from each other by the buried oxide film 3 of the SOI substrate 11 and the sidewall oxide film 4s of the trench 4 as shown in FIG. . Therefore, in the semiconductor device 100 of FIG. 1, the parasitic transistor operation does not occur as in the semiconductor device 92 of FIG.

  In the semiconductor device 100 of FIG. 1, unlike the semiconductor device 92 of FIG. 12, the impurity concentration of the same conductivity type as that of the first semiconductor layer 1 is high (n +) on the buried oxide film 3 in the first semiconductor layer 1 of n conductivity type. ) A first impurity layer 1a is formed. In the semiconductor device 100 of FIG. 1 as well, similar to the semiconductor device 92 of FIG. 12, the types of capacitors C1 to C3 shown in FIG. 12 are formed with the buried oxide film 3 interposed therebetween. However, in the semiconductor device 100 of FIG. 1, even if a voltage that changes sharply is applied to one circuit formation region isolated by the trench 4 by the high impurity concentration first impurity layer 1a, Expansion of the depletion layer in the formation region is suppressed. That is, the maximum depletion layer width decreases as the impurity concentration increases according to the formula for giving the maximum depletion layer width in the MOS diode shown in the lower part of FIG. Therefore, in the semiconductor device 100 of FIG. 1 having the first impurity layer 1a having a high impurity concentration, the expansion of the depletion layer is suppressed as compared with the semiconductor device 92 of FIG. 12 having no first impurity layer 1a.

  As described above, the semiconductor device 100 in FIG. 1 is a semiconductor device in which a low potential reference circuit, a high potential reference circuit, and a level shift circuit are provided in the surface layer portion of the SOI substrate 11. Even when a voltage that changes sharply is applied to a circuit, a semiconductor device in which the influence on another circuit is suppressed can be obtained.

  Further, in the semiconductor device 100 of FIG. 1, the second buried oxide film 3a is formed in the first semiconductor layer 1 in the formation region of the level shift circuit, and the second buried oxide film 3a serves as the first semiconductor. The level shift circuit formed in the surface layer portion of the layer 1 and the first impurity layer 1a are insulated and separated from each other.

  Here, among the circuit elements used in the level shift circuit, in order to increase the source-drain breakdown voltage of the circuit element, the distance between the source (S) and the drain (D) is increased as shown in FIG. There is a circuit element (SOI-RESURF structure) designed to completely deplete the source-drain region by spreading the depletion layer from the buried oxide film 3. For such a circuit element, the first impurity layer 1 a formed on the buried oxide film 3 suppresses the spread of the depletion layer from the buried oxide film 3, thereby reducing the source-drain breakdown voltage. .

  On the other hand, the level shift circuit formation region in the semiconductor device 100 of FIG. 1 in which the second buried oxide film 3a is introduced is designed to completely deplete the source-drain region again (SOI-RESURF structure). The circuit element can be used, and a decrease in the breakdown voltage of the circuit element can be suppressed. In order to realize complete depletion between the source and the drain in the circuit element described above, the tip of the source diffusion region of the MOS transistor or the tip of the source diffusion region and the drain diffusion region in the level shift circuit is the second It is preferable to reach the buried oxide film 3a.

  As described above, the semiconductor device 100 in FIG. 1 is a semiconductor device that can avoid restrictions on circuit design such as forming a circuit with only a surface device and has a degree of freedom in circuit design. be able to.

  In the semiconductor device 100 of FIG. 1, the second buried oxide film 3a is formed only in the level shift circuit. In the level shift circuit, a circuit element having a high breakdown voltage is required to connect the low potential reference circuit and the high potential reference circuit, and the depletion layer from the buried oxide film 3 spreads to completely deplete the source and drain. Circuit elements designed in this way are often used. Therefore, by introducing the second buried oxide film 3a into the formation region of the level shift circuit in which such a circuit element is formed, the effect of suppressing the depletion layer from spreading by the first impurity layer 1a and the second buried oxide film are provided. The effect of suppressing pressure drop reduction by 3a can be efficiently exhibited.

  As described above, the second buried oxide film 3a is preferably formed in a level shift circuit that requires a high breakdown voltage circuit element. However, the present invention is not limited to this, and it is effective to form the second buried oxide film 3a in another low potential reference circuit or a high potential reference circuit that requires a high breakdown voltage circuit element.

  Next, a method for manufacturing the semiconductor device 100 shown in FIG. 1 will be described.

  2A to 2D are cross-sectional views for each process showing a method of forming the first impurity layer 1a and the second buried oxide film 3a, which is a feature of the semiconductor device 100. FIG.

  As shown in FIG. 2A, the first impurity layer 1 a is formed in advance at the stage of preparing the SOI substrate 11. That is, an impurity is implanted into the surface of one silicon (Si) substrate that becomes the first semiconductor layer 1 to form the first impurity layer 1a, and is opposed to the other silicon (Si) substrate that becomes the second semiconductor layer 2. Then, they are bonded together by a commonly used substrate bonding method. A buried oxide film 3 is formed at the time of bonding the substrates. Next, the first semiconductor layer 1 is polished to a predetermined thickness. Thereby, the SOI structure semiconductor substrate 11 in which the first impurity layer 1a is formed on the buried oxide film 3 is formed.

  Next, the surface of the first semiconductor layer 1 is covered with a thermal oxide film 1b. Next, a photoresist film is formed on the thermal oxide film 1b and patterned on a mask M1 having a level shift circuit formation region as an opening.

  Next, oxygen ions are implanted into the predetermined depth of the first semiconductor layer 1 from the opening of the mask M1. After implanting oxygen ions, the thermal oxide film 1b in the level shift circuit formation region is removed using the mask M1.

  Next, as shown in FIG. 2B, after removing the mask M1, annealing is performed at a high temperature to modify the oxygen ion implantation region into the second buried oxide film 3a and to recover the ion implantation damage. Subsequently, an oxidation process is performed to locally oxidize the level shift circuit formation region to form a thick thermal oxide film 1b in the level shift circuit formation region. The thick portion of the thermal oxide film 1b in this level shift circuit formation region serves as a positioning reference in the trench formation in FIG.

  Next, as shown in FIG. 2C, a silicon nitride (SiN) film 1c and a silicon oxide (SiO) film 1d, which serve as a trench etching mask, are sequentially deposited on the thermal oxide film 1b.

  Next, as shown in FIG. 2D, the trench formation region in the SiN film 1c and the SiO film 1d is opened using the photoresist as a mask, and after removing the photoresist, the silicon film different from silicon (Si) is used using the SiO film 1d as a mask. The trench 4 is formed by isotropic etching. The side wall oxide film of the trench 4 in the subsequent process is formed of the second buried oxide film 3a so that the level shift circuit formed in the surface layer portion of the first semiconductor layer 1 and the first impurity layer 1a are insulated from each other. A trench 4 is formed at a position where it abuts against the end.

  In FIG. 2D and thereafter, after forming the sidewall oxide film of the trench 4, the trench 4 is backfilled, and a low potential reference circuit is formed on the surface layer portion of the first semiconductor layer 1 using a normal semiconductor device manufacturing process. A high potential reference circuit and a level shift circuit are formed.

  Thus, the semiconductor device 100 shown in FIG. 1 is manufactured.

  In the manufacturing process of the semiconductor device 100 shown in FIGS. 2A to 2D, the formation order of the second buried oxide film 3a and the trench 4 may be reversed. 3A to 3D are cross-sectional views for each process when the trench 4 is formed first.

  In this case, as shown in FIG. 3A, after preparing the SOI structure semiconductor substrate 11 by the substrate bonding method, the thermal oxide film 1b, the silicon nitride (SiN) film 1c, and the first semiconductor layer 1 are formed. A silicon oxide (SiO) film 1d is sequentially deposited.

  Next, the trench formation region in the SiN film 1c and the SiO film 1d is opened using the photoresist as a mask, and after removing the photoresist, the trench 4 is formed by silicon (Si) anisotropic etching using the SiO film 1d as a mask. .

  Next, as shown in FIG. 3B, a side wall oxide film 4s is formed in the trench 4 by thermal oxidation, and the trench 4 is backfilled with polycrystalline silicon (or dielectric) 4u (after deposition, etch back is performed). ).

  Next, as shown in FIG. 3C, the upper SiO film 1d and the SiN film 1c are removed. Next, a photoresist film is formed on the thermal oxide film 1b, and patterned into a mask M2 having a level shift circuit formation region as an opening.

  Next, oxygen ions are implanted into the predetermined depth of the first semiconductor layer 1 from the opening of the mask M2.

  Next, as shown in FIG. 3D, after removing the mask M2, annealing is performed at a high temperature to modify the oxygen ion implantation region into the second buried oxide film 3a and to recover the ion implantation damage.

  After FIG. 3D, a low potential reference circuit, a high potential reference circuit, and a level shift circuit are formed in the surface layer portion of the first semiconductor layer 1 using a normal semiconductor device manufacturing process.

  Thus, the semiconductor device 100 shown in FIG. 1 is manufactured.

  In any of the manufacturing methods of the semiconductor device 100 shown in FIGS. 2A to 2D or FIGS. 3A to 3D, the second buried oxide film 3a is formed by oxygen ion implantation. Thereby, as described above, the semiconductor device 100 can be easily formed, and an inexpensive semiconductor device can be obtained.

(Second Embodiment)
In the first embodiment, a first impurity layer having a high impurity concentration is formed on a buried oxide film of an SOI structure semiconductor substrate, so that even if a voltage that changes sharply is applied to one of the circuits, another circuit is transferred. A semiconductor device in which the influence of the above is suppressed and a manufacturing method thereof have been shown. The present embodiment relates to a semiconductor device in which a second impurity region having a high impurity concentration is formed under a buried oxide film of an SOI structure semiconductor substrate and a method for manufacturing the same. Hereinafter, the present embodiment will be described with reference to the drawings.

  FIG. 4 is a schematic cross-sectional view of the semiconductor device 101 in this embodiment. Also in the semiconductor device 101 of FIG. 4, the same parts as those of the semiconductor device (high voltage IC) 92 of FIG.

  The semiconductor device 101 shown in FIG. 4 is also an inverter driving high voltage IC similar to the semiconductor device 92 of FIG. In the semiconductor device 101 of FIG. 4, similarly to the semiconductor device 92 of FIG. 12, the first semiconductor layer 1 on the main surface side of the SOI structure semiconductor substrate 10 having the buried oxide film 3 has a low potential (GND) reference circuit, A potential (floating) reference circuit and a level shift circuit are provided. Further, the formation regions of the GND reference circuit, the floating reference circuit, and the level shift circuit are insulated and separated from each other by the buried oxide film 3 of the SOI substrate 10 and the sidewall oxide film of the first trench 4 as shown in FIG. Yes. Therefore, in the semiconductor device 101 of FIG. 4 as well, the parasitic transistor operation does not occur like the semiconductor device 92 of FIG.

  In the semiconductor device 101 of FIG. 4, unlike the semiconductor device 92 of FIG. 12, the second semiconductor layer is located below the buried oxide film 3 in the second semiconductor layer 2 of the n conductivity type at the boundary between the GND reference circuit and the level shift circuit. (N +) second impurity region 2a having the same conductivity type as that of FIG. Further, in the semiconductor device 101, the second trench 5 is formed that reaches the second impurity region 2 a through the buried oxide film 3 from the main surface side of the SOI substrate 10. In the second trench 5, polycrystalline silicon 5u containing an impurity having the same conductivity type as that of the second impurity region 2a is buried via a sidewall insulating film 5s. The potential of the second impurity region 2 a is fixed on the main surface side of the SOI substrate 10 through the polycrystalline silicon 5 u embedded in the second trench 5.

  In the semiconductor device 101 of FIG. 4 as well, the types of capacitors C1 to C3 shown in FIG. 12 are formed with the buried oxide film 3 interposed therebetween, similarly to the semiconductor device 92 of FIG. However, in the semiconductor device 101 of FIG. 4, even if a voltage that changes sharply is applied to one circuit formation region isolated by the first trench 4, the second impurity region 2a having a high impurity concentration becomes an obstacle, The influence on a certain other circuit formation region is suppressed.

  The formation position of the second impurity region 2a is not limited to the boundary portion between the low potential (GND) reference circuit and the level shift circuit, but is formed, for example, at the boundary portion between the high potential (floating) reference circuit and the level shift circuit. Can exhibit the same obstacle effect. The formation position of the second impurity region 2a may be other than the boundary portion of each circuit, but by forming it at the boundary portion of each circuit, the potential fixing effect by the second impurity region 2a can be efficiently exhibited and Even if the potential is fixed on the main surface side via the two trenches 5, the degree of freedom in circuit design can be ensured to the maximum. In addition, as in the semiconductor device 101 shown in FIG. 4, the first first trench 4 is preferably disposed adjacent to the second trench 5. Further, the width of the second trench 5 is preferably larger than the width of the first first trench 4. Thereby, as will be described later, etching for forming the first trench 4 and the second trench 5 can be performed in the same process.

  FIG. 5 shows another semiconductor device 102. In the semiconductor device 101 of FIG. 4, the second impurity region 2a is formed under the buried oxide film 3 of the SOI substrate 10 at the boundary between the GND reference circuit and the level shift circuit. On the other hand, in the semiconductor device 102 of FIG. 5, the (n +) second impurity region 2b having the same conductivity type and high impurity concentration as the second semiconductor layer 2 is formed on the entire surface of the SOI structure semiconductor substrate 12 with the buried oxide film 3. Formed below. Thus, by forming the second impurity region 2b on the entire surface under the buried oxide film 3, the potential fixing effect by the second impurity region 2b is surely exhibited, and at the main surface side through the second trench 5. Even if the potential is fixed at the same time, the maximum degree of freedom in circuit design can be secured.

  The semiconductor devices 101 and 102 shown in FIGS. 4 and 5 can suppress the vapor phase diffusion of impurities during the process, compared with the case where the entire second semiconductor layer 2 as the support substrate is made high in concentration. Variations in characteristics of circuit elements formed in the surface layer portion of the first semiconductor layer 1 due to impurity diffusion can be reduced. As another potential fixing method, a method of forming a circuit element on the surface layer portion of the first semiconductor layer 1 and then etching a necessary region from the back surface to fix the potential with a metal film is conceivable. However, compared with the method of etching the back surface, the potential fixing method in the semiconductor devices 101 and 102 of FIGS. 4 and 5 can suppress the stress fluctuation of the SOI structure semiconductor substrates 10 and 12, and the circuit element due to the stress fluctuation. It is possible to reduce fluctuations in characteristics.

  As described above, the semiconductor devices 101 and 102 of FIGS. 4 and 5 are semiconductor devices in which the low potential reference circuit, the high potential reference circuit, and the level shift circuit are provided in the surface layer portion of the SOI substrates 10 and 12. Thus, even if a voltage that changes sharply is applied to any of the above circuits, a semiconductor device in which the influence on another circuit is suppressed can be obtained.

  The semiconductor devices 101 and 102 form the second impurity regions 2 a and 2 b in the second semiconductor layer 2 below the buried oxide film 3, and are formed on the first semiconductor layer 1 on the buried oxide film 3. The circuit elements of each circuit are not affected, and the circuit design can be performed in the same manner as a conventional semiconductor device. Therefore, the degree of freedom in circuit design is ensured similarly to the conventional semiconductor device 92 shown in FIG.

  Next, a method for manufacturing the semiconductor device 101 shown in FIG. 4 will be described.

  FIGS. 6 to 8 are cross-sectional views by process showing a method of forming the second impurity region 2 a and the second trench 5, which is a feature of the semiconductor device 101.

  As shown in FIG. 6A, after preparing the SOI structure semiconductor substrate 10 by the substrate bonding method, the thermal oxide film 1b, the silicon nitride (SiN) film 1c, and the silicon oxide (SiO) are formed on the first semiconductor layer 1. A film 1d is sequentially deposited. The SiO film 1d is used as a mask during trench etching, and the SiN film 1c serves as a stopper for removing the SiO film 1d used as the mask after etching. The film thickness of the SiO film 1d used as an etching mask is deposited thick in consideration of the amount of film reduction during etching.

  Next, using the photoresist as a mask, the formation regions of the first trench 4 and the second trench 5 in the SiN film 1c and the SiO film 1d are opened. At this time, the width t of the second trench 5 is set larger than the width s of the first trench 4. The resist mask is removed by over-etching until the SiN film 1c and the SiO film 1d can be completely removed.

Next, as shown in FIG. 6B, the first semiconductor layer 1 is subjected to Si dry etching (low temperature ECR etching processing including SF ₆ and O ₂ ) having a selection ratio of 20 or more with respect to the SiO film 1d. One trench 4 and a second trench 5 are formed.

  Here, FIG. 9 shows the relationship between the trench width and the etching rate by the etching. From the results in FIG. 9, the etching rate increases as the trench width increases. The reason why the width t of the second trench 5 is set larger than the width s of the first trench 4 is to use the difference in etching rate due to the difference in trench width.

  Therefore, as shown in FIG. 6B, when the first trench 4 and the second trench 5 are simultaneously etched, the tip of the wide second trench 5 first reaches the buried oxide film 3, and this stage Then, the etching of the first semiconductor layer 1 is finished.

  Subsequently, as shown in FIG. 6C, oxide film etching is performed, and only the second trench 5 where the buried oxide film 3 is exposed is etched, and the tip of the second trench 5 is the second supporting substrate. The semiconductor layer 2 is reached.

  Subsequently, as shown in FIG. 7A, Si etching is performed so that the tip of the first trench 4 reaches the buried oxide film 3. At that time, the second semiconductor layer 2 which is the support substrate at the tip of the second trench 5 is also shaved at the same time.

  Next, as shown in FIG. 7B, using the trench mask as it is, phosphorus (P) is ion-implanted into the second semiconductor layer 2 at the tip of the second trench 5 to form the second impurity region 2a. A phosphorus ion implantation region is formed. The acceleration voltage at the time of ion implantation is set to a range in which the implanted ions cannot pass through the laminated film composed of the SiO film 1d, the SiN film 1c and the thermal oxide film 1b.

  Next, as shown in FIG. 7C, thermal oxidation treatment is performed to form side wall oxide films 4 s and 5 s in the first trench 4 and the second trench 5. By this thermal oxidation treatment, the phosphorous ion implantation region in the second semiconductor layer 2 is simultaneously diffused and activated to form the second impurity region 2a.

Next, as shown in FIG. 8A, the oxide film formed at the bottom of the second trench 5 in the previous step is removed by using anisotropic SiO ₂ etching. Etching conditions are set such that the sidewall oxide films 4 s and 5 s and the buried oxide film 3 exposed at the bottom of the first trench 4 are not removed.

  Next, as shown in FIG. 8B, polycrystalline silicon 5u containing n-conductivity type impurities at a high concentration and having (n +) conductivity is deposited on the entire surface, and the first trench 4 and the second trench are then deposited. Backfill 5

  Next, as shown in FIG. 8C, the polycrystalline silicon 5u and the SiO film 1d deposited on the upper surface of the SOI substrate 10 are removed by CMP (Chemical Mechanical Polishing) using the SiN film 1c as a stopper.

  After FIG. 8C, a low potential reference circuit, a high potential reference circuit, and a level shift circuit are formed in the surface layer portion of the first semiconductor layer 1 using a normal semiconductor device manufacturing process.

  Thus, the semiconductor device 101 shown in FIG. 4 is manufactured.

  In the manufacture of the semiconductor device 102 shown in FIG. 5, the second impurity region 2 b is formed in advance at the stage of preparing the SOI substrate 12. That is, impurities are implanted into the surface of one silicon (Si) substrate that becomes the second semiconductor layer 2 that is the support substrate to form the second impurity region 2b, and the other silicon (Si that becomes the first semiconductor layer 1) ) Opposing to the substrate, bonding is performed by a commonly used substrate bonding method. A buried oxide film 3 is formed at the time of bonding the substrates. Next, the first semiconductor layer 1 is polished to a predetermined thickness. Thus, the SOI structure semiconductor substrate 12 in which the second impurity region 2b is formed under the buried oxide film 3 is formed.

  The semiconductor device 102 shown in FIG. 5 is manufactured by using the SOI substrate 12 and using the steps shown in FIGS. 6 to 8 except the ion implantation step shown in FIG. 7B.

  In the manufacturing method of the semiconductor devices 101 and 102 shown in FIGS. 6 to 8, the etching for forming the first trench 4 and the second trench 5 is performed in the same process. For this reason, the semiconductor devices 101 and 102 can be manufactured at low cost.

(Other embodiments)
Each of the semiconductor devices 100 to 103 of the above embodiment is a semiconductor device in which the first semiconductor layer 1 and the second semiconductor layer 2 use the n-conductivity type SOI structure semiconductor substrates 10 to 12. However, the semiconductor device of the present invention is not limited to this, and may be a semiconductor device using a p-conductivity type SOI structure semiconductor substrate. In this case, all the conductivity types shown in the above-described embodiments are reversed.

  In the semiconductor device of the above embodiment, the inverter is a high breakdown voltage IC for driving an inverter in which the low potential reference circuit is a GND (ground) reference circuit and the high potential reference circuit is a floating reference circuit. However, the semiconductor device of the present invention is not limited to this, and can be applied to any semiconductor device provided with two different reference potential circuits of a low potential and a high potential and a level shift circuit for connecting them.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. (A)-(d) is a figure explaining the manufacturing method of the semiconductor device of FIG. 1, and the cross section according to process which shows the formation method of the 1st impurity layer and 2nd buried oxide film which are the characteristics of the semiconductor device of FIG. FIG. (A)-(d) is a figure explaining the manufacturing method of the semiconductor device of FIG. 1, and is sectional drawing according to process in the case of forming a trench previously. It is typical sectional drawing of the semiconductor device in 2nd Embodiment. It is a typical sectional view of another semiconductor device in a 2nd embodiment. (A)-(c) is sectional drawing according to process which shows the formation method of the 2nd impurity region and 2nd trench which are the characteristics of the semiconductor device of FIG. (A)-(c) is sectional drawing according to process which shows the formation method of the 2nd impurity region and 2nd trench which are the characteristics of the semiconductor device of FIG. (A)-(c) is sectional drawing according to process which shows the formation method of the 2nd impurity region and 2nd trench which are the characteristics of the semiconductor device of FIG. It is a figure which shows the relationship between a trench width and an etching rate. (A) is a circuit block diagram explaining centering on the power part of the inverter for motor control currently disclosed by patent document 1. FIG. (B) is a block diagram of an internal configuration unit of a high voltage IC (HVIC) used in (a). It is a figure which shows the conventional high voltage | pressure-resistant IC currently disclosed by patent document 2. FIG. It is a figure which shows the conventional high voltage IC for inverter drive using SOI substrate and trench isolation as a high voltage IC with a dielectric isolation structure. It is a figure explaining an SOI-RESURF structure. (A), (b) is a figure which shows the expansion of the depletion layer in a GND reference circuit formation area.

Explanation of symbols

90 to 92, 100 to 102 Semiconductor device (high voltage IC)
10-12 SOI structure semiconductor substrate 1 1st semiconductor layer 1a 1st impurity layer 2 2nd semiconductor layer (support substrate)
2a, 2b 2nd impurity region 3 buried oxide film 3a second buried oxide film 4 (first) trench 4s sidewall oxide film 5 second trench 5s sidewall insulating film (oxide film)
5u polycrystalline silicon

Claims (9)

A semiconductor device in which a low potential reference circuit, a high potential reference circuit, and a level shift circuit are provided in a surface layer portion of a first semiconductor layer on a main surface side of an SOI structure semiconductor substrate having a buried oxide film,
The formation regions of the low potential reference circuit, the high potential reference circuit, and the level shift circuit are insulated from each other by a first trench reaching the buried oxide film,
A first impurity layer having the same conductivity type as the first semiconductor layer and a high impurity concentration is formed on the buried oxide film in the first semiconductor layer,
A second buried oxide film is formed in the first semiconductor layer in a formation region of at least one of the low potential reference circuit, the high potential reference circuit, and the level shift circuit;
At least one of the low potential reference circuit, the high potential reference circuit, and the level shift circuit formed in the surface layer portion of the first semiconductor layer by the second buried oxide film and the first impurity layer are mutually connected. A semiconductor device characterized by being insulated and separated.   2. The semiconductor device according to claim 1, wherein the circuit in which the second buried oxide film is formed is the level shift circuit.   3. The semiconductor device according to claim 2, wherein a leading end of a source diffusion region of a MOS transistor or a leading end of a source diffusion region and a drain diffusion region reaches the second buried oxide film in the level shift circuit. .   The semiconductor device according to claim 1, wherein the first semiconductor layer is of n conductivity type.   5. The semiconductor device according to claim 1, wherein the low potential reference circuit is a GND reference circuit, and the high potential reference circuit is a floating reference circuit. 6.   6. The semiconductor device according to claim 1, wherein the semiconductor device is a high voltage IC for driving an inverter. A low potential reference circuit, a high potential reference circuit, and a level shift circuit are provided on the surface layer portion of the first semiconductor layer on the main surface side of the SOI structure semiconductor substrate having a buried oxide film,
The formation regions of the low potential reference circuit, the high potential reference circuit, and the level shift circuit are insulated from each other by a first trench reaching the buried oxide film,
A first impurity layer having the same conductivity type as the first semiconductor layer and a high impurity concentration is formed on the buried oxide film in the first semiconductor layer,
A method of manufacturing a semiconductor device, wherein a second buried oxide film is formed in the first semiconductor layer in a formation region of at least one of the low potential reference circuit, the high potential reference circuit, and the level shift circuit. ,
A method of manufacturing a semiconductor device, wherein the second buried oxide film is formed by oxygen ion implantation.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the oxygen ion implantation is performed before the formation of the first trench.   The method of manufacturing a semiconductor device according to claim 7, wherein the oxygen ion implantation is performed after the formation of the first trench.

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