JP4983333B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device applicable to a high voltage IC for driving an inverter or the like.

  Conventionally, a high voltage IC for driving an inverter or the like is disclosed in, for example, Patent Document 1 and Non-Patent Document 1. As an example of such a high voltage IC structure, FIG. 9 shows an example in which an SOI structure semiconductor substrate and an insulating isolation trench are used. FIG. 9 is a schematic cross-sectional view of a conventional high voltage IC 1. In FIG. 9, the same elements as those shown in the embodiment of the present invention are given the same reference numerals or similar reference numerals.

  As shown in FIG. 9, a low potential (GND) reference circuit 2, a high potential (floating) reference circuit 3, and a level shift circuit 5 are provided on the semiconductor layer 11 of the SOI structure semiconductor substrate 10 constituting the high voltage IC 1. Is provided. The formation regions of the GND reference circuit 2, the floating reference circuit 3, and the level shift circuit 5 are insulated (dielectric) separated by the buried oxide film 13 and the sidewall oxide film of the insulation isolation trench 11a, respectively. The SOI structure semiconductor substrate 10 is formed by bonding the substrates, and below the buried oxide film 13 is a thick support substrate 12 made of silicon (Si).

  In the level shift circuit 5 of the high voltage IC 1, a high voltage circuit element is required to connect the low potential reference circuit 2 and the high potential reference circuit 3. The N-channel LDMOS (Lateral Double-diffused MOS) 20 in the level shift circuit formation region shown in FIG. 9 has an SOI-RESURF structure in which the lateral breakdown voltage in the cross section is formed by the surface p-type impurity layer and the buried oxide film 13. To ensure. As for the breakdown voltage in the vertical direction of the cross section, as disclosed in Non-Patent Document 1, the high voltage applied between the drain D and the ground (GND) is divided between the low-concentration semiconductor layer 11 and the buried oxide film 13. The electric field in the semiconductor layer 11 is relaxed.

  By the way, in order to realize a high breakdown voltage semiconductor device using an SOI structure semiconductor substrate, the impurity concentration and thickness of the semiconductor layer and the thickness of the buried oxide film are optimally designed in order to ensure the breakdown voltage in the vertical direction of the cross section. There is a need to. However, to obtain a high breakdown voltage of 1000 V or higher with the configuration shown in FIG. 9, the buried oxide film 13 thicker than 5 μm and the semiconductor layer 11 thicker than 50 μm are required. On the other hand, the upper limit film thickness of the buried oxide film 13 that can be achieved due to the warpage of the SOI structure semiconductor substrate 10 is about 4 μm. Moreover, the thickness of the semiconductor layer 11 is usually about several μm to 20 μm, and the trench processing load increases when the thickness of the semiconductor layer 11 is increased. For this reason, the withstand voltage of about 600V is the limit, and the withstand voltage of 1200V required by the 400V power supply system, EV cars, etc. cannot be ensured.

  Therefore, in order to solve the above problem, the present applicant discloses Patent Document 2. In the semiconductor device disclosed in Patent Document 2, n transistor elements (n ≧ 2) that are insulated from each other are arranged between the GND potential and the predetermined potential Vs, the GND potential side being the first stage, and the predetermined potential Vs side. Are connected in series in order. The gate terminal of the first-stage transistor element is an input terminal of the semiconductor device, and the n resistance elements are between the GND potential and the predetermined potential Vs, and the GND potential side is the first stage and the predetermined potential. The Vs side is the nth stage, and they are sequentially connected in series. The gate terminals of the transistor elements of each stage excluding the transistor element of the first stage are sequentially connected to the voltage dividing points between the resistor elements of the respective stages connected in series, so that a predetermined potential of the n-th transistor element is obtained. An output is taken out from a terminal on the Vs side via a load resistor having a predetermined resistance value.

  Note that n transistor elements in the semiconductor device are formed in a semiconductor layer of an SOI structure semiconductor substrate having a buried oxide film. The n transistor elements are isolated from each other by an element isolation trench that reaches the buried oxide film. A plurality of field isolation trenches reaching the buried oxide film are formed, and n transistor elements insulated and isolated from each other are configured to include high-stage transistor elements in each field region surrounded by the field isolation trenches. Are sequentially arranged one by one.

Accordingly, the voltage applied to each field region surrounded by the field isolation trench is equalized in accordance with the voltage increase from the GND potential to the predetermined potential Vs, and the voltage range assigned to the n transistor elements is changed from the GND potential to the predetermined potential Vs. Can be shifted in order toward Therefore, even a transistor element having a normal breakdown voltage that can be manufactured at low cost using a general manufacturing method, a semiconductor that secures a high breakdown voltage required as a whole by appropriately setting the number n of transistor elements. It can be a device.
Japanese Patent No. 3384399 JP 2006-148058 A Proc. Of ISPSD '04, p385, H. Akiyama, et al (Mitsubishi Electric)

  In the configuration shown in Patent Document 2, the potential of each field region is not fixed and is a floating potential. In contrast, for example, in Japanese Patent Application No. 2006-102395, the present applicant fixed the potential of each field region to the same potential as any one of the three terminals of the transistor elements arranged in the field region. Filed a configuration.

  By the way, the support substrate constituting the SOI structure semiconductor substrate is generally fixed to the GND potential in order to stabilize the potential of the semiconductor layer stacked on the support substrate via the buried oxide film. However, in a configuration in which n transistor elements connected in series are arranged one by one in the field region, the potential difference between the potential of the field region and the potential of the support substrate (that is, the voltage applied to the buried oxide film) increases toward the predetermined potential Vs. ) Becomes larger.

  In view of the above problems, an object of the present invention is to provide a semiconductor device that can ensure an arbitrary withstand voltage and can improve the reliability of a buried oxide film.

  In order to achieve the above object, an invention according to claim 1 is directed to an element isolation trench that reaches a buried oxide film in a semiconductor layer in an SOI structure semiconductor substrate in which a semiconductor layer is stacked on a support substrate via a buried oxide film. N (n ≧ 2) transistor elements that are insulated and isolated from each other and multiple field isolation trenches reaching the buried oxide film are formed, and each of the n transistor elements is surrounded by each field region trench. In addition, one element is arranged with each of the element isolation trenches so as to include a high-stage or low-stage transistor element, and between the first predetermined potential and a second predetermined potential different from the first predetermined potential. The first predetermined potential side is connected in series with the first predetermined potential side as the first stage, and the second predetermined potential side as the nth stage. The potential is fixed to the same potential as any one of the three terminals of the transistor elements arranged in the region, the gate terminal of the first stage transistor element is used as the input terminal, and the n resistance elements or capacitance elements are connected to the first predetermined element. Each stage excluding the first stage transistor element is connected in series between the potential and the second predetermined potential, with the first predetermined potential side being the first stage and the second predetermined potential side being the nth stage. The gate terminal of each transistor element is sequentially connected between the resistor elements or the capacitor elements of each stage connected in series, and the output is taken out from the second predetermined potential side terminal of the n-th transistor element. This is a semiconductor device. In the support substrate, portions corresponding to the plurality of field regions are divided into a plurality of isolation regions by the support substrate isolation trench reaching the buried oxide film, and each isolation region is opposed to the field region via the buried oxide film. And is capacitively coupled.

  As described above, according to the present invention, the voltage between the first predetermined potential and the second predetermined potential is divided by n transistor elements, and compared with the configuration shared by one transistor element, The breakdown voltage required for each transistor element is approximately 1 / n. Therefore, even a transistor element having a normal breakdown voltage can be manufactured at low cost by using a general manufacturing method, and has a high breakdown voltage (DC breakdown voltage) required as a whole by appropriately setting the number n. A semiconductor device can be obtained.

  Further, portions of the support substrate corresponding to the plurality of field regions are divided into a plurality of isolation regions that are insulated from each other. Each isolation region is capacitively coupled to the opposing field region via a buried oxide film. That is, due to capacitive coupling, the potential is based on the field region where each separation region is opposed. Therefore, the maximum value of the potential difference between the field region and the support substrate can be reduced as compared with the configuration in which the support substrate is fixed to the first predetermined potential or the second predetermined potential. Thereby, the reliability of the buried oxide film can be improved.

  Note that the potential of each field region is fixed to the same potential as any one of the three terminals of the transistor elements arranged in the field region. That is, the potential of the field region is fixed to substantially the same potential as the transistor element in the element isolation trench arranged in the field region. Therefore, electric field concentration caused by the potential difference between the field region and the transistor element can be suppressed, and the breakdown voltage of each transistor element can be improved as compared with a state where the potential of the field region is not fixed (floating state). .

  Specifically, as described in claim 2, it is preferable that each separation region is divided according to the field region. As described above, when one isolation region is opposed to only one field region and one isolation region corresponds to one field region, the potential difference between the field region and the corresponding isolation region becomes almost zero. Therefore, the reliability of the buried oxide film can be further improved.

  According to a third aspect of the present invention, the support substrate may be divided so that the separation region is smaller than the field region and at least one separation region straddles a plurality of adjacent field regions. Even with such a configuration, the maximum value of the potential difference between the field region and the support substrate can be reduced, and the reliability of the buried oxide film can be improved.

  In the invention according to any one of claims 1 to 3, for example, as described in claim 4, the support substrate isolation trench may be filled with an insulating material. In addition, the support substrate isolation trench may be a gap that is not filled with an insulating material.

  Next, according to the fifth aspect of the present invention, in an SOI structure semiconductor substrate in which a semiconductor layer is stacked on a support substrate via a buried oxide film, the semiconductor layer is insulated from each other by an element isolation trench reaching the buried oxide film. N transistor elements (n ≧ 2) and multiple field isolation trenches reaching the buried oxide film are formed, and n transistor elements are formed in each field region surrounded by the field isolation trench. Alternatively, each element is arranged with element isolation trenches so as to contain a low-stage transistor element, and the first predetermined potential is different from the first predetermined potential and the second predetermined potential is different from the first predetermined potential. Are connected in series with the first potential side as the first stage and the second predetermined potential side as the nth stage, and the potential of each field region is arranged in the field region. It is fixed at the same potential as any one of the three terminals of the transistor element, the gate terminal of the first stage transistor element is used as the input terminal, and the n resistance elements or the capacitor elements are connected to the first predetermined potential and the second potential. The gates of the transistor elements in each stage except for the first stage transistor element are sequentially connected in series with the first predetermined potential side as the first stage and the second predetermined potential side as the nth stage. A semiconductor device having a structure in which terminals are sequentially connected between resistance elements or capacitive elements of respective stages connected in series, and an output is taken out from a second predetermined potential side terminal of the n-th transistor element. . The potential of the support substrate is fixed to a potential between the first predetermined potential and the second predetermined potential.

  As described above, also in the present invention, the voltage between the first predetermined potential and the second predetermined potential is divided by n transistor elements, and compared with the configuration shared by one transistor element, The breakdown voltage required for the transistor element is approximately 1 / n. Therefore, a semiconductor device having a high breakdown voltage required as a whole can be manufactured at low cost by using a general manufacturing method, and even if it is a transistor element having a normal breakdown voltage, by appropriately setting the number n, can do.

  Further, the potential of the support substrate is fixed to a potential between the first predetermined potential and the second predetermined potential. Therefore, the maximum value of the potential difference between the field region and the support substrate can be reduced as compared with the configuration in which the support substrate is fixed to the first predetermined potential or the second predetermined potential. Thereby, the reliability of the buried oxide film can be improved.

  Note that the potential of each field region is fixed to the same potential as any one of the three terminals of the transistor elements arranged in the field region. That is, the potential of the field region is fixed to substantially the same potential as the transistor element in the element isolation trench arranged in the field region. Therefore, electric field concentration caused by the potential difference between the field region and the transistor element can be suppressed, and the breakdown voltage of each transistor element can be improved as compared with a state where the potential of the field region is not fixed (floating state). .

  In a fifth aspect of the present invention, as in the sixth aspect, it is preferable that the potential of the support substrate is an intermediate potential between the first predetermined potential and the second predetermined potential. According to this, the maximum value of the potential difference between the field region and the support substrate is made smaller than the configuration in which the potential is biased to either the first predetermined potential or the second predetermined potential, and the reliability of the buried oxide film is reduced. The sex can be further improved.

  Specifically, as described in claim 7, the support substrate is electrically connected to a field region in which a predetermined-stage transistor element is disposed between the first-stage transistor element and the n-th transistor element. What is necessary is just to have a configuration. According to this, the configuration can be simplified.

  In addition, as described in claim 8, a plurality of support substrate resistance elements are connected in series between a first predetermined potential and a second predetermined potential, and the support substrate has a partial pressure between the support substrate resistance elements. It may be configured to be electrically connected to one of the points. As described above, the above-described configuration can be realized by a configuration in which the support substrate resistance element is provided separately from the resistance element.

  In the invention described in claim 8, as described in claim 9, the support substrate resistance element may be provided separately from the SOI structure semiconductor substrate. In addition, a configuration in which the SOI structure semiconductor substrate is provided integrally may be employed. Note that “integrated with an SOI structure semiconductor substrate” means a state where it is formed inside or on the surface of a support substrate or a semiconductor layer.

  Further, in the invention described in claim 9, as described in claim 10, the supporting substrate resistance element may be integrally molded together with the SOI structure semiconductor substrate. In addition, for example, a holding substrate resistance element may be fixed on a mold package including an SOI structure semiconductor substrate.

  In the invention according to any one of claims 1 to 10, as described in claim 11, the potential of each field region is the same as the gate terminal among the three terminals of the transistor elements disposed in the field region. A configuration in which the potential is fixed is preferable.

  With such a configuration, since the gate terminal and the field region are electrically connected, the potentials of the remaining two terminals are not affected by the parasitic capacitance. Therefore, even with a P-channel transistor element, the delay time and the occurrence of spikes can be eliminated. In addition, the potential of each field region is fixed at a potential that is evenly divided by a resistance element or a capacitance element. Therefore, the maximum value of the potential difference between the field region and the support substrate can be further reduced. Further, it is possible to improve the voltage deviation of the transistor elements at each stage when the dV / dt surge is applied. That is, it is possible to improve the dV / dt surge resistance.

  In the invention according to any one of claims 1 to 11, as described in claim 12, a GND reference gate drive circuit based on the GND potential, a floating reference gate drive circuit based on the floating potential, and a GND potential In a high voltage IC for driving an inverter including a level shift circuit for level-shifting an input / output signal between a first potential and a floating potential, one of a first predetermined potential and a second predetermined potential is a GND potential and the other is a floating potential By using a potential, it is suitable for a level shift circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same reference numerals are given to the same elements as those constituting the semiconductor device shown in the conventional example.
(First embodiment)
FIG. 1 is a plan view showing a schematic configuration of a high-voltage IC including a semiconductor device according to each of the following embodiments. FIG. 2 is a diagram illustrating a schematic configuration of the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view showing a characteristic portion of the semiconductor device. In FIG. 3, transistor elements and element isolation trenches are omitted. The basic configuration of the semiconductor device shown below is the same as that of Japanese Patent Application Laid-Open No. 2006-148058 and Japanese Patent Application No. 2006-102395 by the applicant of the present application. Therefore, detailed description of the basic configuration and operation is omitted. The part will be described in detail.

  A high voltage IC 1 shown in FIG. 1 is a high voltage IC for driving an inverter, and includes a GND reference gate drive circuit 2 based on the GND potential, a floating reference gate drive circuit 3 based on the floating potential, and a GND reference gate drive circuit 2. And the control circuit 4 for controlling the floating reference gate drive circuit 3 and the control circuit 4 between the control circuit 4 and the floating reference gate drive circuit 3, and the input / output signals of the control circuit 4 are leveled between the GND potential and the floating potential. The level shift circuit 5 is configured to shift. In FIG. 1, the GND reference gate drive circuit 2, the floating reference gate drive circuit 3, the control circuit 4, and the level shift circuit 5 are integrated on one substrate 6. A semiconductor device 100 described below is applied to the level shift circuit 5.

  As shown in FIG. 3, the semiconductor device 100 includes an SOI structure semiconductor substrate 10 in which a semiconductor layer 11 is stacked on a support substrate 12 with a buried oxide film 13 interposed therebetween. As shown in FIG. 2, n (n ≧ 2, 4 in this embodiment) transistor elements 21 to 24 are formed in the semiconductor layer 11. In the present embodiment, P-channel LDMOS (Lateral Double-diffused MOS) is employed as the transistor elements 21 to 24. Moreover, the three terminals, the source 31, the gate 32, and the drain 33 which comprise each transistor element 21-24 become a pattern arrange | positioned concentrically as shown in FIG.

  The transistor elements 21 to 24 are surrounded by element isolation trenches 41 to 44 that reach the buried oxide film 13, and are thereby insulated and isolated from each other. In the present embodiment, the element isolation trenches 41 to 44 are arranged concentrically with the terminals 31 to 33 described above. Note that an element isolation trench 41 is formed in the first stage transistor element 21 and an element isolation trench 44 is formed in the fourth stage transistor element 24.

  The semiconductor layer 11 has a plurality of field isolation trenches 51 to 54 reaching the buried oxide film 13. Then, in each field region 61 to 64 surrounded by the field isolation trenches 51 to 54, the transistor elements 21 to 24 include a transistor element of a subsequent stage or a low stage (low stage in the present embodiment), One by one is sequentially arranged together with corresponding element isolation trenches 41 to 44. As described above, in this embodiment, the P-channel type LDMOS is employed, and therefore, the transistor element 21 surrounded by the element isolation trench 41 is disposed in the first-stage field region 61. In the field region 64 of the fourth stage, the transistor elements 24 surrounded by the element isolation trench 44 are arranged together with the field regions 61 to 63 which are low stages.

  As shown in FIG. 2, a field region 65 that is partitioned by a field isolation trench 55 and encloses each field region 61 to 64 is formed outside the fourth-stage field region 64. In 65, a GND pad and an output pad are formed. Further, a field region 66 partitioned by a field isolation trench 56 is formed in the first-stage field region 61, and a power pad and an input pad are formed in the field region 66.

  Each of the transistor elements 21 to 24 has a power supply potential Vcc side between a power supply potential Vcc as a first predetermined potential and a GND potential as a second predetermined potential different from the first predetermined potential. The first stage and the GND potential side are sequentially connected in series with the nth stage (fourth stage). In this embodiment, since each of the transistor elements 21 to 24 is a MOS transistor, the lower drain voltage is applied to the source 31 of the upper stage. In addition, n (four in this embodiment) resistance elements 71 to 74 correspond to the transistor elements 21 to 24, and the power supply potential Vcc side is the first stage between the power supply potential Vcc and the GND potential. The GND potential side is sequentially connected in series with the fourth stage. The gate 31 in the first stage transistor element 21 is input, and the gate 31 in each stage transistor element 22 to 24 excluding the first stage transistor element 21 is connected in series to each stage resistance element 71. Are sequentially connected to the voltage dividing points between .about.74, and the output is taken out from the GND potential side terminal of the fourth stage transistor element 24. FIG. Specifically, an output resistor 75 is connected between the fourth-stage transistor element 24 and the GND pad so that an output can be taken out between the drain 33 and the output resistor 75 of the fourth-stage transistor element 24. Yes. That is, the output signal is extracted in a state where the reference potential is converted (level shift) from the power supply potential Vcc of the input signal to the GND potential and inverted with respect to the input signal. In the present embodiment, the voltage is divided by the resistance elements 71 to 74, but may be divided by the capacitive element. Further, the voltage may be divided by the resistance element and the capacitance element.

  In the case of a P-channel type LDMOS as shown in this embodiment, when the potential of the source 31 of the transistor elements 21 to 24 is higher than the potential of the gate 32, the transistor elements 21 to 24 are turned on. Therefore, for example, when the power supply voltage Vcc is 1200 V, a signal having a voltage (for example, 1195 V) lower than that of the source 31 is input to the gate 32 in the first-stage transistor element 21. Thereby, the transistor element 21 is turned on. The voltage input to the gate 32 of the second stage transistor element 22 is lower than the gate 32 of the first stage transistor element 21 by the amount of the first stage resistance element 71. Accordingly, the first-stage transistor element 21 is turned on, and the potential of the source 31 is higher than the potential of the gate 32 in the second-stage transistor element 22. That is, the second stage transistor element 22 is turned on. This operation is repeated in the same manner up to the transistor element 24 in the n-th stage (fourth stage in the present embodiment), and all the transistor elements 21 to 24 are turned on in a very short time.

  As described above, according to the semiconductor device 100 according to the present embodiment, the voltage applied to the field regions 61 to 64 surrounded by the multiple field isolation trenches 51 to 54 in accordance with the voltage drop from the power supply potential Vcc to the GND potential. And the voltage ranges assigned to the transistor elements 21 to 24 can be shifted in order from the power supply potential Vcc to the GND potential. In other words, the voltage between the power supply potential Vcc and the GND potential is divided by the plurality of transistor elements 21 to 24, and the transistor elements 21 to 24 in the first to fourth stages share their respective voltage ranges. Yes. Therefore, compared to the case where the voltage between the power supply potential Vcc and the GND potential is shared by one transistor element, the static withstand voltage (DC withstand voltage) required for each transistor element 21 to 24 can be reduced. In other words, by appropriately setting the number of transistor elements, it is possible to obtain a semiconductor device that ensures a high breakdown voltage required as a whole.

  In the present embodiment, an example (four-stage example) in which the semiconductor device 100 includes four transistor elements 21 to 24 is shown. However, the number is not particularly limited. When the breakdown voltage of each transistor element is 200 V or less, the semiconductor device 100 can be manufactured at low cost by using a general manufacturing method.

  Further, in the present embodiment, the field regions 61 to 64 are insulated and separated, and the field isolation trenches 51 to 54 disposed between the adjacent transistor elements 21 to 24 are formed as a single far isolation trench. . Therefore, the connection wiring of the transistor elements 21 to 24 can be facilitated, the occupied area can be reduced, and the semiconductor device 100 can be downsized. However, at least one of the field isolation trenches 51 to 54 may be multiple far isolation trenches.

  In the present embodiment, the transistor elements 21 to 24 have the same breakdown voltage. Thereby, the voltage (withstand voltage) shared by each element inserted between the GND potential and the power supply potential Vcc can be equalized and minimized.

  Moreover, in this embodiment, as shown in FIG.2 and FIG.3, the electric potential of each field area | region 61-64 is made out of each 3 terminal of the transistor elements 21-24 arrange | positioned in this field area | region 61-64. It is fixed at the same potential as the gate 32. Therefore, the electric field concentration caused by the potential difference between the field regions 61 to 64 and the transistor elements 21 to 24 can be suppressed. As compared with a state where the potentials of the field regions 61 to 64 are not fixed (floating state), it is possible to improve the static withstand voltage (DC withstand voltage) of each of the transistor elements 21 to 24 and ensure a high static withstand voltage as a whole. it can. In particular, in the present embodiment, as described above, the potentials of the field regions 61 to 64 are fixed to the same potential as that of the gate 32. Therefore, the potential of the remaining two terminals (source 31 or drain 33) is not affected by the parasitic capacitance. Therefore, even with a P-channel transistor element, the delay time and the occurrence of spikes can be eliminated. In addition, since the potentials of the field regions 61 to 64 are fixed at potentials that are evenly divided by the resistance elements 71 to 74, the voltage deviation of the transistor elements 21 to 24 at each stage when the dV / dt surge is applied is reduced. Can be improved. That is, it is possible to improve the dV / dt surge resistance. Since the above points are described in detail in Japanese Patent Application No. 2006-102395, please refer to them.

  Further, in the present embodiment, as shown in FIG. 3, the support substrate in which the portions corresponding to the plurality of field regions 61 to 64 among the support substrate 12 constituting the SOI structure semiconductor substrate 10 reach the buried oxide film 13. The separation trenches 111 to 114 are divided into a plurality of separation regions 101 to 104. The isolation regions 101 to 104 are capacitively coupled to the opposing field regions 61 to 64 through the buried oxide film 13. More specifically, support substrate isolation trenches 111 to 114 are formed corresponding to the field isolation trenches 51 to 54, whereby the isolation regions 101 to 104 are divided corresponding to the field regions 61 to 64. That is, one isolation region 101-104 is opposed to only one field region 61-64, and one isolation region 101-104 corresponds to one field region 61-64. Therefore, if the potentials of the field regions 61 to 64 are V1 to V4, respectively, the potentials of the separation regions 101 to 104 of the support substrate 12 are substantially equal to the potentials of the opposing field regions 61 to 64 due to capacitive coupling. Become.

  Thus, according to the semiconductor device 100 according to the present embodiment, portions of the support substrate 12 corresponding to the plurality of field regions 61 to 64 are divided into the plurality of isolation regions 101 to 104 that are insulated from each other. Yes. The potential is based on the field regions 61 to 64 facing the separation regions 101 to 104 by capacitive coupling. Therefore, the maximum value of the potential difference between the field regions 61 to 64 and the support substrate 12 can be reduced as compared with the configuration in which the support substrate 12 is fixed to the power supply potential Vcc or the GND potential. In particular, in the present embodiment, since the separation regions 101 to 104 are divided corresponding to the field regions 61 to 64, the maximum value of the potential difference between the field regions 61 to 64 and the support substrate 12 can be further reduced. it can. Specifically, in FIG. 3, the potential V1 of the field region 61 is approximately 1200 V, and the potential of the separation region 101 of the opposing support substrate 12 is also substantially the same as V1. That is, the potential difference is almost zero. In addition, the potential difference between the separation regions 102 to 104 facing the other field regions 62 to 64 is substantially zero. Specifically, in this embodiment, the transistor elements 21 to 24 have the same configuration, and the resistance elements 71 to 74 have the same configuration. Accordingly, the voltages are evenly divided so that the potentials V1 and V6 are approximately 1200V, the potential V2 is approximately 900V, the potential V3 is approximately 600V, the potential V4 is approximately 300V, and the potential V5 is approximately 0V.

  On the other hand, when the support substrate 12 is not separated and is fixed to the GND potential, for example, a potential difference of approximately 1200 V is generated between the field region 61 and the support substrate 12.

  Further, in the present embodiment, as shown in FIG. 3, portions of the support substrate 12 corresponding to a field region 65 in which a GND pad and an output pad are formed and a field region 66 in which a power pad and an input pad are formed. In addition, the isolation regions 105 and 106 are isolated from the isolation regions 101 to 104 by the support substrate isolation trenches 114 and 116 reaching the buried oxide film 13. The potentials of the isolation regions 105 and 106 are substantially the same as the potentials V5 and V6 of the field regions 65 and 66 due to capacitive coupling. Therefore, the maximum value of the potential difference between the field regions 61 to 64 and the support substrate 12 can be further reduced. However, the separation region 105 may be integrated with the separation region 104 without being separated, and the separation region 106 may be integrated with the separation region 101 without being separated. Further, since the potential V4 of the field region 64 and the potential V5 of the field region 65 are different by the resistance element 74, the separation region 104 and the separation region 105 are separated, and the separation region 106 is not separated and is integrated with the separation region 101. It is good also as a structured.

  Moreover, in this embodiment, as shown in FIG. 3, the support substrate isolation | separation trench 111-114,116 showed the example which is a space | gap which is not filled with an insulating material inside a trench. However, the trench may be filled with an insulating material such as polycrystalline silicon or silicon oxide.

  In the present embodiment, an example in which a P-channel type LDMOS is employed as the transistor elements 21 to 24 is shown. However, as shown in FIG. 4, an N-channel LDMOS having higher carrier mobility than the P-channel may be employed. In this case, as shown in FIG. 4, the GND potential becomes the first predetermined potential, and the power supply potential Vcc becomes the second predetermined potential. The transistor elements 21 to 24 are sequentially connected in series between the GND potential and the power supply potential Vcc, with the GND potential side as the first stage and the power supply potential side as the nth stage (fourth stage in FIG. 4). . The field regions 61 to 64 are provided so as to include a higher-level field region. A power pad and an output pad are formed in the field region 65, and a GND pad and an input pad are formed in the field region 66. FIG. 4 is a diagram illustrating a modification.

  In the present embodiment, the potential of each field region 61 to 64 is the same as that of the gate 32 of the transistor elements 21 to 24 disposed in the field regions 61 to 64 via the element isolation trenches 41 to 44. An example to be shown. However, a configuration in which the potential is the same as that of the source and the drain may be employed. The effect of each configuration is described in detail in Japanese Patent Application No. 2006-102395, so please refer to it.

(Second Embodiment)
Next, a second embodiment of the present invention will be described based on FIG. FIG. 5 is a cross-sectional view illustrating a schematic configuration of the semiconductor device according to the second embodiment.

  Since the semiconductor device according to the second embodiment is often in common with the semiconductor device shown in the first embodiment, the detailed description of the common parts will be omitted below, and different parts will be described mainly. In addition, the same code | symbol shall be provided to the element same as the element shown in 1st Embodiment.

  In the first embodiment, support substrate isolation trenches 111 to 114 are formed corresponding to the field isolation trenches 51 to 54, whereby the isolation regions 101 to 104 are divided corresponding to the field regions 61 to 64. An example is shown. In contrast, in the present embodiment, the separation region is smaller than the field region, and the support substrate 12 is divided so that at least one separation region straddles a plurality of adjacent field regions. Features.

  As an example, in FIG. 5, the support substrate 12 includes a separation region 101 facing the first-stage field region 61, a separation region 106 facing the field region 66, the entire second-stage field region 62, and the third-stage field. Are separated into a separation region 107 facing a part of the field region 63, a part of the field region of the third stage, a whole field region 64 of the fourth stage, and a separation region 108 facing the field region 65. Therefore, the isolation regions 101 and 106 have substantially the same potential as the opposing field regions 61 and 66 due to capacitive coupling. In addition, the separation region 107 that straddles the two field regions 62 and 63 is at a potential between the potentials V2 and V3 of the field regions 62 and 63 (approximately the midpoint potential of the potentials V2 and V3). In addition, the isolation region 108 across the three field regions 63 to 65 is at a potential between the potentials V3 to V5 of the field regions 63 to 65 (approximately the midpoint potential of the potentials V3 to V5).

  As described above, also in the semiconductor device 100 according to the present embodiment, the maximum value of the potential difference between the field regions 61 to 64 (the field regions 61 to 66 in the present embodiment) and the support substrate 12 is reduced, and the buried oxide film 13 is reduced. Reliability can be improved. In addition, the number of support substrate isolation trenches 111, 116, and 117 can be reduced. However, if the configuration is such that a plurality of field regions having a potential difference are straddled, the potential of the isolation region is affected by each field region, so that the maximum value of the potential difference between the field region and the support substrate 12 becomes smaller as the number of transistor elements decreases. growing. Therefore, it is advantageous in a configuration having a large number of transistor elements.

(Third embodiment)
Next, a second embodiment of the present invention will be described based on FIG. FIG. 6 is a cross-sectional view illustrating a schematic configuration of the semiconductor device according to the third embodiment.

  Since the semiconductor device according to the third embodiment is common in common with the semiconductor device shown in the first embodiment, a detailed description of the common parts will be omitted below, and different parts will be described mainly. In addition, the same code | symbol shall be provided to the element same as the element shown in 1st Embodiment.

  In each embodiment mentioned above, the example which makes small the electric potential difference between the field fields 61-64 which oppose by dividing | segmenting the support substrate 12 was shown. On the other hand, in the present embodiment, the potential of the support substrate 12 is fixed to a potential between the first predetermined potential and the second predetermined potential without dividing the support substrate 12. And

  In FIG. 6 shown as an example, the configuration of the SOI structure semiconductor substrate 10 is the same as that of the modification of the first embodiment (see FIG. 4) except that the support substrate 12 is not divided. The SOI structure semiconductor substrate 10 is fixed to the base 121 made of a conductive material (for example, metal) so as to be conductive with the support substrate 12 as a contact surface (for example, bonded by solder or Ag paste). In addition, the field region 63 and the base 121 in a predetermined stage (the third stage in FIG. 6) between the first stage and the n-th stage (the fourth stage in FIG. 6) are electrically connected via the wire 124. It is connected to the. That is, the support substrate 12 is at the same potential as the field region 63. The field region 65 is electrically connected to the power supply side lead 123 via the wire 124, and the field region 66 is electrically connected to the GND side lead 122 via the wire 124. In this connection state, the SOI structure semiconductor substrate 10, the base 121, the wires 124, and the leads 122 and 123 are partially covered with the mold resin 130 to constitute the semiconductor device 100.

  Thus, according to the semiconductor device 100 according to the present embodiment, the potential of the support substrate 12 is fixed to a potential between the GND potential and the power supply potential Vcc. Therefore, the maximum value of the potential difference between each field region 61 to 64 (in this embodiment, each field region 61 to 66) and the support substrate 12 as compared with the configuration in which the support substrate 12 is fixed to the GND potential or the power supply potential Vcc. Can be reduced. Thereby, the reliability of the buried oxide film 13 can be improved.

  In the present embodiment, the voltage dividing resistors (not shown) all have the same configuration, and the potential of the third-stage field region 63 is substantially equal to the intermediate potential between the GND potential and the power supply potential Vcc. It is at electric potential. Therefore, the maximum potential difference between the field regions 61 to 64 (in the present embodiment, the field regions 61 to 66) and the support substrate 12 is compared with a configuration in which the potential is biased to either the GND potential or the power supply potential Vcc. The value can be made smaller.

  In the present embodiment, the field region of the predetermined stage (the third stage in FIG. 6) between the first stage and the nth stage (the fourth stage in FIG. 6) and the support substrate 12 are electrically connected. As a result, the potential of the support substrate 12 is set to a potential between the GND potential and the power supply potential Vcc. Therefore, the configuration can be simplified.

  However, in addition to the above-described configuration, for example, a plurality of support substrate resistance elements are connected in series between the first predetermined potential and the second predetermined potential, and the support substrate 12 has a partial pressure between the support substrate resistance elements. It may be configured to be electrically connected to one of the points. For example, in FIG. 7, apart from the SOI structure semiconductor substrate 10, there are two support substrate resistance elements 131 and 132 connected in series with each other, and one terminal of the support substrate resistance element 131 is connected to the lead 122. One terminal of the support substrate resistance element 132 is connected to the lead 123. The voltage dividing points of the support substrate resistance elements 131 and 132 and the base 121 are electrically connected via a wire 124. 7 shows an example in which the support substrate resistance elements 131 and 132 are provided separately from the SOI structure semiconductor substrate 10, the SOI structure semiconductor substrate 10 (inside or on the surface of the semiconductor layer 11 or the support substrate 12). Further, the support substrate resistance element may be formed. Further, the number of supporting substrate resistance elements is not limited to two. FIG. 7 is a cross-sectional view showing a modification.

  FIG. 7 shows an example in which support substrate resistance elements 131 and 132 configured separately from the SOI structure semiconductor substrate 10 are disposed in the mold resin 130 and sealed. However, as shown in FIG. 8, the support substrate resistance elements 131 and 132 may be arranged outside the mold resin 130. In FIG. 8, support substrate resistance elements 131 and 132 are bonded and fixed to the lower surface of mold resin 130 (support substrate 12 side), and one terminal of support substrate resistance element 131 is connected to lead 122 for support. One terminal of the substrate resistance element 132 is connected to the lead 123. The voltage dividing points of the support substrate resistance elements 131 and 132 and the leads 125 are electrically connected via the wires 124, and the leads 125 and the base 121 are electrically connected via the wires 124. Yes. FIG. 8 is a cross-sectional view showing a modification. 8 shows an example in which the support substrate resistance elements 131 and 132 are bonded and fixed to the lower surface (the support substrate 12 side) of the mold resin 130, but the fixing position is not particularly limited. A configuration may be adopted in which the mold resin 130 is bonded and fixed to the upper surface (the semiconductor layer 11 side) or the side surface.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  In this embodiment, the example which employ | adopts LDMOS as a transistor element was shown. However, MOS transistor elements other than LDMOS can also be employed. In addition to MOS transistor elements, IGBT (Insulated Gate Bipolar Transistor) elements can also be employed.

It is a top view which shows schematic structure of the high voltage IC containing the semiconductor device which concerns on each embodiment. 1 is a diagram illustrating a schematic configuration of a semiconductor device according to a first embodiment. It is sectional drawing which shows the characteristic part among semiconductor devices. It is a figure which shows a modification. It is sectional drawing which shows schematic structure of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows schematic structure of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification. It is typical sectional drawing of the conventional high voltage IC.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Semiconductor layer 12 ... Support substrate 13 ... Embedded oxide film 21-24 ... Transistor element 41-44 ... Element isolation trench 51-54 ... Field isolation trench 61-64 ... Field regions 71 to 74... Resistive element 100... Semiconductor devices 101 to 104... Isolation regions 111 to 114.

Claims (12)

In an SOI structure semiconductor substrate in which a semiconductor layer is stacked on a support substrate through a buried oxide film, n (n ≧ 2) that are isolated from each other by element isolation trenches reaching the buried oxide film in the semiconductor layer. A transistor element and a plurality of field isolation trenches reaching the buried oxide film are formed,
The n transistor elements are arranged one by one together with the element isolation trench in each field region surrounded by the field isolation trench so as to enclose high-stage or low-stage transistor elements. Between the predetermined potential and a second predetermined potential different from the first predetermined potential, the first predetermined potential side is connected in series with the first predetermined potential side as the first stage and the second predetermined potential side as the nth stage. ,
The potential of each field region is fixed to the same potential as any one of the three terminals of the transistor element disposed in the field region,
The gate terminal in the first stage transistor element is an input terminal,
n resistance elements or capacitive elements between the first predetermined potential and the second predetermined potential, the first predetermined potential side being the first stage and the second predetermined potential side being the nth stage Sequentially connected in series, the gate terminals of the transistor elements of each stage excluding the first stage transistor element are sequentially connected between the resistor elements or capacitive elements of the stages connected in series, respectively.
A semiconductor device configured to extract an output from a terminal on the second predetermined potential side in the n-th transistor element;
Of the support substrate, portions corresponding to the plurality of field regions are divided into a plurality of isolation regions by support substrate isolation trenches reaching the buried oxide film, and each isolation region is opposed to the buried oxide film via the buried oxide film. A semiconductor device which is capacitively coupled to a field region.   The semiconductor device according to claim 1, wherein the isolation region is divided corresponding to the field region.   2. The support substrate according to claim 1, wherein the separation substrate is smaller than the field region, and the support substrate is divided so that at least one of the separation regions straddles a plurality of adjacent field regions. Semiconductor device.   The semiconductor device according to claim 1, wherein an insulating material is filled in the support substrate isolation trench. In an SOI structure semiconductor substrate in which a semiconductor layer is stacked on a support substrate through a buried oxide film, n (n ≧ 2) that are isolated from each other by element isolation trenches reaching the buried oxide film in the semiconductor layer. A transistor element and a plurality of field isolation trenches reaching the buried oxide film are formed,
The n transistor elements are arranged one by one together with the element isolation trench in each field region surrounded by the field isolation trench so as to enclose high-stage or low-stage transistor elements. Between the predetermined potential and a second predetermined potential different from the first predetermined potential, the first predetermined potential side is connected in series with the first predetermined potential side as the first stage and the second predetermined potential side as the nth stage. ,
The potential of each field region is fixed to the same potential as any one of the three terminals of the transistor element disposed in the field region,
The gate terminal in the first stage transistor element is an input terminal,
n resistance elements or capacitive elements between the first predetermined potential and the second predetermined potential, the first predetermined potential side being the first stage and the second predetermined potential side being the nth stage Sequentially connected in series, the gate terminals of the transistor elements of each stage excluding the first stage transistor element are sequentially connected between the resistor elements or capacitive elements of the stages connected in series, respectively.
A semiconductor device configured to extract an output from a terminal on the second predetermined potential side in the n-th transistor element;
The semiconductor device according to claim 1, wherein the potential of the support substrate is fixed to a potential between the first predetermined potential and the second predetermined potential.   6. The semiconductor device according to claim 5, wherein the potential of the support substrate is an intermediate potential between the first predetermined potential and the second predetermined potential.   The support substrate is electrically connected to the field region in which the transistor elements at a predetermined stage are disposed between the first-stage transistor element and the n-th transistor element. The semiconductor device according to claim 5 or 6. A plurality of support substrate resistance elements are connected in series between the first predetermined potential and the second predetermined potential,
The semiconductor device according to claim 5, wherein the support substrate is electrically connected to one of voltage dividing points between the support substrate resistance elements.   The semiconductor device according to claim 8, wherein the support substrate resistance element is provided separately from the SOI structure semiconductor substrate.   The semiconductor device according to claim 9, wherein the supporting substrate resistance element is integrally molded together with the SOI structure semiconductor substrate.   11. The potential of each field region is fixed at the same potential as the gate terminal among the three terminals of the transistor elements arranged in the field region. A semiconductor device according to 1. For inverter driving including a GND reference gate drive circuit based on the GND potential, a floating reference gate drive circuit based on the floating potential, and a level shift circuit for level-shifting input / output signals between the GND potential and the floating potential In the high voltage IC of
12. The level shift circuit according to claim 1, wherein one of the first predetermined potential and the second predetermined potential is the GND potential and the other is the floating potential, and is applied to the level shift circuit. 2. A semiconductor device according to item 1.

Images