JP2008243910A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a layout capable of achieving the stabilization of gate protective characteristics and an improvement in the degree of integration of the integrated circuit without using a Zener diode having a plurality of breakdown voltages corresponding to the gate breakdown voltage of a transistor. <P>SOLUTION: The semiconductor integrated circuit has a high breakdown voltage output circuit having a push-pull circuit consisting of a high-side transistor and a low-side transistor, a level shift circuit and a gate protective circuit. The gate protective circuit has a voltage-dividing resistor dividing the breakdown voltage by the Zener diode and the Zener diode consisting of a P-type impurity region doped by P-type impurities. The voltage-dividing resistor is arranged so as to be surrounded by an N-type impurity region doped by N-type impurities. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a layout of a multi-channel semiconductor integrated circuit for driving a capacitive load such as a plasma display.

  As a high voltage output circuit used in a conventional multi-channel semiconductor integrated circuit, a circuit shown in FIG. 14 is generally known.

  As shown in FIG. 14, the high withstand voltage output circuit 127 includes a push-pull circuit 7 including a high-side transistor 12, a parasitic gate-source capacitance 11 of the high-side transistor 12, and a low-side transistor 13, and a Zener diode 9. And a gate protection circuit 8 that protects the gate of the high-side transistor 12, thick-film gate P-type MOS transistors 14 and 15, and thin-film gate N-type MOS transistors 16 and 17. The level shift circuit 6 drives the side transistor 12.

  Reference numeral 5 denotes a pre-driver that drives the level shift circuit 6 and the low-side transistor 13, reference numeral 4 denotes an output terminal of the push-pull circuit 7, reference numeral 3 denotes a terminal of a high-voltage power supply of 100 V or higher, and reference numeral 2 denotes This is a terminal for a low voltage power supply of about 5V.

  The operation of the high withstand voltage output circuit 127 having the above configuration will be described with reference to FIG.

  FIG. 15 is a timing chart for explaining the operation of the conventional high withstand voltage output circuit 127.

  In FIG. 15, the voltage waveform of the input signal IN input from the low withstand voltage control unit input to the input terminal IN and the output signals IN1 and IN2 of the pre-driver 5 that drives the level shift circuit 6 according to the input signal IN. Level shift circuit that drives the voltage waveform, the voltage waveform of the output signal IN3 of the pre-driver 5 that drives the low-side transistor 13 according to the input signal IN, and the high-side transistor 12 according to the output signals IN1 and IN2 of the pre-driver 5 6, the voltage waveform of the gate-source voltage GH of the high-side transistor 12 determined according to the output signal IN 4 of the level shift circuit 6 and the gate protection circuit 8, and the gate-source voltage. The output terminal OUT of the push-pull circuit 7 output in response to the GH and the output signal IN3 of the pre-driver 5 It shows the voltage waveform.

  Here, when a GND level signal is input to the input signal IN and the input terminal IN becomes L level (GND), the output signal IN1 becomes H level (VDD), and the output signal IN2 becomes L level (GND). The output signal IN4 becomes L level (GND). In this case, the Zener diode 9 becomes forward biased, and the gate voltage-source voltage GH becomes OUT-VFD (Zener forward voltage) to rapidly discharge the parasitic gate capacitance 11, and the threshold voltage of the high side transistor 12 is increased. By being equal to or lower than Vth (N1), the high side transistor 12 is turned off. Thereafter, the gate voltage-source voltage GH is returned to the same potential as the output terminal OUT by the first resistor 10. Further, the output signal IN3 becomes H level (VDD) to turn on the low-side transistor 13, and the output terminal OUT becomes L level (GND).

Next, when a VDD level signal is input to the input signal IN and the input terminal IN becomes H level (VDD), the output signal IN1 becomes L level (GND), and the output signal IN2 becomes H level (VDD). The output signal IN4 becomes H level (VDDH) and the parasitic gate capacitance 11 is rapidly charged, and the gate-source voltage GH becomes OUT + Vz (breakdown voltage) by the Zener diode 9, and the threshold voltage of the high side transistor 12 is reached. By being equal to or higher than Vth (N1), the high side transistor 12 is turned on. Further, the output signal IN3 becomes L level (GND) and the low side transistor 13 is turned off, and the output signal OUT becomes H level (VDDH).
Japanese Patent Laying-Open No. 2005-20142 (FIG. 4)

  However, according to the high breakdown voltage output circuit 127 of the multi-channel semiconductor integrated circuit, since the gate oxide film of the high side transistor 12 is thin, the level shift circuit 6 having an amplitude from GND to VDDH exceeds the gate breakdown voltage. The gate voltage is limited by the Zener diode 9 of the gate protection circuit 8 so as not to be present. For this reason, the devices that can be used with the breakdown voltage of the Zener diode 9 are limited. For example, when it is desired to provide a transistor for the purpose of improving the saturation current per unit area and improving the switching speed to be turned on, the threshold value to be turned on When the thickness of the gate oxide film is made thinner for the purpose of lowering the voltage, there is a problem that it is necessary to add a device having a low breakdown voltage because the gate breakdown voltage is also lowered.

In general, when the breakdown voltage is 5 V or less, there is also a problem that variation due to current flowing in the diode is large. (The breakdown voltage varies greatly depending on the current that flows)
In view of the above, an object of the present invention is to provide a multi-channel semiconductor integrated circuit having a high-voltage output circuit that is optimally laid out as a standard cell without producing a Zener diode having a plurality of breakdown voltages in accordance with the gate breakdown voltage. It is to be.

  To achieve the above object, a semiconductor integrated circuit according to a first embodiment of the present invention includes a push-pull circuit including a high-side transistor having a thin film gate oxide film and a low-side transistor having a thin film gate oxide film. , A semiconductor integrated circuit comprising a level shift circuit and a high withstand voltage output circuit having a gate protection circuit connected between the output of the level shift circuit and the output of the push-pull circuit, the gate protection circuit comprising: A diode, and a first resistor and a second resistor connected in series, each of which includes a P-type impurity region doped with a P-type impurity, and a voltage dividing resistor that divides a breakdown voltage by the Zener diode. The divided potential at the connection point between the first resistor and the second resistor is applied to the gate of the high-side transistor. , The first resistor and the second resistor, an N-type impurity is disposed so as to be surrounded by the doped N-type impurity regions.

  In the semiconductor integrated circuit according to the first aspect of the present invention, each of the first resistor and the second resistor is individually surrounded by the N-type impurity region and is individually separated by different SOIs. Yes.

  In the semiconductor integrated circuit according to the first aspect of the present invention, each of the first resistor and the second resistor is individually surrounded by the N-type impurity region and is integrally separated by the same SOI. Yes.

  In the semiconductor integrated circuit according to the first embodiment of the present invention, the corners of the N-type impurity region and the voltage dividing resistor are rounded.

  In the semiconductor integrated circuit according to the first aspect of the present invention, the first resistor and the second resistor are configured by a single resistor, and the single resistor has a three-terminal electrode. ing.

  The semiconductor integrated circuit according to the first embodiment of the present invention includes a plurality of circuit cells each including a high voltage output circuit further including a pad on a semiconductor chip, and the circuit cell includes a level shift circuit, a gate protection circuit, and a high side. The transistor, the low-side transistor, and the pad are arranged on a straight line.

  The semiconductor integrated circuit according to the first aspect of the present invention further includes a control unit disposed in a central portion of the semiconductor chip, and the plurality of circuit cells are disposed so as to face each other via the control unit. The first circuit cell array and the second circuit cell array each having a plurality of withstand voltage output circuits.

  In the semiconductor integrated circuit according to the first aspect of the present invention, the first power supply pad for the high voltage potential and the first for the reference potential are arranged at both ends of each of the first circuit cell row and the second circuit cell row. Two power supply pads, a first wiring having a high voltage potential disposed on each of the high-side transistors in the first circuit cell row and the second circuit cell row and electrically connected to the first power supply pad, And a second wiring having a reference potential disposed on each low-side transistor in the first circuit cell column and the second circuit cell column and electrically connected to the second power supply pad.

  The semiconductor integrated circuit according to the first aspect of the present invention further includes a third wiring having a reference potential arranged so as to surround the control unit arranged in the central portion of the semiconductor substrate.

  In the semiconductor integrated circuit according to the first embodiment of the present invention, the level shift circuit, the gate protection circuit, and the high side transistor are designed to be within the cell width of the low side transistor.

  In the semiconductor integrated circuit according to the first aspect of the present invention, the Zener diode and the voltage dividing resistor are arranged adjacent to each other in the width direction of the high withstand voltage output circuit.

  A semiconductor integrated circuit according to the second embodiment of the present invention includes a high-side transistor having a thin-film gate oxide film, a high-side regenerative diode connected in parallel with the high-side transistor, a low-side transistor having a thin-film gate oxide film, and A push-pull circuit including a low-side transistor and a low-side regenerative diode connected in parallel; a level shift circuit; and a gate protection circuit connected between the output of the level shift circuit and the output of the push-pull circuit. A semiconductor integrated circuit including a high withstand voltage output circuit, wherein the gate protection circuit includes a zener diode, a first resistor and a second resistor connected in series including a P-type impurity region doped with a P-type impurity. A resistor that divides the breakdown voltage due to the Zener diode. A divided potential at a connection point between the first resistor and the second resistor is applied to the gate of the high-side transistor, and the first resistor and the second resistor are N-type impurities. Arranged so as to be surrounded by the doped N-type impurity region.

  In the semiconductor integrated circuit according to the second aspect of the present invention, each of the first resistor and the second resistor is individually surrounded by the N-type impurity region and is individually separated by different SOIs. Yes.

  In the semiconductor integrated circuit according to the second aspect of the present invention, each of the first resistor and the second resistor is individually surrounded by the N-type impurity region and is integrally separated by the same SOI. Yes.

  In the semiconductor integrated circuit according to the second aspect of the present invention, the shape of each corner of the N-type impurity region and the voltage dividing resistor is rounded.

  In the semiconductor integrated circuit according to the second aspect of the present invention, the first resistor and the second resistor are constituted by a single resistor, and the single resistor has a three-terminal electrode. ing.

  The semiconductor integrated circuit according to the second embodiment of the present invention includes a plurality of circuit cells each including a high withstand voltage output circuit further including a pad on a semiconductor chip, and the circuit cell includes a level shift circuit, a gate protection circuit, and a high side. The transistor, the low-side transistor, the high-side regeneration diode, the low-side regeneration diode, and the pad are arranged on a straight line.

  In the semiconductor integrated circuit according to the second aspect of the present invention, the semiconductor integrated circuit further includes a control unit disposed at the center of the semiconductor chip, and the plurality of circuit cells are disposed so as to face each other via the control unit. The first circuit cell array and the second circuit cell array each having a plurality of withstand voltage output circuits.

  In the semiconductor integrated circuit according to the second aspect of the present invention, the first power supply pad for the high potential and the first potential for the reference potential are arranged at both ends of each of the first circuit cell row and the second circuit cell row. Two power supply pads, a first wiring having a high voltage potential disposed on each of the high-side transistors in the first circuit cell row and the second circuit cell row and electrically connected to the first power supply pad, And a second wiring having a reference potential disposed on each low-side transistor in the first circuit cell column and the second circuit cell column and electrically connected to the second power supply pad.

  The semiconductor integrated circuit according to the second aspect of the present invention further includes a third wiring having a reference potential arranged so as to surround the control unit arranged in the central portion of the semiconductor substrate.

  In the semiconductor integrated circuit according to the second aspect of the present invention, the level shift circuit, the gate protection circuit, the high-side transistor, the high-side regeneration diode, and the low-side regeneration diode are designed to be within the cell width of the low-side transistor. .

  In the semiconductor integrated circuit according to the second aspect of the present invention, the Zener diode and the voltage dividing resistor are arranged adjacent to each other in the width direction of the high withstand voltage output circuit.

  According to the semiconductor integrated circuit described above, it is not necessary to manufacture a Zener diode having a plurality of breakdown voltages according to the gate breakdown voltage. Even a Zener diode having a breakdown voltage with a small variation due to current of 5 V or more has a breakdown voltage of less than 5 V. It is possible to provide a multi-channel semiconductor integrated circuit in which a high breakdown voltage output circuit optimally laid out so that a high-side transistor having a low threshold voltage can be used as a standard cell.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit configuration diagram of a multi-channel semiconductor integrated circuit according to the first embodiment of the present invention. Specifically, to describe a high voltage output circuit constituting a high voltage output circuit cell described later. FIG.

  As shown in FIG. 1, the semiconductor integrated circuit according to this embodiment includes a high-voltage output circuit 127 and a pre-driver that drives the high-voltage output circuit 127 in accordance with a control signal input terminal IN from a low-voltage controller described later. And 5.

  Here, the high withstand voltage output circuit 127 includes a push-pull circuit 7 that forms a push-pull output with the high-side transistor 12, the parasitic gate-source capacitance 11 of the high-side transistor 12, and the low-side transistor 13, and a thick film gate. A level shift circuit 6 that drives the high-side transistor 12, a Zener diode 9, voltage dividing resistors 48 and 49, and a voltage dividing resistor 48, which are composed of P-type MOS transistors 14 and 15 and thin-film gate N-type MOS transistors 16 and 17. 49 of the high-side transistor 12 which can be set to any driving voltage (gate driving voltage = breakdown voltage of the Zener diode 9 / (1 + voltage dividing resistor 48 / voltage dividing resistor 49)). And a gate protection circuit 8 for protecting the gate. The gate protection circuit 8 is connected between the output of the level shift circuit 6 and the output 4 of the push-pull circuit 7, and is divided at the connection point between the voltage dividing resistor 48 and the voltage dividing resistor 49 connected in series. A voltage potential is applied to the gate of the high side transistor 7.

  The high-side transistor 12 is connected to a high-voltage power source terminal 3, the low-side transistor 13 is connected to a reference potential terminal 1, and the pre-driver 5 is connected to a low-voltage power source terminal 2. The push-pull circuit 7 is connected to a high voltage output terminal 4. The high side transistor 12 is for high level output, and the low side transistor 13 is for low level output.

  FIG. 2 is a timing chart for explaining the operation of the high voltage output circuit 127 in the multi-channel semiconductor integrated circuit according to the first embodiment of the present invention.

  In FIG. 2, the voltage waveform of the input signal IN from the low withstand voltage control unit input to the input terminal IN and the voltage waveform of the output signals IN1 and IN2 of the pre-driver 5 that drives the level shift circuit 6 according to the input signal IN. The voltage waveform of the output signal IN3 of the pre-driver 5 that drives the low-side transistor 13 according to the input signal IN and the level shift circuit 6 that drives the high-side transistor 12 according to the output signals IN1 and IN2 of the pre-driver 5 The voltage waveform of the output signal IN4, the voltage waveform of the gate-source voltage GH of the high-side transistor 12 determined according to the output signal IN4 of the level shift circuit 6 and the gate protection circuit 8, the gate-source voltage GH, Voltage waveform of the output voltage OUT of the push-pull circuit 7 output according to the output signal IN3 of the pre-driver 5 The shows.

  When a GND level signal is input to the input signal IN and the input terminal IN becomes L level, the output signal IN1 becomes H level (VDD), the output signal IN2 becomes L level (GND), and the output signal IN4. Becomes L level (GND). In this case, the Zener diode 9 and the parasitic diode 47 of the voltage dividing resistors 48 and 49 are forward-biased, and the gate-source voltage GH becomes OUT-VFD (diode forward voltage) and is divided by the voltage-dividing resistors 48 and 49. Without being restricted, the high-side transistor 12 is turned off when the parasitic gate capacitance 11 is rapidly discharged and becomes equal to or lower than the threshold voltage Vth (N1) of the high-side transistor 12. Thereafter, the gate-source voltage GH returns to the same potential as the output voltage OUT by the voltage dividing resistors 48 and 49. Further, the output signal IN3 becomes H level (VDD) to turn on the low-side transistor 13, and the output voltage OUT becomes L level (GND).

  Next, when a VDD level signal is input to the input signal IN and the input terminal IN becomes H level (VDD), the output signal IN1 becomes L level (GND), and the output signal IN2 becomes H level (VDD). The output signal IN4 becomes H level (VDDH). At this time, since the gate-source voltage GH charges the parasitic gate capacitor 11 with a value obtained by dividing the breakdown voltage of the Zener diode 9 by the voltage dividing resistors 48 and 49, the gate-source voltage GH is OUT + Vz (breakdown). Voltage) / (1 + voltage dividing resistor 48 / voltage dividing resistor 49), and when the voltage becomes equal to or higher than the threshold voltage Vth (N1) of the high side transistor 12, the high side transistor 12 is turned on. Further, the output signal IN3 becomes L level (GND) and the low side transistor 13 is turned off, and the output signal OUT becomes H level (VDDH).

  3A is a plan view showing a layout of the voltage dividing resistors 48 and 49 constituting the gate protection circuit 8, and FIG. 3B is a sectional view taken along line IIIb-IIIb in FIG. is there. In FIG. 3A, for convenience of explanation, a part of the configuration shown in FIG. 3B is not shown.

  As shown in FIGS. 3A and 3B, a well 46 is formed which is separated by a trench 36 and a BOX 43, which are characteristic of SOI, and is doped with a thin N-type impurity. A resistor 45 doped with a dense P-type impurity is formed in the well 46, and a guard is a region doped with a dense N-type impurity so as to surround the resistor 45. A ring 44 is formed.

  As described above, since the N-type guard ring 44 is disposed so as to surround the P-type resistor 45, when the potential of the guard ring 44 becomes lower than that of the resistor 45, the parasitic diode 47 is in order. Biased. For this reason, the discharge of the gate capacitance 11 of the high side transistor 12 can be rapidly discharged without being limited by the voltage dividing resistors 48 and 49, so that the high side transistor 12 can be quickly turned off, and hence push Through-breakage of the pull circuit 7 can be avoided.

  On the other hand, when the potential of the guard ring 44 becomes higher than that of the resistor 45, the parasitic diode 47 is reverse-biased, and the potential of the well 46 is stabilized by the Zener diode 9. Therefore, the voltage dividing resistors 48 and 49 can accurately limit the gate drive voltage of the high side transistor 12. In addition, since the well 46, the guard ring 44, and the resistor 45 can all be used as diffusion layers used in other transistors, the configuration of the voltage dividing resistors 48 and 49 can be realized at low cost without increasing the mask process. it can.

  FIG. 4A is a plan view showing a layout of the voltage dividing resistors 48 and 49 constituting the gate protection circuit 8, which is a modification of the layout shown in FIGS. 3A and 3B. FIG. 4B is a cross-sectional view taken along line IVb-IVb in FIG. In FIG. 4A, for the convenience of explanation, illustration of a part of the configuration shown in FIG. 4B is omitted.

  The layout of the voltage dividing resistors 48 and 49 shown in FIGS. 4A and 4B differs from the layout of the voltage dividing resistors 48 and 49 shown in FIGS. A resistor 145 is formed in the well 46 which is doped with a thick P-type impurity so that the four corners are rounded, and is formed so as to surround the periphery of the resistor 145. The guard ring 144, which is a region doped with a thick N-type impurity, is formed so that the four corners are rounded.

  In this way, the current when the parasitic diode 47 generated when the potential of the guard ring 144 becomes lower than the resistor 145 is forward-biased can be made to flow uniformly. Therefore, the discharge of the gate capacitance 11 of the high side transistor 12 is not limited to the voltage dividing resistors 48 and 49, and can be discharged quickly and efficiently. As a result, the turn-off of the high-side transistor 12 can be accelerated, and as a result, the penetration breakdown of the push-pull circuit can be avoided.

  On the other hand, when the potential of the guard ring 144 becomes higher than that of the resistor 145, the parasitic diode 47 is reverse-biased, and the potential of the well 46 is stabilized by the Zener diode 9. Therefore, the voltage dividing resistors 48 and 49 can accurately limit the gate drive voltage of the high-side transistor 12. In addition, since the well 46, the guard ring 144, and the resistor 145 can all be used as diffusion layers used in other transistors, the configuration of the voltage dividing resistors 48 and 49 can be realized at low cost without increasing the mask process. it can.

  FIG. 5 is a plan view showing a layout in the high voltage output circuit cell 27 constituting the high voltage output circuit 127.

  As shown in FIG. 5, the layout of the high withstand voltage output circuit cell 27 includes a level shift circuit 6 in which thin-film gate N-type MOS transistors 16 and 17 and thick-film gate P-type MOS transistors 14 and 15 are arranged in this order. The gate protection circuit 8, which is arranged in the order of the Zener diode 9, the voltage dividing resistors 48 and 49, the high side transistor 12, the low side transistor 13, and the output pad 24 are arranged in this order.

  According to this layout, the low-side transistor 13 through which current flows most is arranged close to the output pad 24, while the level shift circuit 6 that hardly conducts current is arranged far from the output pad 24. The influence of the resistance can be suppressed to a low level, and since the large-sized low-side transistor 13 is closest to the output pad 24, the resistance to electrostatic breakdown can be improved.

  Further, as shown in FIG. 5, the level shift circuit 6, the gate protection circuit 8, the high side transistor 12, the low side transistor 13, and the output pad 24 are arranged in a straight line, which will be described later. As can be seen from the layout of the semiconductor integrated circuit shown in FIG. 5, high integration of the high breakdown voltage output circuit cell 27 including the high breakdown voltage output circuit 127 can be realized.

  Further, the level shift circuit 6 and the gate protection circuit 8 are designed to be within the cell width of the low side transistor 13 and the high side transistor 12 having the largest cell width. That is, as shown in FIG. 5, the level shift circuit 6 and the gate protection circuit 8 are designed in accordance with the cell widths of the low-side transistor 13 and the high-side transistor 12, thereby realizing high integration of the semiconductor integrated circuit. Has been.

  In FIG. 5, 28 is a drain region of the low side transistor 13, 29 is a gate region of the low side transistor 13, 30 is a source region of the low side transistor 13, 25 is a through hole, and 26 is a contact. , 31 is a drain region of the high-side transistor 12, 33 is a gate region of the high-side transistor 12, 32 is a source region of the high-side transistor 12, 35 is an anode electrode of a Zener diode, and 34 is The cathode electrode of the Zener diode, 18 is a reference potential wiring, 19 is a high-voltage power supply wiring, 20 and 22 are control signal lines for the level shift circuit 6, and 23 is a control signal line for the low-side transistor 13. It is.

  FIG. 6 is a plan view showing the structure of a multi-channel semiconductor integrated circuit in which high withstand voltage output circuit cells 27 having the layout shown in FIG.

  As shown in FIG. 6, a low breakdown voltage control unit 56 that performs output timing control by an input control circuit or the like is disposed on the semiconductor chip 57 on the semiconductor chip 57, and faces through the low breakdown voltage control unit 56. As described above, the plurality of high withstand voltage output circuit cells 27 are arranged along the chip side. The low withstand voltage control unit 56 including the pre-driver 5 and each of the high withstand voltage output circuit cells 27 are connected by the control signal lines 20 and 22 of the level shift circuit 6 and the control signal line 23 of the low-side transistor 13. 5, the control signal from the low withstand voltage control unit 56 is transmitted to the high withstand voltage output circuit cell 27 using the control signal lines 20, 22, and 23.

  Further, a high-voltage power supply pad 54 and a reference potential pad 53 are arranged at both ends of the plurality of high-breakdown-voltage output circuit cells 27. A reference potential wiring 18 is formed on the low-side transistor 13 in the high breakdown voltage output circuit cell 27, and the wiring 18 has a reference potential arranged on both sides of the plurality of high breakdown voltage output circuit cells 27. It is connected to the pad 53. Similarly, a high-voltage potential wiring 19 is formed on the high-side transistor 12 in the high-voltage output circuit cell 27, and the high-voltage potential wiring 19 is arranged on both sides of the plurality of high-voltage output circuit cells 27. It is connected to a pad 54 of a high voltage power source.

  The reference potential pads 53 and the high-voltage power supply pads 54 disposed on both sides of the plurality of high-breakdown-voltage output circuit cells 27 in the semiconductor chip 57 are wire-bonded from the package. The potential of the power supply pad 54 is stable. For this reason, the wiring impedance of the reference potential wiring 18 and the high-voltage potential wiring 19 can be reduced, and even when the output current from each channel gathers to become a large current, the high withstand voltage output circuit cell 27 The reference potential and the high voltage potential are stable, and uniform output characteristics and ESD tolerance can be obtained. On the other hand, an input control pad 55 is disposed on one side in the length direction of the low withstand voltage control unit 56, and a reference potential pad 53 is disposed on the other side. Further, a reference potential wiring 18b is formed on the low withstand voltage control unit 56 so as to surround three directions excluding the input control pad 55 side. The reference potential wiring 18 b serves as a shield for preventing external noise entering from the output pad 24 from being transmitted to the low breakdown voltage control unit 56 via the high breakdown voltage output circuit cell 27. For this reason, the signal input via the pre-driver 5 from the low withstand voltage control unit 56 is stabilized, and the output characteristics are stabilized.

(Second Embodiment)
FIG. 7 is a plan view showing a layout in the high voltage output circuit 27 constituting the high voltage output circuit 127 in the semiconductor integrated circuit according to the second embodiment of the present invention.

  The high breakdown voltage output circuit 127 shown in FIG. 7 is different from the high breakdown voltage output circuit 127 shown in FIG. 5 according to the first embodiment described above in the configuration of the gate protection circuit 8. 7 are the same as the corresponding portions of high voltage output circuit 127 shown in FIG. 5, and therefore description thereof will not be repeated. Also, the structure of the multi-channel semiconductor integrated circuit in which the high withstand voltage output circuit cell 27 shown in FIG. 7 is arranged is the same as the structure shown in FIG. 6 described above, and therefore description thereof will not be repeated.

  The gate protection circuit 8 in the high withstand voltage output circuit 127 shown in FIG. 7 includes a voltage dividing resistor disposed in the Zener diode 9 and the well 46 doped with the same thin N-type impurity separated by the trench 36 and the BOX 43. 48 and 49 are arranged in this order. That is, in the first embodiment, the voltage dividing resistors 48 and 49 are separated by individual SOIs, whereas in the second embodiment, the voltage dividing resistors 48 and 49 are separated by a single SOI. ing. With the layout shown in FIG. 7, the degree of integration of the gate protection circuit 8 is further improved. As a layout of the voltage dividing resistors 48 and 49 shown in FIG. 7, it is naturally possible to use the layout shown in FIG. 4A according to the first embodiment described above.

(Third embodiment)
FIGS. 8A and 8B are a plan view and a cross-sectional view showing a layout of the voltage dividing resistors 48 and 49 constituting the gate protection circuit 8 in the semiconductor integrated circuit according to the third embodiment of the present invention.

  The voltage dividing resistors 48 and 49 shown in FIGS. 8A and 8B differ from the voltage dividing resistors 49 and 49 according to the first and second embodiments described above in the layout of the voltage dividing resistors 48 and 49. It is. Since other parts constituting the gate protection circuit 8 are the same as those described in the first embodiment, description thereof will not be repeated.

  As shown in FIGS. 8A and 8B, a deep P-type impurity is doped in a well 46 that is separated by a trench 36 and a BOX 43 that are characteristic of SOI and doped with a thin N-type impurity. A resistor 45 is arranged. A guard ring 44, which is a region doped with a dense N-type impurity, is disposed so as to surround the resistor 45. Here, the resistor 45 has a three-terminal electrode provided with an electrode 50 for extracting a divided potential of resistance at the center. As described above, the N-type guard ring 44 is disposed so as to surround the P-type resistor 45, and the electrode 50 for extracting the divided potential of the resistor at the center of the resistor 45 and the Zener diode 9. Since the three-terminal electrode including the electrode 51 for connecting to the cathode and the electrode 52 for connecting to the anode of the Zener diode 9 is arranged, the relative accuracy due to the proximity of the voltage dividing resistors 48 and 49 And high integration of the voltage dividing resistors 48 and 49 can be realized.

  In the above layout, when the potential of the guard ring 44 becomes lower than the resistor 45, the parasitic diode 47 is forward biased. For this reason, the discharge of the gate capacitor 11 of the high side transistor 12 can be rapidly discharged without being limited by the voltage dividing resistors 48 and 49, so that the high side transistor 12 can be quickly turned off, and hence push-pull. Circuit breakthrough can be avoided.

  On the other hand, in the layout described above, when the potential of the guard ring 44 becomes higher than the resistor 45, the parasitic diode 47 is reverse-biased. For this reason, since the potential of the well 46 is stabilized by the Zener diode 9, the voltage dividing resistors 48 and 49 can accurately limit the gate drive voltage of the high-side transistor 12. In addition, since the well 46, the guard ring 44, and the resistor 45 can all be used as diffusion layers used in other transistors, the well 46, the guard ring 44, and the resistor 45 can be realized at low cost without increasing the number of mask processes.

  FIG. 9 shows a high withstand voltage output circuit cell 27 constituting the high withstand voltage output circuit 127 including the gate protection circuit 8 including the voltage dividing resistors 49 and 49 having the layout shown in FIGS. 8A and 8B. It is a top view which shows the layout in.

  The layout of the high voltage output circuit cell 27 shown in FIG. 9 is different from the layout of the high voltage output circuit cell 27 shown in FIGS. 5 and 7 according to the first and second embodiments described above. This is a layout of the Zener diode 9 and the voltage dividing resistors 49 and 49 constituting the circuit. The other parts of the high voltage output circuit cell 27 shown in FIG. 9 are the same as the layout of the high voltage output circuit cell 27 shown in FIGS. 5 and 7 according to the first and second embodiments described above. The description will not be repeated.

  In the layout of the high breakdown voltage output circuit cell 27 shown in FIG. 9, the Zener diode 9 constituting the gate protection circuit 8 and the resistor 45 constituting the voltage dividing resistors 49, 49 are arranged in the length direction of the high breakdown voltage output circuit cell 27. Are arranged adjacent to each other in the width direction perpendicular to the line. By laying out in this way, it becomes possible to increase the size of the Zener diode 9 and the voltage dividing resistors 49, 49 constituting the gate protection circuit 8 in the length direction of the high withstand voltage output circuit cell 27. Can easily increase the capacity. Further, the Zener diode 9 and the voltage dividing resistors 48 and 49 can increase the resistance value or increase the cathode size of the Zener diode 9 without exceeding the low side transistor 13 having the largest cell width (in other words, the cell width of the low side transistor 13). Can be large) and is easy to design.

  Also in such a layout, the level shift circuit 6 and the gate protection circuit 8 are designed to fit within the cell width of the low side transistor 13 and the high side transistor 12 having the largest cell width, as shown in FIG. As a result, high integration of the semiconductor integrated circuit can be realized as in the first and second embodiments described above.

  In this embodiment, the layout shown in FIG. 9 is used as the layout of the high voltage output circuit cell 27 including the gate protection circuit 8 including the voltage dividing resistors 48 and 49 having the layout shown in FIGS. However, as long as the cell width of the low-side transistor 13 is not changed, the Zener diode 9 and the voltage dividing resistors 48 and 49 may be arranged side by side in the length direction of the high-breakdown-voltage output circuit cell 27. It doesn't matter. Further, the structure of the multi-channel semiconductor integrated circuit in which the high withstand voltage output circuit cell 27 shown in FIG. 9 is arranged is the same as the structure shown in FIG. 6 described above, and therefore the description thereof will not be repeated.

(Fourth embodiment)
FIG. 10 is a circuit configuration diagram of a multi-channel semiconductor integrated circuit according to the fourth embodiment of the present invention. Specifically, a high voltage output circuit constituting a high voltage output circuit cell to be described later will be described. FIG.

  As shown in FIG. 10, the semiconductor integrated circuit according to this embodiment includes a high-voltage output circuit 127 and a pre-driver that drives the high-voltage output circuit 127 according to a control signal input terminal IN from a low-voltage control unit described later. And 5.

  As shown in FIG. 10, the high withstand voltage output circuit 127 is pushed by the high side transistor 58, the parasitic gate-emitter capacitance 111 of the high side transistor 58, the high side regeneration diode 60, the low side transistor 59, and the low side regeneration diode 61. A push-pull circuit 7 constituting a pull output, a thick gate P type MOS transistors 14 and 15 and thin film gate N type MOS transistors 16 and 17, a level shift circuit 6 for driving the high side transistor 58, and a Zener diode 9, the voltage dividing resistors 48 and 49, and the parasitic diode 47 of the voltage dividing resistors 48 and 49, and the driving voltage at which the gate is not destroyed is arbitrarily set (gate driving voltage = the breakdown voltage of the Zener diode 9 / (1 + the voltage dividing resistor 48 / Can be set to voltage dividing resistor 49) The gate protection circuit 8 protects the gate of the side transistor 58. The gate protection circuit 8 is connected between the output of the level shift circuit 6 and the output 4 of the push-pull circuit 7, and is connected in series. A voltage dividing potential at a connection point between the voltage dividing resistor 48 and the voltage dividing resistor 49 connected to is applied to the gate of the high side transistor 58.

  Further, the high-side transistor 58 and the high-side regenerative diode 60 are connected to the high-voltage power supply terminal 3, and the low-side transistor 59 and the low-side regenerative diode 61 are connected to the reference potential terminal 1. Is connected to a terminal 2 of a low-voltage power source, and a push-pull circuit 7 is connected to a terminal 4 of a high-voltage output. The high side transistor 58 is for high level output, and the low side transistor 59 is for low level output.

  FIG. 11 is a timing chart for explaining the operation of the high voltage output circuit 127 in the multi-channel semiconductor integrated circuit according to the fourth embodiment of the present invention.

  In FIG. 11, the voltage waveform of the input signal IN from the low withstand voltage control unit input to the input terminal IN and the voltage waveforms of the output signals IN1 and IN2 of the pre-driver 5 that drives the level shift circuit 6 according to the input signal IN. The voltage waveform of the output signal IN3 of the pre-driver 5 that drives the low-side transistor 59 according to the input signal IN and the level shift circuit 6 that drives the high-side transistor 59 according to the output signals IN1 and IN2 of the pre-driver 5 The voltage waveform of the output signal IN4, the voltage waveform of the gate-emitter voltage GH of the high-side transistor 58 determined according to the output signal IN4 of the level shift circuit 6 and the gate protection circuit 8, the gate-emitter voltage GH, The output voltage OUT of the push-pull circuit 7 output in response to the output signal IN3 of the pre-driver 5 It shows the waveform.

  When a GND level signal is input to the input signal IN and the input terminal IN becomes L level, the output signal IN1 becomes H level (VDD), the output signal IN2 becomes L level (GND), and the output signal IN4. Becomes L level (GND). In this case, the Zener diode 9 and the parasitic diode 47 of the voltage dividing resistors 48 and 49 are forward-biased, and the gate-emitter voltage GH becomes OUT-VFD (diode forward voltage) and is divided by the voltage-dividing resistors 48 and 49. Without being restricted, the parasitic gate capacitance 111 is rapidly discharged to be equal to or lower than the threshold voltage Vth (T1) of the high side transistor 58, whereby the high side transistor 58 is turned off. Thereafter, the gate-emitter voltage GH returns to the same potential as the output voltage OUT by the voltage dividing resistors 48 and 49. Further, the output signal IN3 becomes H level (VDD) and turns on the low-side transistor 59, and the output voltage OUT becomes L level (GND).

  Next, when a VDD level signal is input to the input signal IN and the input terminal IN becomes H level (VDD), the output signal IN1 becomes L level (GND), and the output signal IN2 becomes H level (VDD). The output signal IN4 becomes H level (VDDH). At this time, since the gate-emitter voltage GH charges the parasitic gate capacitance 111 with a value obtained by dividing the breakdown voltage of the Zener diode 9 by the voltage dividing resistors 48 and 49, the gate-emitter voltage GH is OUT + Vz (breakdown). Voltage) / (1 + voltage dividing resistor 48 / voltage dividing resistor 49), and when the voltage becomes equal to or higher than the threshold voltage Vth (T1) of the high side transistor 58, the high side transistor 58 is turned on. Further, the output signal IN3 becomes L level (GND), the low side transistor 59 is turned off, and the output voltage OUT becomes H level (VDDH).

  FIG. 12 is a plan view showing a layout in the high voltage output circuit cell 27 constituting the high voltage output circuit 127.

  As shown in FIG. 12, the layout of the high withstand voltage output circuit cell 27 includes a level shift circuit 6 in which thin-film gate N-type MOS transistors 16 and 17 and thick-film gate P-type MOS transistors 14 and 15 are arranged in this order. The gate protection circuit 8 arranged in the order of the Zener diode 9, the voltage dividing resistors 48 and 49, the high side transistor 58, the low side transistor 59, the low side regeneration diode 61, the output pad 24, and the high side regeneration diode 60. Are arranged in this order.

  According to this layout, since the high-side regenerative diode 60 and the low-side regenerative diode 61 that also serve as an ESD protection element are arranged with the output pad 24 interposed therebetween, the tolerance to electrostatic breakdown can be improved.

  Further, as shown in FIG. 12, the level shift circuit 6, the gate protection circuit 8, the high side transistor 58, the low side transistor 59, the low side regeneration diode 61, the output pad 24, and the high side regeneration diode 60 are aligned on a straight line. As is apparent from the layout of the semiconductor integrated circuit shown in FIG. 13 to be described later, the high withstand voltage output circuit cell 27 including the high withstand voltage output circuit 127 can be highly integrated. Here, the layout of the gate protection circuit 8 is the same as the layout shown in FIG. 9 in the first embodiment, but the layout shown in FIGS. 5 and 6 is used. (The layout of the voltage dividing resistors 48 and 49 may be as shown in FIG. 3 or FIG. 4).

  Further, the level shift circuit 6 and the gate protection circuit 8 are designed to be within the cell width of the low side transistor 59 and the high side transistor 58 having the largest cell width. That is, as shown in FIG. 12, the high integration of the semiconductor integrated circuit is realized by being designed according to the cell widths of the low-side transistor 59 and the high-side transistor 58.

  In FIG. 12, 67 is a collector region of the low-side transistor 59, 66 is a gate region of the low-side transistor 59, 65 is an emitter region of the low-side transistor 59, 25 is a through hole, and 26 is a contact. 64 is a collector region of the high-side transistor 58, 63 is a gate region of the high-side transistor 58, 62 is an emitter region of the high-side transistor 58, 69 is a cathode region of the low-side regenerative diode 61, 68 is an anode region of the low-side regenerative diode 61, 72 is a cathode region of the high-side regenerative diode 60, 71 is an anode region of the high-side regenerative diode 60, 35 is an anode electrode of the Zener diode, 34 The cathode electrode of the Zener diode, 18 is a reference potential wiring, 19 is a high voltage power source wiring, 20 and 22 are level shift 6 control signal lines, and 23 is a low side transistor 59 control signal line. is there.

  FIG. 13 is a plan view showing the structure of a multi-channel semiconductor integrated circuit in which the above-mentioned high withstand voltage output circuit cell 27 is arranged on the semiconductor chip 57. FIG.

  As shown in FIG. 13, a low withstand voltage control unit 56 that performs output timing control by an input control circuit or the like is disposed on the semiconductor chip 57 and is opposed to the semiconductor chip 57 through the low withstand voltage control unit 56. As described above, the plurality of high withstand voltage output circuit cells 27 are arranged along the chip side. The low breakdown voltage control unit 56 including the pre-driver 5 and each of the high breakdown voltage output circuit cells 27 are connected by the control signal lines 20 and 22 of the level shift circuit 6 and the control signal line 23 of the low-side transistor 59. The control signal from the low withstand voltage control unit 56 is transmitted to the high withstand voltage output circuit cell 27 using the control signal lines 20, 22, and 23.

  Further, a high-voltage power supply pad 54 and a reference potential pad 53 are arranged at both ends of the plurality of high-breakdown-voltage output circuit cells 27. Further, a reference potential wiring 18 is formed on the low-side transistor 59 in the high breakdown voltage output circuit cell 27, and the wiring 18 is a reference potential pad disposed on both sides of the plurality of high breakdown voltage output circuit cells 27. 53. Similarly, the high-voltage potential wiring 19 is formed on the high-side transistor 58 in the high-voltage output circuit cell 27, and the high-voltage potential wiring 19 is arranged on both sides of the plurality of high-voltage output circuit cells 27. It is connected to a pad 54 of a high voltage power source.

  The reference potential pads 53 and the high-voltage power supply pads 54 disposed on both sides of the plurality of high-breakdown-voltage output circuit cells 27 in the semiconductor chip 57 are wire-bonded from the package. The potential of the power supply pad 54 is stable. For this reason, the wiring impedance of the reference potential wiring 18 and the high-voltage potential wiring 19 can be reduced, and even when the output current from each channel gathers to become a large current, the high withstand voltage output circuit cell 27 The reference potential and the high voltage potential are stable, and uniform output characteristics and ESD tolerance can be obtained. On the other hand, an input control pad 55 is disposed on one side in the length direction of the low withstand voltage control unit 56, and a reference potential pad 53 is disposed on the other side. Further, a reference potential wiring 18b is formed on the low withstand voltage control unit 56 so as to surround three directions excluding the input control pad 55 side. The reference potential wiring 18 b serves as a shield for preventing external noise entering from the output pad 24 from being transmitted to the low breakdown voltage control unit 56 via the high breakdown voltage output circuit cell 27. For this reason, the signal input via the pre-driver 5 from the low withstand voltage control unit 56 is stabilized, and the output characteristics are stabilized.

  In each of the embodiments described above, the description is made using the expression “reference potential”, including the case where the potential is other than the ground potential. However, the “reference potential” is usually defined as a semiconductor chip. A potential connected to the substrate, which means a ground potential.

  The present invention is useful for a multi-channel semiconductor integrated circuit that drives a capacitive load such as a PDP.

1 is a circuit configuration diagram of a multi-channel semiconductor integrated circuit according to a first embodiment of the present invention, specifically, a circuit configuration diagram for explaining a high voltage output circuit constituting a high voltage output circuit cell. . FIG. 3 is a timing chart for explaining the operation of the high-breakdown-voltage output circuit cell in the multichannel semiconductor integrated circuit according to the first embodiment of the present invention. (A) is a top view which shows the layout of the voltage dividing resistor which comprises the gate protection circuit in the high voltage | pressure-resistant output circuit cell based on the 1st Embodiment of this invention, (b) is IIIb- of (a). It is sectional drawing of a IIIb line. (A) is a top view which shows the layout of the voltage dividing resistor which comprises the gate protection circuit in the high voltage | pressure-resistant output circuit cell based on the 1st Embodiment of this invention, (b) is IVb- in (a). It is sectional drawing of an IVb line. 1 is a plan view showing a layout of a high voltage output circuit cell of a multi-channel semiconductor integrated circuit according to a first embodiment of the present invention. 1 is a plan view showing a layout of a multi-channel semiconductor integrated circuit according to a first embodiment of the present invention. It is a top view which shows the layout of the high voltage | pressure-resistant output circuit cell of the multichannel semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. (A) is a top view which shows the layout of the voltage dividing resistor which comprises the gate protection circuit in the high voltage | pressure-resistant output circuit cell based on the 3rd Embodiment of this invention, (b) is VIIIb- in (a). It is sectional drawing of a VIIIb line. It is a top view which shows the layout of the high voltage | pressure-resistant output circuit cell of the multichannel semiconductor integrated circuit which concerns on the 3rd Embodiment of this invention. FIG. 9 is a circuit configuration diagram of a multi-channel semiconductor integrated circuit according to a fourth embodiment of the present invention, specifically, a circuit configuration diagram for explaining a high voltage output circuit constituting a high voltage output circuit cell. . FIG. 10 is a timing chart for explaining the operation of a high voltage output circuit cell in a multi-channel semiconductor integrated circuit according to a fourth embodiment of the present invention. It is a top view which shows the layout of the high voltage | pressure-resistant output circuit cell of the multichannel semiconductor integrated circuit which concerns on the 4th Embodiment of this invention. It is a top view which shows the layout of the multichannel semiconductor integrated circuit which concerns on the 4th Embodiment of this invention. It is a circuit block diagram for demonstrating the high voltage | pressure-resistant output circuit in the conventional multichannel semiconductor integrated circuit. FIG. 10 is a timing diagram illustrating the operation of a high voltage output circuit in a conventional multi-channel semiconductor integrated circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reference potential terminal 2 Low voltage power supply terminal 3 High voltage power supply terminal 4 High voltage output terminal 5 Pre-driver 6 Level shift circuit 7 Push-pull circuit 8 Gate protection circuit 9 Zener diode 10 First resistor 11 Between parasitic gate and source Capacitor 12 High-side transistor 13 Low-side transistor 14, 15 Thick gate P-type MOS transistor 16, 17 Thin-film gate N-type MOS transistor 18, 18 b Reference potential wiring 19 High-voltage power supply wiring 20, 22 Level shift control signal wiring 23 Low side Transistor control signal wiring 24 Output pad 25 Through hole 26 Contact 27 High breakdown voltage output circuit cell 28 Low-side transistor drain region 29 Low-side transistor gate region 30 Low-side transistor source region 31 High-side transistor Njisuta drain region 32 the high-side transistor source region 33 the high-side transistor anode electrode 36 trench 40 aluminum electrode 41 protective film 43 BOX cathode electrode 35 Zener diode gate region 34 Zener diode (buried oxide)
44 N-type guard ring 45 P-type resistor 46 N-type well 47 Parasitic diode 48, 49 Voltage dividing resistor 50 Voltage dividing electrode 51 Cathode connection electrode 52 Anode connection electrode 53 Reference potential pad 54 High voltage power supply pad 55 Input control Pad 56 Low voltage controller 57 Semiconductor chip 58 High side transistor 59 Low side transistor 60 High side regeneration diode 61 Low side regeneration diode 62 High side transistor emitter region 63 High side transistor gate region 64 High side transistor collector region 65 Low side transistor Emitter region 66 Low-side transistor gate region 67 Low-side transistor collector region 68 Low-side regenerative diode anode region 69 Low-side regenerative diode cap Sword region 71 High-side regenerative diode anode region 72 Low-side regenerative diode cathode region 144 N-type oval guard ring 145 P-type resistor 111 Parasitic gate-emitter capacitance 127 High breakdown voltage output circuit

Claims (22)

A push-pull circuit composed of a high-side transistor having a thin-film gate oxide film and a low-side transistor having a thin-film gate oxide film;
A level shift circuit;
A semiconductor integrated circuit comprising a high withstand voltage output circuit having a gate protection circuit connected between the output of the level shift circuit and the output of the push-pull circuit,
The gate protection circuit is
Zener diode,
A first resistor and a second resistor connected in series composed of a P-type impurity region doped with a P-type impurity, and a voltage dividing resistor for dividing a breakdown voltage by the Zener diode;
A divided potential at a connection point between the first resistor and the second resistor is applied to the gate of the high-side transistor,
The semiconductor integrated circuit, wherein the first resistor and the second resistor are disposed so as to be surrounded by an N-type impurity region doped with an N-type impurity. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit, wherein each of the first resistor and the second resistor is individually surrounded by the N-type impurity region and is individually separated by different SOIs. The semiconductor integrated circuit according to claim 1,
Each of the first resistor and the second resistor is individually surrounded by the N-type impurity region, and is integrally separated by the same SOI. The semiconductor integrated circuit according to claim 1,
The shape of the corner of each of the N-type impurity region and the voltage dividing resistor is rounded. The semiconductor integrated circuit according to claim 1,
The first resistor and the second resistor are configured by a single resistor,
The single resistor has a three-terminal electrode. The semiconductor integrated circuit according to claim 1,
On the semiconductor chip, a plurality of circuit cells including the high withstand voltage output circuit further including a pad are provided,
In the circuit cell, the level shift circuit, the gate protection circuit, the high side transistor, the low side transistor, and the pad are arranged on a straight line. The semiconductor integrated circuit according to claim 6,
A control unit disposed in a central portion of the semiconductor chip;
The plurality of circuit cells are configured by a first circuit cell column and a second circuit cell column each including a plurality of the high withstand voltage output circuits arranged to face each other via the control unit. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 7,
A first power supply pad for a high voltage potential and a second power supply pad for a reference potential disposed at both ends of each of the first circuit cell row and the second circuit cell row;
A first wiring having a high voltage potential disposed on each of the high side transistors in the first circuit cell row and the second circuit cell row and electrically connected to the first power supply pad;
A second wiring having a reference potential, which is disposed on each of the low-side transistors in the first circuit cell row and the second circuit cell row and is electrically connected to the second power supply pad; A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 8, wherein
A semiconductor integrated circuit, further comprising a third wiring having a reference potential disposed so as to surround a control unit disposed in a central portion of the semiconductor substrate. The semiconductor integrated circuit according to claim 6,
The semiconductor integrated circuit, wherein the level shift circuit, the gate protection circuit, and the high side transistor are designed to fit within a cell width of the low side transistor. The semiconductor integrated circuit according to claim 10,
The semiconductor integrated circuit, wherein the Zener diode and the voltage dividing resistor are arranged adjacent to each other in the width direction of the high withstand voltage output circuit. A high-side transistor having a thin gate oxide film, a high-side regenerative diode connected in parallel with the high-side transistor, a low-side transistor having a thin-film gate oxide film, and a low-side regenerative diode connected in parallel with the low-side transistor A push-pull circuit,
A level shift circuit;
A semiconductor integrated circuit comprising a high withstand voltage output circuit having a gate protection circuit connected between the output of the level shift circuit and the output of the push-pull circuit,
The gate protection circuit is
Zener diode,
A first resistor and a second resistor connected in series composed of a P-type impurity region doped with a P-type impurity, and a voltage dividing resistor for dividing a breakdown voltage by the Zener diode;
A divided potential at a connection point between the first resistor and the second resistor is applied to the gate of the high-side transistor,
The semiconductor integrated circuit, wherein the first resistor and the second resistor are disposed so as to be surrounded by an N-type impurity region doped with an N-type impurity. The semiconductor integrated circuit according to claim 12, wherein
The semiconductor integrated circuit, wherein each of the first resistor and the second resistor is individually surrounded by the N-type impurity region and is individually separated by different SOIs. The semiconductor integrated circuit according to claim 12, wherein
Each of the first resistor and the second resistor is individually surrounded by the N-type impurity region, and is integrally separated by the same SOI. The semiconductor integrated circuit according to claim 12, wherein
The shape of the corner of each of the N-type impurity region and the voltage dividing resistor is rounded. The semiconductor integrated circuit according to claim 12, wherein
The first resistor and the second resistor are configured by a single resistor,
The single resistor has a three-terminal electrode. The semiconductor integrated circuit according to claim 12, wherein
On the semiconductor chip, a plurality of circuit cells including the high withstand voltage output circuit further including a pad are provided,
In the circuit cell, the level shift circuit, the gate protection circuit, the high-side transistor, the low-side transistor, the high-side regenerative diode, the low-side regenerative diode, and the pad are arranged in a straight line. . The semiconductor integrated circuit according to claim 17, wherein
A control unit disposed in a central portion of the semiconductor chip;
The plurality of circuit cells are configured by a first circuit cell column and a second circuit cell column each including a plurality of the high withstand voltage output circuits arranged to face each other via the control unit. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 18, wherein
A first power supply pad for a high voltage potential and a second power supply pad for a reference potential disposed at both ends of each of the first circuit cell row and the second circuit cell row;
A first wiring having a high voltage potential disposed on each of the high side transistors in the first circuit cell row and the second circuit cell row and electrically connected to the first power supply pad;
A second wiring having a reference potential, which is disposed on each of the low-side transistors in the first circuit cell row and the second circuit cell row and is electrically connected to the second power supply pad; A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 19, wherein
A semiconductor integrated circuit, further comprising a third wiring having a reference potential disposed so as to surround a control unit disposed in a central portion of the semiconductor substrate. The semiconductor integrated circuit according to claim 17, wherein
The semiconductor integrated circuit, wherein the level shift circuit, the gate protection circuit, the high-side transistor, the high-side regenerative diode, and the low-side regenerative diode are designed to fit within the cell width of the low-side transistor. The semiconductor integrated circuit according to claim 21, wherein
The semiconductor integrated circuit, wherein the Zener diode and the voltage dividing resistor are arranged adjacent to each other in the width direction of the high withstand voltage output circuit.

Images