JP4923686B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device applicable to a high voltage IC for driving an inverter or the like.

  High voltage ICs for driving an inverter are disclosed in, for example, Japanese Patent No. 3384399 (Patent Document 1) and Proc. Of ISPSD'04 (Non-Patent Document 1).

FIG. 9A is a circuit configuration diagram focusing on the power portion of the motor control inverter disclosed in Patent Document 1. FIG. The power devices (Q1 to Q6 which are IGBTs and D1 to D6 which are diodes) used for driving the three-phase motor Mo constitute a bridge circuit and have a structure of a power module housed in the same package. The main power supply V _CC is usually a high voltage of 100 to 400 VDC. In particular, in the control of motors for automobiles such as electric vehicles (EV) and hybrid (HEV) vehicles, the main power supply V _CC is as high as 650 VDC. When the high potential side of the main power supply V _CC is represented as V _CCH and the low potential side is represented as V _CCL , the potential of the gate electrode of the IGBT is higher than this in order to drive the IGBTs Q1 to Q3 connected to V _CCH. It becomes a potential. For this reason, a photocoupler (PC: Photo Coupler) and a high voltage IC (HVIC: High Voltage Integrated Circuit) 90 are used for a drive circuit. The input / output terminals (I / O: Input / Output) of the drive circuit are usually connected to a microcomputer, and the microcomputer controls the entire inverter.

FIG. 9B is a block diagram of an internal configuration unit of the high voltage IC (HVIC) used in FIG. A high voltage IC 90 shown in FIG. 9B includes a control circuit (CU: Control Unit), gate drive circuits GDU (Gate Drive Unit) 4 to 6 based on a low potential GND, and a high potential floating potential. And a level shift circuit (LSU: Level Shift Unit). The control circuit CU exchanges signals with the microcomputer through the input / output terminal I / O, and generates a control signal indicating which IGBT in FIG. 9A is turned on and which is turned off. Gate drive circuits GDU (Gate Drive Unit) 4 to 6 drive IGBTs Q4 to Q6 connected to the low potential side V _CCL of the main power supply V _CC in FIG. 9A. The gate drive circuits GDU1 to GDU1 drive the IGBTs Q1 to Q3 connected to the high potential side V _CCH of the main power supply V _CC in FIG. The level shift circuit LSU is a signal V _CCL level of the control circuit CU, GDU1～3 signals alternate between the V _CCH level and the V _CCL level (SIN1~3, SOUT1~3) between mediate Work. Therefore, since the semiconductor device constituting the level shift circuit LSU of the high voltage IC 90 handles signals between the V _CCH level and the V _CCL level (0 to 650 V) as described above, a particularly high breakdown voltage (about 1200 V) is required. Is done.

In a semiconductor device in which two or more circuits having different reference potentials are integrated as in the high voltage IC 90 shown in FIG. 9B, the formation region of each circuit having different reference potentials is made of pn junction isolation or SiO ₂ . They are separated from each other by dielectric separation using a dielectric. In general, a high voltage IC using pn junction isolation may cause a malfunction of a circuit or element destruction because a parasitic transistor is easily formed. On the other hand, in a high voltage IC using dielectric isolation, parasitic transistor operation does not occur, and problems such as circuit malfunction and element destruction do not occur.

FIG. 10 shows a schematic cross-sectional view of a conventional high-voltage IC 91 using an SOI substrate and trench isolation. The high voltage IC 91 shown in FIG. 10 is provided with a low potential (GND) reference circuit, a high potential (floating) reference circuit, and a level shift circuit in the SOI layer 1 of the SOI substrate 10 having the buried oxide film 3. Yes. The formation regions of the GND reference circuit, the floating reference circuit, and the level shift circuit are insulated (dielectric) separated by the buried oxide film 3 of the SOI substrate 10 and the sidewall oxide film 4s of the trench 4. In the level shift circuit of the high voltage IC 91, a high withstand voltage circuit element is required to connect the low potential reference circuit and the high potential reference circuit. The MOS transistor Tr _{L in} the level shift circuit formation region shown in FIG. 10 has a so-called SOI-RESURF structure in order to ensure a withstand voltage.

The high voltage in the level shift circuit is applied to the drain (D) of the MOS transistor Tr _L as shown in the figure. In the MOS transistor Tr _L of FIG. 10, the lateral breakdown voltage in the cross section is ensured by the SOI-RESURF structure formed by the surface p-type impurity layer and the buried oxide film 3. As for the breakdown voltage in the vertical direction of the cross section, as disclosed in Non-Patent Document 1, a high voltage applied between the drain (D) and the ground (GND) is applied to the low concentration SOI layer 1 and the buried oxide film 3. And the electric field in the SOI layer 1 is relaxed.
Japanese Patent No. 3384399 Proc. Of ISPSD '04, p385, H. Akiyama, et al (Mitsubishi Electric)

As described above, in order to realize a high breakdown voltage semiconductor device using an SOI structure semiconductor substrate, a desired breakdown voltage can be obtained by distributing the applied voltage between the SOI layer and the buried oxide film in the longitudinal direction of the cross section. It is necessary to optimally design the concentration and thickness of the SOI layer and the thickness of the buried oxide film. However, in order to obtain a high breakdown voltage of 1000 V or more by this method, a buried oxide film thicker than 5 μm and an SOI layer thicker than 50 μm are required. On the other hand, the upper limit of the thickness of the buried oxide film that can be achieved is about 4 μm because of warpage of the SOI substrate. Also, the thickness of the SOI layer is usually about several μm to 20 μm, and increasing the thickness of the SOI layer increases the trench processing load. For this reason, in the MOS type transistor Tr _L in the level shift circuit formation region of FIG. 10, it is impossible to secure the withstand voltage of about 1200V required for a 400V power supply system, an EV car, etc., because the withstand voltage of about 600V is the limit.

In order to solve the above problem, a novel semiconductor device 100 shown in FIG. 11 has been invented. FIG. 11 is a basic circuit diagram of the semiconductor device 100. In the semiconductor device 100 shown in FIG. 11, the transistor elements _Tr 1 to Tr _n of n that are insulated and separated from each other (n ≧ 2), between the ground (GND) potential and the predetermined potential Vs, the GND potential side first One stage is connected in series with the predetermined potential Vs side as the nth stage. The n transistor elements Tr _{1 to} Tr _n may be MOS (Metal Oxide Semiconductor) type transistor elements or IGBT (Insulated Gate Bipolar Transistor) elements. In the above configuration, _assuming that each of the transistor elements Tr _{1 to} Tr _n is a MOS transistor element, the drain voltage of the lower MOS transistor element is applied to the source of the upper MOS transistor element. .

In addition, n resistance elements R _{1 to} R _n are sequentially connected in series between the same GND potential and a predetermined potential Vs, with the GND potential side as the first stage and the predetermined potential Vs side as the nth stage. . A weak current flows through the _n resistance elements R _{1 to} R _n , and the voltage between the GND potential and the predetermined potential Vs is divided into the resistance elements R _{1 to} R _n . In FIG. 11, the voltage between the GND potential and the predetermined potential Vs is divided by each of the resistance elements R _{1 to} R _n , but may be divided using a capacitive element. In this case, there is an effect of reducing current consumption.

In the semiconductor device 100 of FIG. 11, the gate terminal of the transistor element _Tr 2 to Tr _n of each stage, except for the transistor elements Tr ₁ of the first stage, via the resistor _Rg 2 _{~Rg n,} each connected in series The connection points P _{2 to} P _n between the resistive elements R _{1 to} R _{n of the} stage are sequentially connected. Similarly, in each of the transistor elements Tr _{2 to} Tr _n except for the first-stage transistor element Tr ₁ , diodes D _{2 to} D _n are inserted between the gate terminal and the GND potential side terminal. . These resistive elements _Rg 2 ～Rg _n and the diode _D 2 to D _n, upon the addition of the input signal to the gate terminal of the transistor elements Tr ₁ of the first stage, transistor elements _Tr 2 to Tr n-th stage from the second stage The simultaneous operation of _n can be stabilized.

The gate terminal of the first-stage transistor element Tr ₁ is an input terminal of the semiconductor device 100. The output of the semiconductor device 100 is taken out from a terminal on the predetermined potential Vs side of the n-th stage transistor element Tr _n via a load resistor (not shown) having a predetermined resistance value. The output signal is extracted in a state where the reference potential is converted (level shift) from the GND potential of the input signal to the predetermined potential Vs and inverted with respect to the input signal.

In the semiconductor device 100 of FIG. 11, by adding an input signal to the gate terminal of the transistor elements Tr ₁ of the first stage, also the n resistance elements R ₁ ~ connected in series between the GND potential and the predetermined potential Vs The second to n-th transistor elements Tr _{2 to} Tr _n can be operated simultaneously via R _n . That is, when each of the transistor elements Tr _{1 to} Tr _n is a MOS transistor element and the GND potential side of each of the transistor elements Tr _{1 to} Tr _n is a source, a signal voltage is applied to the gate terminal of the first stage transistor element Tr _1. Once applied, the drain potential of the transistor elements Tr ₁ of the first stage is reduced. Along with this, since the source potential of the transistor elements Tr ₂ of the second stage is lowered, the second stage of the transistor elements Tr ₂ gate - current flows from the connection point P ₂ to the diode D2 between the source. Gate - result-source fixed to the Zener voltage (5V in this case), the transistor elements Tr ₂ of the second stage is to ON. The same process is repeated up to the _n-th transistor element Tr _n , and all the transistor elements Tr _{1 to} Tr _n are turned on in an extremely short time.

In operation of the semiconductor device 100 of FIG. 11, the voltage between the GND potential and the predetermined potential Vs is divided by the n transistor elements _Tr 1 to Tr _n, each transistor elements _Tr 1 ~ of the n stages from the first stage Tr _n shares the respective voltage ranges. Therefore, the breakdown voltage required for each of the transistor elements Tr _{1 to} Tr _n is approximately ₁ / _n compared to the case where the voltage between the GND potential and the predetermined potential Vs is shared by _one transistor element. Therefore, even a transistor element having a normal breakdown voltage that can be manufactured at low cost using a general manufacturing method is necessary as a whole by appropriately setting the number n of transistor elements in the semiconductor device 100 of FIG. The semiconductor device can ensure a high breakdown voltage. In the semiconductor device 100 of FIG. 11, it is preferable that the _n transistor elements Tr _{1 to} Tr _n have the same breakdown voltage. Thereby, the voltage (withstand voltage) shared by the transistor elements Tr _{1 to} Tr _n inserted between the GND potential and the predetermined potential can be equalized and minimized.

  FIG. 12 is a diagram illustrating a basic configuration of another semiconductor device, and is a circuit diagram of the semiconductor device 101. The semiconductor device 101 shown in FIG. 12 has n (n ≧ 2) transistor elements Tr, and a resistor element R and a capacitor element C2 connected in parallel as parallel RC elements between the GND potential and a predetermined potential. It is the structure divided | segmented by a parallel RC element. From another viewpoint, the configuration of the semiconductor device 101 is a configuration in which a line of the capacitive element C2 connected in series is added to the line of the resistor R connected in series between the GND potential and the predetermined potential. It has become. When the resistance value of the resistance element R is large, the line of the capacitive element C2 connected in series functions as a line for releasing a surge current when a dV / dt surge is generated. In the semiconductor device 101, by appropriately setting the resistance value of the resistance element R in the n parallel RC elements and the capacitance value of the second capacitance element C2, the n transistor elements Tr of the n transistor elements Tr when a dV / dt surge occurs are set. The potential at each connection point in the line can be distributed almost evenly.

  Note that a patent application has already been filed for the above invention (application number 2005-227058, application number 2005-318679).

  On the other hand, in the semiconductor devices 100 and 202 of FIG. 11 and FIG. 12, a high power supply voltage is applied to the line of the resistor R connected in series between the GND potential and the predetermined potential. There is a problem that power consumption increases. In order to reduce the leakage current, it is necessary to increase the resistance value of the voltage dividing resistor R to several MΩ, but in this case, the area occupied by the voltage dividing resistor R formed of a thin film such as CrSi on the chip increases. As a result, the cost increases.

  Further, in the semiconductor device 101 of FIG. 12, in order to evenly divide the dV / dt surge and prevent the wraparound to the substrate (transistor element Tr), the capacitance value of the capacitive element C2 needs to be on the order of pF. However, in this case as well, if the number of stages of the transistor elements Tr is laid out, the chip area increases and the area efficiency becomes very poor.

  Therefore, the present invention is a semiconductor device in which n (n ≧ 2) transistor elements that are insulated and separated from each other are sequentially connected in series, and can ensure a high breakdown voltage required as a whole, and power consumption The object is to provide a small, inexpensive and inexpensive semiconductor device.

The semiconductor device according to claim 1, wherein n transistor elements (n ≧ 2) that are insulated from each other are arranged between a ground (GND) potential and a predetermined potential, and the GND potential side is the first stage, and the predetermined potential As the gate voltage dividing circuit of the transistor elements sequentially connected in series with the n-th side as the n-th stage, the gate terminal in the first-stage transistor element as the input terminal, and sequentially connected in series between the GND potential and the predetermined potential Without using a resistance element, n short-circuited transistor elements whose gates and sources are short-circuited have a GND potential side in the first stage and a predetermined potential side in the first stage between the GND potential and the predetermined potential. n stages are sequentially connected in series, and the gate terminal of each stage transistor element excluding the first stage transistor element is connected between the series connected short circuit transistor elements. Each will be sequentially connected, from the predetermined potential side terminal in the n-th stage transistor element, the output is characterized by comprising fetched.

  The short-circuit transistor element in which the gate and the source in the semiconductor device are short-circuited can function as a diode. For this reason, in the semiconductor device, the gate voltage dividing circuit of the main line transistor elements sequentially connected in series between the GND potential and the predetermined potential is also a short circuit transistor element sequentially connected in series between the GND potential and the predetermined potential. (Diode). Therefore, since the semiconductor device does not use a resistance element for the gate voltage dividing circuit line, no (leakage) current flows through the gate voltage dividing circuit line in a steady state, and thus power consumption does not increase. . Further, the area occupied by the short-circuit transistor element in the chip is smaller than that of the resistor element and the capacitor element, and this does not increase the cost.

  In the semiconductor device, as in the case of using a resistive element and a capacitive element in the gate voltage dividing circuit, an input signal is applied to the gate terminal of the first-stage transistor element, so that the n number of short-circuited transistor elements are connected. The second to n-th transistor elements can be operated simultaneously. In the semiconductor device, a voltage between the GND potential and the predetermined potential is divided by n transistor elements, and each transistor element from the first stage to the n-th stage shares a voltage range. Therefore, the breakdown voltage required for each transistor element can be reduced as compared with the case where the voltage between the GND potential and the predetermined potential is shared by one transistor element.

  In a semiconductor device in which the GND potential and a predetermined potential are divided and shared by the transistor elements of each stage of the main line, generally, the gate voltage dividing circuit line is configured together with the breakdown voltage of the transistor elements of each stage configuring the main line. The same breakdown voltage is required for each element. In this respect, the breakdown voltage of the short-circuit transistor element (diode) in which the gate and the source are short-circuited in the semiconductor device is equal to or higher than that in the state where the gate and the source are not short-circuited. Therefore, the above-mentioned semiconductor device in which the main line and the gate voltage dividing circuit line are basically composed of the same transistor element is very easy to design withstand voltage as compared with a semiconductor device using a diode element having a simple structure in the gate voltage dividing circuit line. It will be something. Further, since the deviation in the breakdown voltage characteristics of the transistor elements in the main line and the short-circuit transistor elements in the gate voltage dividing circuit line is small, the voltage dividing ratio between the GND potential and the predetermined potential can be made more accurate.

  The semiconductor device in which the main line and the gate voltage dividing circuit line are basically composed of the same transistor element has a very simple manufacturing process as compared with, for example, a semiconductor device using a diode element having a simple structure in the gate voltage dividing circuit line. It becomes. The manufacturing process of the semiconductor device can be configured only by the manufacturing process of transistor elements that can be simultaneously formed, the number of processes is small, process management is easy, and the semiconductor device can be manufactured at low cost.

  When a surge is applied to the semiconductor device, each of the first to n-th short-circuit transistors on the gate voltage dividing circuit line is the same as when a resistor element or a capacitive element is used for the gate voltage dividing circuit. The charge of surge current can be quickly released to GND through the element. For this reason, a high voltage due to a surge is not applied to a specific transistor element in the main line. Therefore, circuit breakdown due to breakdown of the transistor element when a surge is applied can be suppressed.

  As described above, the semiconductor device is a semiconductor device in which n (n ≧ 2) transistor elements that are insulated and separated from each other are sequentially connected in series, and ensures a high breakdown voltage required as a whole. In addition, a small and inexpensive semiconductor device with low power consumption can be obtained.

  According to a second aspect of the present invention, in the semiconductor device, the transistor element and the short-circuit transistor element preferably have the same cross-sectional structure in the channel length direction.

  The breakdown voltage of the transistor element is determined by the cross-sectional structure in the channel length direction. For this reason, by making the cross-sectional structure in the channel length direction of the transistor element of the main line and the short-circuit transistor element of the gate voltage dividing circuit line the same, the withstand voltage design is simplified and the withstand voltage characteristics of both transistor elements are accurately set. Can match. Also, since the breakdown voltage of each transistor element constituting each line is equal in each line, the voltage (withstand voltage) shared by each transistor element inserted between the GND potential and a predetermined potential is equalized and minimized. can do.

  If the cross-sectional structures in the channel length direction are the same, the gate width of the transistor element in the direction orthogonal to the channel length direction hardly affects the breakdown voltage characteristics. For this reason, in the semiconductor device, the gate width of the transistor element of the main line and the short-circuit transistor element of the gate voltage dividing circuit line can be arbitrarily set.

  For example, as described in claim 3, gate widths of the n transistor elements constituting the main line can be set equal.

  On the other hand, the transistor element has a parasitic capacitance, and the value of the parasitic capacitance is proportional to the gate width of the transistor element.

By using this, as described in claim 4, in the semiconductor device, the gate width of the short-circuit transistor element in the (k−1) th stage (2 ≦ k ≦ n) is the (k−). the sum of the gate width of each transistor device is above 1) step, it is preferable that formed by equal properly set.

  In the semiconductor device in which the gate width is set as described above, the parasitic capacitance of the short-circuit transistor element in the (k−1) th stage (2 ≦ k ≦ n) is higher than the (k−1) th stage. It is almost equal to the sum of the parasitic capacitances of the transistor elements. For this reason, in the semiconductor device described above, the parasitic capacitance of the short-circuit transistor element in the gate voltage dividing circuit line is corrected in order from the power supply side of the predetermined potential by correcting the influence of the parasitic capacitance of the multistage transistor elements in the main line. Will be placed. This makes it difficult for charges to be accumulated in the transistor elements at each stage, so that the charge of the surge current can be quickly released to GND, and deterioration in switching speed due to the multi-stage can be suppressed.

  In the semiconductor device, the gate width of the short-circuit transistor element in the highest nth stage closest to the predetermined potential hardly affects the characteristics against the surge and the switching speed.

  Therefore, as described in claim 5, the gate width of the n-th stage short-circuit transistor element can be set smaller than the gate width of the n-th stage transistor element.

  In the semiconductor device, as described in claim 6, the gate widths of the n transistor elements and the n short transistor elements are all set equal to each other, and each of the n short transistor elements is Thus, the capacitive elements may be connected in parallel. You may make it correct | amend the influence of the parasitic capacitance of the multistage transistor element in a main line by the capacitive element connected in parallel with respect to each of this short circuit transistor element.

The semiconductor device according to claim 7, wherein n (n ≧ 2) transistor elements that are insulated from each other are arranged between a ground (GND) potential and a predetermined potential, the GND potential side is a first stage, and the predetermined potential is set. As the gate voltage dividing circuit of the transistor elements sequentially connected in series with the n-th side as the n-th stage, the gate terminal in the first-stage transistor element as the input terminal, and sequentially connected in series between the GND potential and the predetermined potential Without using a resistance element, n short-circuited transistor elements whose gates and sources are short-circuited have a GND potential side in the first stage and a predetermined potential side in the first stage between the GND potential and the predetermined potential. n stages are sequentially connected in series, and the gate terminal of each stage transistor element excluding the first stage transistor element is connected between the series connected short circuit transistor elements. Each of the n short-circuit transistor elements is sequentially connected, and a capacitive element is connected in parallel to each of the n short-circuit transistor elements, and an output is taken out from the predetermined potential side terminal of the n-th transistor element. It is characterized by.

  The semiconductor device has a configuration in which a short-circuit transistor element and a capacitor element connected in parallel are used at each stage of the gate voltage dividing circuit line. Also in this case, as described in the semiconductor device of claim 1, since no resistance element is used for the gate voltage dividing circuit line, no current (leakage) flows in the gate voltage dividing circuit line in a steady state. A semiconductor device with low power consumption can be obtained. Further, in the semiconductor device, the influence of the parasitic capacitance of the multi-stage transistor elements in the main line can be corrected by the capacitor elements connected in parallel to each of the short-circuit transistor elements.

  As described above, the semiconductor device is also a semiconductor device in which n (n ≧ 2) transistor elements that are insulated from each other are sequentially connected in series, and ensures a high breakdown voltage required as a whole. In addition, a small and inexpensive semiconductor device with low power consumption can be obtained. In the semiconductor device, the n transistor elements and the short-circuit transistor elements may have different cross-sectional structures and gate widths.

  According to an eighth aspect of the present invention, the transistor element and the short-circuit transistor element can be, for example, a lateral MOS transistor element suitable for use in the following SOI structure semiconductor substrate. The transistor element and the short-circuit transistor element may be an IGBT (Insulated Gate Bipolar Transistor) element.

  In the semiconductor device, the transistor element and the short-circuit transistor element are formed in an SOI layer of an SOI structure semiconductor substrate having a buried oxide film, and an insulating isolation trench reaching the buried oxide film is It can be configured to be insulated and separated from each other.

  When an SOI structure semiconductor substrate is used, as described in claim 10, the capacitor element includes the insulating isolation trench as a dielectric layer, and the SOI layers formed on both sides of the insulating isolation trench are electrode-connected. A configuration of layers can be employed.

  The capacitive element using the insulating isolation trench can ensure a high breakdown voltage of 400 V or more, and can reduce the area occupied by the chip because the capacitive element is formed in the depth direction of the substrate.

  In addition, according to an eleventh aspect, the capacitive element has a conductivity formed on the oxide film with the oxide film formed on the SOI layer serving as a dielectric layer and the oxide film interposed therebetween. A configuration may be adopted in which polysilicon is used as one electrode and the SOI layer under the oxide film is used as the other electrode connection layer.

  In this case, although the area efficiency is inferior to that of the capacitive element using the insulating isolation trench, there is no problem of constriction of the oxide film at the trench edge, so that the capacitive element can be made more reliable.

  14. The semiconductor device according to claim 12, wherein the semiconductor device includes a GND reference gate drive circuit based on a GND potential, a floating reference gate drive circuit based on a floating potential, the GND reference gate drive circuit, and the floating reference gate drive. A control circuit for controlling the circuit, and a level shift circuit which is interposed between the control circuit and the floating reference gate drive circuit and shifts an input / output signal of the control circuit between the GND potential and the floating potential. The inverter-driven high voltage IC is suitable for the level shift circuit. In this case, the predetermined potential becomes the floating potential.

  The high voltage IC may be, for example, a high voltage IC for driving an inverter of an in-vehicle motor as described in claim 13, or may be an inverter driving of an in-vehicle air conditioner, as described in claim 14. It may be a high voltage IC.

  The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a semiconductor device 200 as an example of the semiconductor device of the present invention.

In the semiconductor device 200 shown in FIG. 1, four transistor elements _Tr 1 to Tr ₄ which is insulated and separated from each other, between the GND potential (0V) and a predetermined power supply potential Vss (1000V), the first stage the GND side The power supply side is the fourth stage and is sequentially connected in series. The gate - four to-source shorted shunt transistor element _STR 1 ～STR ₄ is between the same GND potential and the power supply potential Vss, and the first stage the GND side, the power supply side as a fourth stage, sequentially They are connected in series. In the semiconductor device 200, the gate terminals of the transistor elements Tr _{2 to} Tr ₄ in each stage excluding the transistor element Tr ₁ in the first stage are connected between the short-circuit transistor elements STR _{1 to} STR _{4 in} each stage connected in series. Are sequentially connected to each other. In the figure, the resistor R _in (200 kΩ) is an input resistor, and the resistor R _out (10 kΩ) is an output resistor.

Note that the semiconductor device 200 shown in FIG. 1 includes four transistor elements Tr _{1 to} Tr ₄ and four short-circuit transistor elements STR _{1 to} STR ₄ . However, the present invention is not limited to this, and the effects of the semiconductor device 200 described below can be similarly obtained for a semiconductor device including any n (n ≧ 2) transistor elements and short-circuit transistor elements. Further, the four transistor elements _Tr 1 to Tr ₄ and the short-circuit transistor element _STR 1 ～STR ₄ of the semiconductor device 200 shown in FIG. 1 is a MOS transistor of N channel (Metal Oxide Semiconductor transistor), limited to Alternatively, an insulated gate bipolar transistor (IGBT, Insulated Gate Bipolar Transistor) or the like may be used.

In the semiconductor device 200 of FIG. 1, the gate terminal of the transistor elements Tr ₁ of the first stage is an input terminal of the input signal _{V in.} Further, the output signal V _Out of the semiconductor device 200 is taken out from the drain-side terminal of the fourth-stage transistor element Tr ₄ . In other words, the circuit of the semiconductor device 200 is a level shift circuit _in which the input signal Vin based on the GND potential (0 V) is converted into an output signal V _{Out based} on the power supply potential (1000 V) and extracted. Yes.

The short-circuit transistor elements STR _{1 to} STR ₄ in which the gate and the source are short-circuited in the semiconductor device 200 of FIG. 1 can function as diodes. For this reason, in the semiconductor device 200, the gate voltage dividing circuit of the main-line transistor elements Tr _{1 to} Tr ₄ sequentially connected in series between the GND potential and the predetermined power supply potential Vss is similarly connected between the GND potential and the power supply potential Vss. Are short-circuit transistor elements (diodes) STR _{1 to} STR ₄ connected in series. Therefore, in the semiconductor device 200 of FIG. 1, since no resistive element is used for the gate voltage dividing circuit line unlike the semiconductor devices 100 and 101 of FIG. 11 and FIG. 12, the gate voltage dividing circuit line is in a steady state ( Leakage) current does not flow, and this does not increase power consumption. Further, the area occupied by the short-circuit transistor elements STR _{1 to} STR _{4 in} the chip is smaller than that of the resistance element and the capacitance element, and this does not increase the cost.

In the semiconductor device 200 of FIG. 1, a resistor, a capacitor, as in the semiconductor device 100, 101 in FIGS. 11 and 12 used for the gate voltage divider circuit, the input to the gate terminal of the transistor elements Tr ₁ of the first stage by adding a signal _{V in,} it is possible via the four shunt transistor element _STR 1 _{~STR 4,} transistor elements _Tr 2 to Tr ₄ of the n-stage from the second stage is also simultaneously operated. In the semiconductor device 200, the voltage between the GND potential and the power supply potential Vss is divided by four transistor elements, and each transistor element in the first to fourth stages shares a voltage range. Therefore, as with the high voltage IC 91 in FIG. 10, the transistor elements Tr _{1 to} Tr ₄ are required compared to the case where the voltage between the GND potential and the power supply potential Vss is shared by one transistor element Tr _L. The breakdown voltage can be reduced.

In a semiconductor device in which the GND potential and a predetermined potential are divided and shared by the transistor elements of each stage of the main line, generally, the gate voltage dividing circuit line is configured together with the breakdown voltage of the transistor elements of each stage configuring the main line. The same breakdown voltage is required for each element. In this respect, the breakdown voltage of the short-circuit transistor elements (diodes) STR _{1 to} STR ₄ in which the gate and the source are short-circuited in the semiconductor device 200 of FIG. 1 is equal to or higher than that in the state where the gate and the source are not short-circuited. have. Accordingly, the semiconductor device 200 main lines and gate voltage divider circuit line consists essentially identical transistor elements _{Tr 1 ~Tr 4, STR 1 ~STR} 4 uses a diode element of a simple structure for example, the gate voltage dividing circuit lines semiconductor Compared with the device, the withstand voltage design becomes very easy.

In particular, in the semiconductor device 200 of FIG. 1, it is preferable that the transistor elements Tr _{1 to} Tr ₄ and the short-circuit transistor elements STR _{1 to} STR ₄ have the same cross-sectional structure in the channel length direction. The breakdown voltage of the transistor elements Tr _{1 to} Tr ₄ and STR _{1 to} STR ₄ is determined by the cross-sectional structure in the channel length direction. Therefore, when the sectional structure in the channel length direction of the short-circuit transistor element STR ₁ ~STR ₄ transistor elements Tr ₁ to Tr ₄ and the gate voltage dividing circuit line in the main line to the same breakdown voltage design is simplified At the same time, the withstand voltage characteristics of the two transistor elements Tr _{1 to} Tr ₄ and STR _{1 to} STR ₄ can be matched accurately. Moreover, even within each line, each transistor elements _Tr 1 _{to Tr} 4 constituting _it, because the breakdown voltage of the STR 1 ~STR ₄ are equal, GND potential and the transistor elements _Tr 1 ~ inserted between the predetermined potential The voltage (breakdown voltage) shared by Tr ₄ and STR _{1 to} STR ₄ can be made uniform and minimized. Further, since the semiconductor device 200 of FIG. 1, a small shift in the breakdown voltage characteristic of the short-circuit transistor element _STR 1 _{~STR 4} transistor elements _Tr 1 of the main line to Tr ₄ and the gate voltage dividing circuit line, GND potential and the power supply potential The voltage division ratio between Vss can also be made more accurate.

If the cross-sectional structures in the channel length direction are the same, the gate width in the direction orthogonal to the channel length direction of the transistor element hardly affects the breakdown voltage characteristics. For this reason, in the semiconductor device 200 of FIG. 1, the gate widths of the transistor elements Tr _{1 to} Tr _{4 in} the main line and the short circuit transistor elements STR _{1 to} STR _{4 in} the gate voltage dividing circuit line can be arbitrarily set. For example, in the semiconductor device 200 of FIG. 1, the gate widths of the _four transistor elements Tr _{1 to} Tr 4 constituting the main line can be set equal.

On the other hand, the transistor element has a parasitic capacitance, and the value of the parasitic capacitance is proportional to the gate width of the transistor element. By using this, in the semiconductor device 200 of FIG. 1, the gate widths of the short-circuit transistor elements STR _{1 to} STR ₃ in the (k−1) th stage (2 ≦ k ≦ 4) are the (k−1) th stage. It is preferable that the gate width of each transistor element located above is set to be approximately equal. For example, when the gate widths of the _four transistor elements Tr _{1 to} Tr 4 constituting the main line are set equal to w, the gate width of the third-stage short-circuit transistor element STR ₃ is set to w, and the second the gate width of the short-circuit transistor element STR ₂ stages is set to 2w, the gate width of the short-circuit transistor element STR ₁ of the first stage is set to 3w.

In the semiconductor device 200 of FIG. 1 in which the gate width is set as described above, the parasitic capacitance of the (k−1) -th (2 ≦ k ≦ 4) short-circuit transistor elements STR _{3 to} STR ₁ is (k -1) It is almost equal to the sum of the parasitic capacitances of the transistor elements above the stage. Therefore, in the semiconductor device 200 includes, in order from the power source side of the power supply potential Vss, and so as to correct the influence of a staged parasitic capacitance of the transistor elements Tr ₄ to Tr ₂ in the main line, the gate voltage dividing circuit line The parasitic capacitances of the short-circuit transistor elements STR _{3 to} STR ₁ in FIG. Thus, the transistor elements _Tr 1 _{to Tr} 4 of each _stage, STR 1 becomes ～STR ₄ hardly charges accumulate, the charges of the surge current can be released to quickly GND, the deterioration of the switching speed due to the multistage Can be suppressed. In the semiconductor device 200, the gate width of the fourth-stage short-circuit transistor element STR ₁ at the highest stage closest to the power supply potential Vss hardly affects the characteristics against the surge and the switching speed. For this reason, the gate width of the fourth-stage short-circuit transistor element STR ₁ can be set smaller than the gate width of the fourth-stage transistor element Tr ₄ .

The semiconductor device 200 mainly lines and gate voltage divider circuit line consists essentially identical transistor elements _{Tr 1 ~Tr 4, STR 1 ~STR} 4 is a semiconductor device using a diode element of a simple structure for example, the gate voltage dividing circuit line In comparison, the manufacturing process is also very simple. Manufacturing process of the semiconductor device 200 may be configured only in the process of manufacturing the transistor elements _{Tr 1 ~Tr 4, STR 1 ~STR} 4 which can be simultaneously formed, is easy to the number of steps is small process control, low cost semiconductor device 200 Can be manufactured.

When a surge is applied to the semiconductor device 200 of FIG. 1, the gate voltage dividing circuit is similar to the semiconductor devices 100 and 101 of FIG. 11 and FIG. through the first stage from the fourth stage the shorting transistor element _STR 1 ～STR ₄ of the line, immediately the charge of the surge current can escape to the GND. For this reason, a high voltage due to a surge is not applied to the specific transistor elements Tr _{1 to} Tr ₄ in the main line. Accordingly, circuit breakdown due to breakdown of the transistor elements Tr _{1 to} Tr ₄ when a surge is applied can be suppressed.

  As described above, the semiconductor device 200 of FIG. 1 is a semiconductor device in which n (n ≧ 2) transistor elements that are insulated from each other are sequentially connected in series, and has a high breakdown voltage required as a whole. Thus, a small and inexpensive semiconductor device with low power consumption can be obtained.

Next, a description will be given of the result of confirming the characteristics by simulation for the effect of the semiconductor device 200 described above. In the simulation of the semiconductor device 200 shown below, the transistor elements Tr _{1 to} Tr _{4 in} the main line all have the same cross-sectional structure in the channel length direction, and the channel widths w are all equal to 90 μm. The short-circuit transistor elements STR _{1 to} STR ₄ in the gate voltage dividing circuit line all have the same cross-sectional structure in the channel length direction as the transistor elements Tr _{1 to} Tr _4, and are multistaged as described above. In order to correct the influence of the parasitic capacitances of the transistor elements Tr _{4 to} Tr ₂ , the channel width w of each of the STR _{1 to} STR ₄ is set to 360 μm, 180 μm, 90 μm, and 10 μm.

Figure 2 is a simulation result of the response characteristic (switching waveform) with respect to the pulse signal input in the semiconductor device 200 of FIG. 1 is a diagram showing the voltage waveforms at both ends of the output resistor R _out to the pulse input. As shown in FIG. 2, in the semiconductor device 200, a good rectangular wave is observed at the output resistance terminal for both rising and falling, and the transistor elements Tr _{1 to} Tr ₄ connected in series on the main line operate normally. Was confirmed.

FIG. 3 is a simulation result of response characteristics (dV / dt response waveform) when a dV / dt surge is applied in the semiconductor device 200 of FIG. FIG. 3A is an equivalent circuit diagram used in the simulation, and FIG. 3B is a diagram showing a voltage waveform between the source and drain of each of the transistor elements Tr _{1 to} Tr ₄ when a dV / dt surge is applied. It is.

As shown in the equivalent circuit diagram 200a of FIG. 3 (a), dV / in dt simulation of the response characteristics when a surge is applied, shorting the gate terminal of the first stage transistor element Tr ₁ in the semiconductor device 200 of FIG. 1 to GND The simulation is performed by applying a surge voltage of 1000 V to the power supply side. As shown in FIG. 3B, in the semiconductor device 200, it was confirmed that the surge voltage was evenly distributed to the transistor elements Tr _{1 to} Tr ₄ connected in series on the main line. It can be seen that the equal distribution of the surge voltage to the transistor elements Tr ₁ to Tr ₄ is ensured not only in the steady state but also at the rising time.

FIG. 4 is a specific structural example of the semiconductor device 200 shown in FIG. 1, and in the semiconductor device 200 applied to the level shift circuit of the high voltage IC 210, the transistor elements Tr _{1 to} Tr connected in series constituting the main line. It is a figure which shows the cross-section of the channel length direction of _n (n> = 2).

The transistor elements Tr _{1 to} Tr _n of the semiconductor device 200 shown in FIG. 4 are N-channel lateral MOS transistor elements (LDMOS, Lateral Diffused Metal Oxide Semiconductor) suitable for use with an SOI structure semiconductor substrate. In the semiconductor device 200 of FIG. 4, transistor elements (LDMOS) Tr _{1 to} Tr _n are formed in the SOI layer 1 of the SOI structure semiconductor substrate 11 having the buried oxide film 3, and the insulating isolation trench 4 reaching the buried oxide film 3. Are isolated from each other. Note that the serially connected short-circuit transistor elements STR _{1 to} STR _n (n ≧ 2) constituting the gate voltage dividing circuit line also have the same channel length direction cross-sectional structure and the SOI layer 1 of the same SOI structure semiconductor substrate 11. Can be formed.

  FIG. 5 is a circuit diagram of the semiconductor device 201 as another example of the semiconductor device according to the present invention. In the semiconductor device 201 of FIG. 5, the same reference numerals are given to the same parts as those of the semiconductor device 200 of FIG.

The semiconductor device shown in FIG. 5 201, for each of the four short in the semiconductor device 200 transistor device _STR 1 ～STR ₄ shown in FIG. 1, a capacitor _C 1 -C ₄ becomes parallel connected to each Yes. That is, the semiconductor device 201 of FIG. 5 has a configuration in which a short-circuit transistor element and a capacitor element connected in parallel are used in each stage of the gate voltage dividing circuit line. Also in this case, as described in the semiconductor device 200 of FIG. 1, since no resistance element is used for the gate voltage dividing circuit line, no (leakage) current flows in the gate voltage dividing circuit line in a steady state. A semiconductor device with low power consumption can be obtained.

In the semiconductor device 201 of FIG. 5, the shunt transistor element _STR 1 by the capacitor _C 1 -C ₄ are connected in parallel to the respective ～STR _4, a staged transistor element _Tr 1 to Tr in the main line The influence of the parasitic capacitance of ₄ can be corrected. For this reason, in the semiconductor device 201, the cross-sectional structure in the channel length direction and the gate width in the n (n ≧ 2) transistor elements and the short-circuit transistor elements can all be set equal. However, the present invention is not limited to this, and the n transistor elements and the short-circuit transistor elements may have different cross-sectional structures and gate widths.

  As described above, the semiconductor device 201 in FIG. 5 is also a semiconductor device in which n (n ≧ 2) transistor elements that are insulated from each other are sequentially connected in series, and has a high breakdown voltage required as a whole. Thus, a small and inexpensive semiconductor device with low power consumption can be obtained.

Figure 6 is a simulation result of the response characteristic (switching waveform) with respect to the pulse signal input in the semiconductor device 201 of FIG. 5 is a diagram showing the voltage waveforms at both ends of the output resistor R _out to the pulse input. FIG. 7 is a simulation result of response characteristics (dV / dt response waveform) when a dV / dt surge is applied in the semiconductor device 201 of FIG. 5, and each of the transistor elements Tr _{1 to} Tr ₄ when a dV / dt surge is applied. It is a figure which shows a drain electric potential waveform. In the simulation of FIG. 6 and FIG. 7, the transistor elements _Tr 1 to Tr ₄ and the short-circuit transistor element _STR 1 _{~STR 4} in the semiconductor device 201 of FIG. 5, and all have the same channel length direction of the sectional structure The channel widths w are all equal to 100 μm. The capacitive elements C _{1 to} C ₄ all have the same capacitance value of ₁ pF. Further, in the simulation of the response characteristics when the dV / dt surge is applied in FIG. 7, the first stage transistor element Tr ₁ of the semiconductor device 201 is similar to the equivalent circuit diagram 200a of the semiconductor device 200 shown in FIG. The simulation is performed by short-circuiting the gate terminal to GND and applying a surge voltage of 1000 V to the power supply side.

As shown in FIG. 6, also in the semiconductor device 201, a rectangular wave with good rising and falling edges is observed at the output resistance terminal, and the transistor elements Tr _{1 to} Tr ₄ connected in series on the main line operate normally. I was able to confirm. Further, as shown in FIG. 7, it was confirmed that the surge voltage was evenly distributed to the transistor elements Tr _{1 to} Tr ₄ connected in series in the main line also in the semiconductor device 201.

Also in the semiconductor device 201 of FIG. 5, the transistor elements Tr _{1 to} Tr _n and the short-circuit transistor elements STR _{1 to} STR _n are formed in the SOI layer 1 of the SOI structure semiconductor substrate 11 as shown in FIG. be able to. When the semiconductor device 201 of FIG. 5 is formed using the SOI structure semiconductor substrate, the capacitor elements C _{1 to} C ₄ are also formed on the same SOI structure semiconductor substrate as the transistor elements Tr _{1 to} Tr _n and the short-circuit transistor elements STR _{1 to} STR _n. can do.

  FIGS. 8A and 8B are examples of forming capacitive elements when an SOI structure semiconductor substrate is used, and are perspective views showing the capacitive elements Ca and Cb in partial cross sections, respectively. Note that the SOI structure semiconductor substrate 11 on which the capacitive elements Ca and Cb of FIGS. 8A and 8B are formed is the same as the SOI structure semiconductor substrate 11 shown in FIG. Yes.

  In the capacitive element Ca shown in FIG. 8A, the insulating isolation trench 4 is a dielectric layer, and the SOI layers 1 formed on both sides of the insulating isolation trench 4 are electrode connection layers. The capacitive element Ca using the insulating isolation trench 4 can ensure a high breakdown voltage of 400 V or more, and the capacitive element Ca is formed in the depth direction of the substrate 11, so that the area occupied by the chip is reduced. Can do.

  The capacitive element Cb shown in FIG. 8B has conductivity formed on the oxide film 2 with the oxide film 2 such as LOCOS formed on the SOI layer 1 as a dielectric layer and the oxide film 2 interposed therebetween. Polysilicon 5 is used as one electrode, and SOI layer 1 under oxide film 2 is used as the other electrode connection layer. The capacitive element Cb is less reliable than the capacitive element Ca using the insulating isolation trench 4 in FIG. 8A, but is more reliable because it has no problem of narrowing of the oxide film at the trench edge. A capacitive element can be used.

  The semiconductor devices 200 and 201 described above include a high voltage IC for driving an inverter, which includes a GND reference gate drive circuit, a floating reference gate drive circuit, a control circuit, and a level shift circuit as shown in FIG. 9B. Are suitable for semiconductor devices used in level shift circuits. A high voltage IC using the semiconductor devices 200 and 201 shown in FIG. 1 and FIG. 5 can ensure a high breakdown voltage required as a whole, has low power consumption, is a small and inexpensive semiconductor device, A high voltage IC suitable for driving an inverter of an in-vehicle motor or an inverter of an in-vehicle air conditioner can be obtained. However, the application target of the non-conductor device of the present invention is not limited to this, and can also be applied to the field of consumer / industrial motor control.

3 is a circuit diagram of a semiconductor device 200 as an example of the semiconductor device of the present invention. FIG. It is a simulation result of response characteristics to a pulse signal input in the semiconductor device 200, and is a diagram illustrating a voltage waveform at both ends of an output resistance _Rout with respect to the pulse input. In the simulation result of the response characteristics at the time of dV / dt surge applied in the semiconductor device 200, (a) is an equivalent circuit diagram used in the simulation, (b) each of the transistor elements _Tr 1 ~ at dV / dt surge applied is a diagram illustrating voltage waveforms between the source and the drain of tr _4. In a specific structural example of the semiconductor device 200, in the semiconductor device 200 applied to the level shift circuit of the high voltage IC 210, the channels of the transistor elements Tr _{1 to} Tr _n (n ≧ 2) connected in series constituting the main line It is a figure which shows the cross-section of a length direction. FIG. 10 is a circuit diagram of a semiconductor device 201 as another example of the semiconductor device according to the present invention. FIG. 6 is a diagram showing a voltage waveform at both ends of an output resistance _Rout for a pulse input as a result of a simulation of response characteristics for a pulse signal input in the semiconductor device 201. FIG. 6 is a diagram showing simulation results of response characteristics when a dV / dt surge is applied in the semiconductor device 201, and shows drain potential waveforms of the transistor elements Tr _{1 to} Tr ₄ when a dV / dt surge is applied. (A), (b) is the formation example of the capacitive element at the time of using an SOI structure semiconductor substrate, and is the perspective view which each showed capacitive element Ca and Cb in the partial cross section. (A) is a circuit block diagram centering on the power part of the inverter for motor control currently disclosed by patent document 1. FIG. (B) is a block diagram of an internal configuration unit of a high voltage IC (HVIC) used in (a). It is a typical sectional view of conventional high voltage IC91 using SOI substrate and trench isolation. 1 is a basic circuit diagram of a novel semiconductor device 100. FIG. FIG. 10 is a schematic diagram showing a basic configuration of another semiconductor device, and is a circuit diagram of the semiconductor device 101.

Explanation of symbols

100,101,200,201 semiconductor device Tr ₁ ~Tr _4, Tr _n transistor elements STR ₁ ~STR ₄ shorting transistor element R _in the input resistance R _out output resistance _{C2, C 1 ~C 4, Ca} , Cb capacitive element Vss power supply Potential 10, 11 SOI substrate 1 SOI layer 2 Oxide film 3 Buried oxide film 4 Insulation isolation trench 5 Polysilicon 90, 91 High voltage IC

Claims (14)

N (n ≧ 2) transistor elements that are isolated from each other are sequentially connected in series between the ground (GND) potential and a predetermined potential, with the GND potential side as the first stage and the predetermined potential side as the nth stage. Being
The gate terminal in the first stage transistor element is an input terminal,
Without using a resistive element as a gate voltage dividing circuit of transistor elements sequentially connected in series between the GND potential and a predetermined potential,
N short-circuit transistor elements whose gates and sources are short-circuited are sequentially connected in series between the GND potential and the predetermined potential, with the GND potential side as the first stage and the predetermined potential side as the nth stage,
The gate terminals of the transistor elements of each stage excluding the first stage transistor element are sequentially connected between the short-circuit transistor elements of each stage connected in series,
A semiconductor device, wherein an output is taken out from a terminal on the predetermined potential side in the n-th transistor element.   2. The semiconductor device according to claim 1, wherein the transistor element and the short-circuit transistor element have the same cross-sectional structure in the channel length direction.   3. The semiconductor device according to claim 2, wherein gate widths of the n transistor elements are set to be equal. The gate width of the first (k-1) shorting transistor of the stage (2 ≦ k ≦ n) is the sum of the gate width of each transistor device is above the first (k-1) stage, it is equally set correctly The semiconductor device according to claim 2 or 3, wherein   5. The gate width of the nth stage short-circuit transistor element is set to be smaller than a gate width of the nth stage transistor element. 6. Semiconductor device. The gate widths of the n transistor elements and the n short-circuit transistor elements are set to be equal,
3. The semiconductor device according to claim 2, wherein a capacitance element is connected in parallel to each of the n short-circuit transistor elements. N (n ≧ 2) transistor elements that are isolated from each other are sequentially connected in series between the ground (GND) potential and a predetermined potential, with the GND potential side as the first stage and the predetermined potential side as the nth stage. Being
The gate terminal in the first stage transistor element is an input terminal,
Without using a resistive element as a gate voltage dividing circuit of transistor elements sequentially connected in series between the GND potential and a predetermined potential,
N short-circuit transistor elements whose gates and sources are short-circuited are sequentially connected in series between the GND potential and the predetermined potential, with the GND potential side as the first stage and the predetermined potential side as the nth stage,
The gate terminals of the transistor elements of each stage excluding the first stage transistor element are sequentially connected between the short-circuit transistor elements of each stage connected in series,
Capacitance elements are connected in parallel to each of the n short-circuit transistor elements,
A semiconductor device, wherein an output is taken out from a terminal on the predetermined potential side in the n-th transistor element.   8. The semiconductor device according to claim 1, wherein the transistor element and the short-circuit transistor element are lateral MOS transistor elements. The transistor element and the short-circuit transistor element are formed in an SOI layer of an SOI structure semiconductor substrate having a buried oxide film;
9. The semiconductor device according to claim 1, wherein the semiconductor devices are isolated from each other by an insulating isolation trench reaching the buried oxide film. 10.   10. The semiconductor device according to claim 9, wherein the capacitive element uses the insulating isolation trench as a dielectric layer, and uses SOI layers formed on both sides of the insulating isolation trench as electrode connection layers.   The capacitor element includes an oxide film formed on the SOI layer as a dielectric layer, and conductive polysilicon formed on the oxide film with the oxide film interposed therebetween as one electrode, The semiconductor device according to claim 9, wherein the SOI layer is used as the other electrode connection layer. The semiconductor device is
A GND reference gate drive circuit based on a GND potential, a floating reference gate drive circuit based on a floating potential, a control circuit for controlling the GND reference gate drive circuit and the floating reference gate drive circuit, and the control circuit; In a high voltage IC for driving an inverter, which is interposed between the floating reference gate driving circuit and configured by a level shift circuit for level shifting an input / output signal of the control circuit between a GND potential and a floating potential.
The predetermined potential as a floating potential,
The semiconductor device according to claim 1, wherein the semiconductor device is applied to the level shift circuit.   The semiconductor device according to claim 12, wherein the high voltage IC is a high voltage IC for driving an inverter of an in-vehicle motor.   13. The semiconductor device according to claim 12, wherein the high voltage IC is a high voltage IC for driving an inverter of an in-vehicle air conditioner.

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