JPH0418732A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0418732A JPH0418732A JP2121844A JP12184490A JPH0418732A JP H0418732 A JPH0418732 A JP H0418732A JP 2121844 A JP2121844 A JP 2121844A JP 12184490 A JP12184490 A JP 12184490A JP H0418732 A JPH0418732 A JP H0418732A
- Authority
- JP
- Japan
- Prior art keywords
- stress
- bumps
- integrated circuit
- circuit device
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000035882 stress Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 239000004840 adhesive resin Substances 0.000 description 3
- 229920006223 adhesive resin Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000006355 external stress Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特にその突起電極
の配置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to the arrangement of protruding electrodes thereof.
近年、電子回路の高密度実装技術の進展は目覚ましく、
特に、半導体応用製品の高機能化、高密度化の中心は、
モノリシックICの大規模化およびマルチチップ実装を
指向している。これらの高密度実装に応える一手段とし
て、半田突起電極を有するフリップチップICが採用さ
れてきている。In recent years, high-density packaging technology for electronic circuits has made remarkable progress.
In particular, the focus of increasing the functionality and density of semiconductor application products is
The aim is to increase the scale of monolithic ICs and implement multi-chip implementation. Flip chip ICs having solder protrusion electrodes have been adopted as a means of meeting these high-density packaging requirements.
フリップチップICを用いたフェースダウンボンディン
グをICの実装方法として採用する目的は、第1に高密
度実装、第2に組立プロセスの簡便化、第3に接続部の
機械的強度の向上環があげられる。特に自動車用のハイ
ブリッドICでは、高信頼性の要求から、接続部の強度
向」二が重視される。The objectives of adopting face-down bonding using flip-chip IC as an IC mounting method are: firstly, high-density mounting, secondly, simplifying the assembly process, and thirdly, improving the mechanical strength of the connection part. It will be done. Particularly in the case of hybrid ICs for automobiles, the strength of the connection parts is emphasized due to the requirement for high reliability.
第2図は、従来採用されているフリップチップICの電
極配置およびその実装例を示す構成図である。FIG. 2 is a configuration diagram showing the electrode arrangement of a conventionally employed flip-chip IC and an example of its mounting.
第2図(alはフリップチップICIの突起電極(以下
「ハンプ」という)2の配置を示すものであり、ICの
パターン設計上量もパターン効率が良い最外周にバンプ
2を配置している。FIG. 2 (al) shows the arrangement of protruding electrodes (hereinafter referred to as "humps") 2 of the flip chip ICI, and the bumps 2 are arranged at the outermost periphery where the pattern efficiency is good in terms of IC pattern design.
第2図fb)は、(alで示したフリップチップICI
を実装したハイブリッドICの構成図である。同図にお
いて、フリップチップICIは、導体配線が施されたセ
ラミック基板3上に半田付けされ、さらにセラミック基
板3は放熱のためヒートシンク4に接着樹脂5を介して
接着されている。そして、ヒートシンク4にケース6が
取り付けられている。このハイブリッドICは、最終的
にユーザのセントに組み付けられる際、ねし7によって
締めイ1けられるため、ヒートシンク4の平面度や反り
の状態によって、第2図(C1の矢印ARで示すように
、ねじ締め方向の応力がハイブリッドIC内部に加わる
ことがある。Fig. 2 fb) is a flip chip ICI shown in (al)
1 is a configuration diagram of a hybrid IC implemented with the following. In the figure, the flip chip ICI is soldered onto a ceramic substrate 3 provided with conductive wiring, and the ceramic substrate 3 is further bonded to a heat sink 4 via an adhesive resin 5 for heat radiation. A case 6 is attached to the heat sink 4. When this hybrid IC is finally assembled into the user's socket, it is tightened by the screws 7, so depending on the flatness and warpage of the heat sink 4, the , stress in the screw tightening direction may be applied inside the hybrid IC.
従来のフリップチップICを実装したハイブリッドIC
は以」二のように構成されているため、ねじ締めによる
応力方向ARが実装されたフリップチップICIの対角
線方向と一致した場合、その応力綿l〕付近に有るフリ
ップデツプICIのコーナバンプ2の半田付は部分に応
力が集中し、実使用において断線に至るという問題があ
った。Hybrid IC mounted with conventional flip chip IC
Since the structure is as shown in 2 below, when the stress direction AR due to screw tightening matches the diagonal direction of the mounted flip chip ICI, the soldering of the corner bump 2 of the flip deep ICI near the stress thread 1] However, there was a problem in that stress was concentrated in some parts, leading to wire breakage in actual use.
本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、フリソフ゛チソフ。The present invention has been made in view of the above points, and its purpose is to improve the performance of Frisoftisof.
ICのコーナハンプの半田付は部分に集中する応力を他
のハンプに分散し、特定方向の応力に対する従来品の弱
点を解消し、信頼性の高いハイブリッドICを提供する
ことにある。The purpose of soldering IC corner humps is to disperse the stress concentrated in one part to other humps, eliminate the weakness of conventional products against stress in a specific direction, and provide a highly reliable hybrid IC.
このような課題を解決するために本発明は、複数個の突
起電極を同心円状に配置するようにしたものである。In order to solve this problem, the present invention arranges a plurality of protruding electrodes concentrically.
本発明による半導体集積回路装置においては、あらゆる
方向からの応力に対し常に一定の応力分散が実現可能と
なり、信頼性の向上が図れる。In the semiconductor integrated circuit device according to the present invention, constant stress distribution can always be achieved against stress from all directions, and reliability can be improved.
以下、本発明の実施例について説明する。第1図におい
て、(a+は本発明による半導体集積回路装置の一実施
例としてのフリップチップICのバンプの配置を示す構
成図であり、(blはta+で示したフリップチップT
CIを実装したハイブリッドICの構成図である。第1
図(b)において、フリップチップIC1は導体配線が
施されたセラミック基板3上に半田付げされ、さらにセ
ラミック基板3は放熱のためヒートシンク4に接着樹脂
5を介して接着されている。そして、ヒートシンク4に
ケース6が取り付けられている。Examples of the present invention will be described below. In FIG. 1, (a+ is a configuration diagram showing the bump arrangement of a flip chip IC as an embodiment of the semiconductor integrated circuit device according to the present invention, and (bl is a flip chip T shown as ta+).
FIG. 1 is a configuration diagram of a hybrid IC equipped with a CI. 1st
In Figure (b), the flip chip IC 1 is soldered onto a ceramic substrate 3 provided with conductive wiring, and the ceramic substrate 3 is further bonded to a heat sink 4 via an adhesive resin 5 for heat radiation. A case 6 is attached to the heat sink 4.
このハイブリッドICは、最終的にユーザのセットに組
み付けられる際、ねし7によって締め付けられ°ζ使用
される。When this hybrid IC is finally assembled into a user's set, it is tightened with screws 7 and used.
上述したように、バンプ2を第1図の点線で示すように
同心円状にフリップチップrC1に配置した場合、ヒー
トシンク4のねじ締め方向からの応力がハンプ2の半田
付は部分に加わっても、隣接ハンプへの応力分散がなさ
れるため、特定方向からの応力に対し各ハンプは平均的
に応力を受けることとなり、特定ハンプへの応力集中を
防ぐことが可能となる。As described above, when the bumps 2 are arranged concentrically on the flip chip rC1 as shown by the dotted lines in FIG. Since stress is distributed to adjacent humps, each hump receives an average stress from stress from a specific direction, making it possible to prevent stress from concentrating on a specific hump.
なお、第1図の点線は同心円状であることを示すための
みの線であり、実際にこのような点線がフリップチップ
ICI上に描かれている訳ではない。Note that the dotted lines in FIG. 1 are only lines to indicate concentric circles, and such dotted lines are not actually drawn on the flip chip ICI.
以上説明したように本発明は、複数個の突起電極を同心
円状に配置するようにしたことにより、あらゆる方向か
らの外部応力に対して応力分散することが可能となるの
で、信頼性の高い半導体集積回路装置を提供できる効果
がある。As explained above, in the present invention, by arranging a plurality of protruding electrodes concentrically, it is possible to disperse external stress from all directions. This has the effect of providing an integrated circuit device.
第1図は本発明による半導体集積回路装置の一実施例を
示す構成図、第2図は従来の半導体集積回路装置を示す
構成図である。
1・・・フリップチップIC,2・・・バンプ、3・・
・セラミック基板、4・・・ヒートシンク、5・・・接
着樹脂、6・・・ケース、7・・・ねじ。FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a block diagram showing a conventional semiconductor integrated circuit device. 1...Flip chip IC, 2...Bump, 3...
- Ceramic board, 4... Heat sink, 5... Adhesive resin, 6... Case, 7... Screw.
Claims (1)
て、前記複数個の突起電極を同心円状に配置したことを
特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device having a plurality of protruding electrodes, wherein the plurality of protruding electrodes are arranged concentrically.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2121844A JPH0418732A (en) | 1990-05-12 | 1990-05-12 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2121844A JPH0418732A (en) | 1990-05-12 | 1990-05-12 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0418732A true JPH0418732A (en) | 1992-01-22 |
Family
ID=14821336
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2121844A Pending JPH0418732A (en) | 1990-05-12 | 1990-05-12 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0418732A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000033455A1 (en) * | 1998-12-02 | 2000-06-08 | Seiko Epson Corporation | Piezoelectric device and method of manufacture thereof |
WO2006090805A1 (en) * | 2005-02-23 | 2006-08-31 | Sony Corporation | Oscillatory gyro sensor |
JP2007173335A (en) * | 2005-12-20 | 2007-07-05 | Matsushita Electric Ind Co Ltd | Electronic component |
-
1990
- 1990-05-12 JP JP2121844A patent/JPH0418732A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000033455A1 (en) * | 1998-12-02 | 2000-06-08 | Seiko Epson Corporation | Piezoelectric device and method of manufacture thereof |
US6762537B1 (en) | 1998-12-02 | 2004-07-13 | Seiko Epson Corporation | Piezoelectric device and method for manufacture thereof |
WO2006090805A1 (en) * | 2005-02-23 | 2006-08-31 | Sony Corporation | Oscillatory gyro sensor |
JP2006284551A (en) * | 2005-02-23 | 2006-10-19 | Sony Corp | Oscillating gyro sensor |
JP2007173335A (en) * | 2005-12-20 | 2007-07-05 | Matsushita Electric Ind Co Ltd | Electronic component |
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