JPH02122556A - Method of mounting semiconductor device - Google Patents
Method of mounting semiconductor deviceInfo
- Publication number
- JPH02122556A JPH02122556A JP27646188A JP27646188A JPH02122556A JP H02122556 A JPH02122556 A JP H02122556A JP 27646188 A JP27646188 A JP 27646188A JP 27646188 A JP27646188 A JP 27646188A JP H02122556 A JPH02122556 A JP H02122556A
- Authority
- JP
- Japan
- Prior art keywords
- lead pins
- printed wiring
- pads
- wiring board
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000005476 soldering Methods 0.000 claims abstract description 10
- 229910000679 solder Inorganic materials 0.000 abstract description 11
- 230000005496 eutectics Effects 0.000 abstract description 5
- 238000005452 bending Methods 0.000 abstract description 4
- 239000004593 Epoxy Substances 0.000 abstract description 2
- 229910020220 Pb—Sn Inorganic materials 0.000 abstract 1
- 239000011521 glass Substances 0.000 abstract 1
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000005219 brazing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の実装方法に関し、特にパッド・グ
リッド・アレイ・パッケージ型の半導体装置の実装方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for mounting a semiconductor device, and particularly to a method for mounting a pad grid array package type semiconductor device.
ビン・グリッド・アレイ・パッケージ型半導体装置のピ
ンの代りにバットを設けたパッド・グリッド・アレイ・
パッケージ（以下ＰＧＡパッケージと記す）型半導体装
置が知られている。Bin Grid Array Packaged Pad Grid Array with Butts Instead of Pins in Packaged Semiconductor Devices
Package (hereinafter referred to as PGA package) type semiconductor devices are known.
第４図（ａ）、（ｂ）はＰＧＡパッケージ型半導体装置
の一例を示す底面図及び側面図である。FIGS. 4(a) and 4(b) are a bottom view and a side view showing an example of a PGA package type semiconductor device.
第４図（ａ＞、（ｂ）に示すように、ＰＧＡパッケージ
６の底面にパッド７が配列されて設けられ、セラミック
基板等を使用した平坦性の良い印刷配線板に実装する場
合には、前記印刷配線板上に設けた突起電極にフェース
ダウンボンディングして直接半導体装置と印刷配線板の
回路を接続することができるが、樹脂系基板を使用した
印刷配線板には不適当な実装方法である。As shown in FIGS. 4(a) and 4(b), pads 7 are arranged on the bottom surface of the PGA package 6, and when the pads 7 are mounted on a printed wiring board with good flatness using a ceramic substrate or the like, Although it is possible to connect the semiconductor device and the printed wiring board circuit directly by face-down bonding to the protruding electrodes provided on the printed wiring board, this mounting method is not suitable for printed wiring boards using resin-based substrates. be.
第５図（ａ）〜（ｃ）は従来の半導体装置の実装方法の
第１の例を説明するためのＰＧＡパッケージの側面図及
び印刷配線板の一部切欠側面図である。FIGS. 5(a) to 5(c) are a side view of a PGA package and a partially cutaway side view of a printed wiring board for explaining a first example of a conventional semiconductor device mounting method.
第５図（ａ）に示すように、ＰＧＡパッケージ６はセラ
ミック容器の底面に設けたタングステン層の表面にニッ
ケルめっきを施したパッド７を２．５關のピッチで配列
して設け、パッド７のそれぞれに０ 、４６ ｍｍ径で
長さ４市のコバールからなり表面を金めっきしたリード
ピン１２の先端をＡｇ−Ｃｕろう材１３によりろう付け
し、表面をＰｂ−５ｎ共晶半田で被覆し、予備半田層を
設ける。As shown in FIG. 5(a), the PGA package 6 has nickel-plated pads 7 arranged at a pitch of 2.5 on the surface of a tungsten layer provided on the bottom of the ceramic container. The tips of the lead pins 12, each made of Kovar with a diameter of 0 mm and 46 mm and a length of 4 mm and whose surfaces were gold-plated, were brazed with Ag-Cu brazing material 13, and the surfaces were coated with Pb-5n eutectic solder. Provide a solder layer.
次に、第５図（ｂ）に示すように、樹脂系の印刷配線板
１にリードピン１２の配列に対応してスルーホール２を
設ける。Next, as shown in FIG. 5(b), through holes 2 are provided in the resin printed wiring board 1 in correspondence with the arrangement of the lead pins 12.
次に、第５図（Ｃ）に示すように、リードピン１２をス
ルーホール２に挿入してリフロー法又は蒸気相半田付法
によりＰＧＡパッケージ６と印刷配線板１を電気的に接
続する。Next, as shown in FIG. 5C, the lead pins 12 are inserted into the through holes 2, and the PGA package 6 and the printed wiring board 1 are electrically connected by a reflow method or a vapor phase soldering method.
第６図（ａ）〜（ｃ）は従来の半導体装置の実装方法の
第２の例を説明するためのＰＧＡパッケージの側面図及
び印刷配線板の一部切欠側面図である。FIGS. 6(a) to 6(c) are a side view of a PGA package and a partially cutaway side view of a printed wiring board for explaining a second example of a conventional semiconductor device mounting method.
第６図（ａ）に示すように、第１の従来例と同様にして
設けたパッド７が１．２７ｍ＋ｎのピッチで配列され、
各パッド７にリードピン１２がろう付けされる。As shown in FIG. 6(a), pads 7 provided in the same manner as in the first conventional example are arranged at a pitch of 1.27m+n,
A lead pin 12 is brazed to each pad 7.
次に、第６図（ｂ）に示すように、印刷配線板６の表面
にリードピン１２の配列に対応して接続用ランド１３を
設ける。Next, as shown in FIG. 6(b), connection lands 13 are provided on the surface of the printed wiring board 6 in correspondence with the arrangement of the lead pins 12.
次に第６図（Ｃ）に示すように、リードピン１２と接続
用ランド１３のそれぞれの表面にＰｂ５ｎ共晶半田を設
けて予備半田とし、リードピン１２の先端と対応する接
続ランド１３とを位置決めにより突き合わせ、リフロー
法又は蒸気相半田付は法により半田付けしてＰＧＡパッ
ケージと印刷配線板１を電気的に接続する。Next, as shown in FIG. 6(C), Pb5n eutectic solder is provided on each surface of the lead pin 12 and the connection land 13 as a preliminary solder, and the tip of the lead pin 12 and the corresponding connection land 13 are aligned by positioning. The PGA package and the printed wiring board 1 are electrically connected to each other by soldering using a butting method, a reflow method, or a vapor phase soldering method.
しかしながら、上述した従来の半導体装置の実装方法は
、リードピンがＰＧＡパッケージのパッドに＾ｇ−Ｃｕ
ろう材により接続されている為にパッケージコストが高
くなる上にこのパッケージに半導体チップを搭載しアセ
ンブリする工程においてリードピンが作業性を悪くした
り、リードピン自身が曲がったりする様な好ましくない
現象が発生する問題点があった。However, in the conventional semiconductor device mounting method described above, the lead pins are attached to the pads of the PGA package using ^g-Cu.
Since the lead pins are connected by brazing metal, the package cost is high, and in the process of mounting and assembling the semiconductor chip in this package, undesirable phenomena such as lead pins impairing workability or bending of the lead pins themselves occur. There was a problem.
本発明の半導体装置の実装方法は、パッド・グリッド・
アレイ・パッケージ型の半導体装置の実装方法において
、前記半導体装置のパッドの配置に対応して印刷配線板
に設けたスルーホールにリードピンを挿入して半田付け
し、前記リードピンの先端に対応する前記パッドのそれ
ぞれを突き合わせて位置決めし、前記リードピンの先端
と前記パッドを半田付けして前記半導体装置と前記印刷
配線板を電気的に接続する手段を含んで構成される。The semiconductor device mounting method of the present invention includes pads, grids,
In a method for mounting an array package type semiconductor device, lead pins are inserted into through holes provided in a printed wiring board corresponding to the arrangement of pads of the semiconductor device and soldered to the pads corresponding to the tips of the lead pins. The semiconductor device and the printed wiring board are electrically connected by positioning the lead pins against each other and soldering the tips of the lead pins and the pads.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｆ＞は本発明の第１の実施例を説明す
るための工程順に示した平面図及び一部切欠側面図であ
る。FIGS. 1(a) to 1(f) are a plan view and a partially cutaway side view showing the steps of the first embodiment of the present invention.
まず、第１図（ａ）、（ｂ）に示すように、ガラス・エ
ポキシ銅張積層板からなる印刷配線板１に０．２５〜０
．３＋＋ｕｎ径のスルーホール２を１．２７〜１．５ｍ
ｍのスルーホールピッチ３で配列して設ける。ここで、
スルーホール周縁には０．５關径のランド（図示せず）
が設けられている。First, as shown in FIGS. 1(a) and 1(b), a printed wiring board 1 made of a glass-epoxy copper-clad laminate is coated with 0.25 to 0.0
．． 3++un diameter through hole 2 1.27~1.5m
They are arranged and provided with a through hole pitch of 3 m. here,
A land with a diameter of 0.5 on the periphery of the through hole (not shown)
is provided.
次に、第１図（ｃ）、（ｄ）に示すように、スルーホー
ル２に０．２〜０．２５＋ｍ径のリードピン４を挿入し
Ｐｂ−５ｎ共晶半田５を用いデイツプ半田付法によりリ
ードピン４を印刷配線板１に固着すると共に、リードピ
ン４の表面に半田層を形成する。Next, as shown in FIGS. 1(c) and 1(d), a lead pin 4 with a diameter of 0.2 to 0.25+m is inserted into the through hole 2, and dip soldering is performed using Pb-5n eutectic solder 5. The lead pins 4 are fixed to the printed wiring board 1, and a solder layer is formed on the surface of the lead pins 4.
次に、第１図（ｅ）、（ｆ）に示すように、治具を用い
てＰＧＡパッケージ６のパッド７の各々を相対するリー
ドピン４の先端にそれぞれ整合して接触させるようにＰ
ＧＡパッケージ６を載置し、リフロー半田付法、蒸気相
半田付は法あるいはベルト炉による加熱等によりパッド
７とリードピン４を接合する。Next, as shown in FIGS. 1(e) and 1(f), a jig is used to align and contact each pad 7 of the PGA package 6 with the tip of the opposing lead pin 4.
The GA package 6 is mounted, and the pads 7 and lead pins 4 are joined by reflow soldering, vapor phase soldering, heating in a belt furnace, or the like.
第２図（ａ）〜（ｄ）は本発明の第２の実施例を説明す
るための工程順に示した平面図及び一部切欠側面図であ
る。FIGS. 2(a) to 2(d) are a plan view and a partially cutaway side view showing a second embodiment of the present invention in order of steps.
第２図（ａ）、（ｂ）に示すように、第１の実施例と同
様にしてリードピン４を植込んだ印刷配線板１を準備し
、印刷配線板１に設けたり−ドビン４の配列に対応した
スルーホール８を底面に設は且つＰＧＡパッケージの位
置決めをするための側壁９を有する樹脂系のアダプタ１
０のスルーホール８を対応するリードピン４に挿入して
印刷配線板１の上に装着し、接着剤１１により固定する
。As shown in FIGS. 2(a) and 2(b), a printed wiring board 1 having lead pins 4 implanted therein is prepared in the same manner as in the first embodiment, and the lead pins 4 are arranged on the printed wiring board 1. A resin-based adapter 1 having a through hole 8 corresponding to the PGA package on the bottom and a side wall 9 for positioning the PGA package.
The through holes 8 of 0 are inserted into the corresponding lead pins 4, mounted on the printed wiring board 1, and fixed with adhesive 11.
次に、第２図（Ｃ）、（ｄ）に示すように、ＰＧＡパッ
ケージを側壁９に添わせて前記アダプタ内に挿入しＰＧ
Ａパッケージのパッド７とり−Ｈビン４の先端を突き合
わせる０次に、リフロー半田付は法により、パッド７と
リードピン４を半田付けする。Next, as shown in FIGS. 2(C) and 2(d), insert the PGA package into the adapter along the side wall 9, and insert the PGA package into the adapter.
The pad 7 of the A package and the tip of the H bottle 4 are brought together. Next, the pad 7 and the lead pin 4 are soldered using reflow soldering.
第３図（ａ）、（ｂ）は本発明の第３の実施例を説明す
るための工程順に示した平面図及び一部切欠断面図であ
る。FIGS. 3(a) and 3(b) are a plan view and a partially cutaway sectional view showing the process order for explaining a third embodiment of the present invention.
第３図（ａ）、（ｂ）に示すように、第２の実施例のア
ダプタを分割してＰＧＡパッケージの対向する２辺に設
けた以外は第２の実施例と同じ構成を有している。As shown in FIGS. 3(a) and 3(b), it has the same configuration as the second embodiment except that the adapter of the second embodiment is divided and provided on two opposing sides of the PGA package. There is.
なお、アダプタは樹脂の代りにアルミニウムを加工した
後表面を陽極酸化したものを使用しても良く熱放散のす
ぐれたヒートシンクとすることができる。Note that instead of resin, the adapter may be made of aluminum processed and then anodized on the surface, resulting in a heat sink with excellent heat dissipation.
以上説明したように本発明は、ＰＧＡパッケージにリー
ドピンをろう付けしないリードレスチップキャリアー（
ＬＣＣ）であるからパッケージコストがリード付ＰＧＡ
パッケージよりも安く、パッケージメーカー ＬＳＩチ
ップの組立工程、その他の工程によるハンドリングでリ
ード曲がりの発生がなく、組立工程の制約も少なくなる
。As explained above, the present invention provides a leadless chip carrier (
Since it is LCC), the package cost is lower than that of PGA with leads.
It is cheaper than a package, and there is no bending of leads during handling during the package manufacturer's LSI chip assembly process or other processes, and there are fewer restrictions on the assembly process.
更に、プリント板に実装する時は、リードピン曲がりが
なく、位置決め用アダプタを使用する方法においては、
位置すれかなく良好な半田接続が得られる。Furthermore, when mounting on a printed board, there is no bending of the lead pins, and in the method of using a positioning adapter,
A good solder connection can be obtained with only a few positions.
又、位置決め用アダプタにアルミニウムを陽極酸化処理
を施したものを使用することによりパッケージ裏面から
の放熱効果を高める効果がある。Furthermore, by using anodized aluminum for the positioning adapter, there is an effect of increasing the heat dissipation effect from the back surface of the package.
第１図（ａ ） 〜（ｆ ）及び第２図（ａ）〜（ｄ）
並びに第３図（ａ）、（ｂ）は本発明の第１乃至第３の
実施例を説明するための工程順に示した平面図及び一部
切欠側面図、第４図（ａ）、（ｂ）はＰＧＡパッケージ
型半導体装置の一例を示す底面図及び側面図、第５図（
ａ）〜（ｃ）及び第６図（ａ）〜（ｃ）は従来の半導体
装置の実装方法の第１及び第２の例を説明するためのＰ
ＧＡパッケージの側面図及び印刷配線板の一部切欠側面
図である。
１・・・印刷配線板、２・・・スルーホール、３・・・
スルーホールピッチ、４・・・リードピン、５・・・Ｐ
ｂ−５ｎ共晶半田、６・・・ＰＧＡパッケージ、７・・
・パッド、８・・・スルーホール、９・・・側壁、１ｏ
・・・アダプタ、１・・・接着剤、
２・・・リードピン、
３・・・＾ｇ−Ｃｕ
ろう材、
４・・・接続用ランド。Figure 1 (a) to (f) and Figure 2 (a) to (d)
FIGS. 3(a) and 3(b) are plan views and partially cutaway side views showing the steps of the first to third embodiments of the present invention, and FIGS. 4(a) and 4(b) are ) is a bottom view and side view showing an example of a PGA package type semiconductor device, and FIG.
a) to (c) and FIGS. 6(a) to (c) are P for explaining the first and second examples of the conventional semiconductor device mounting method.
They are a side view of a GA package and a partially cutaway side view of a printed wiring board. 1...Printed wiring board, 2...Through hole, 3...
Through hole pitch, 4...Lead pin, 5...P
b-5n eutectic solder, 6...PGA package, 7...
・Pad, 8...Through hole, 9...Side wall, 1o
...Adapter, 1...Adhesive, 2...Lead pin, 3...^g-Cu brazing material, 4...Connection land.
Claims (1)
の実装方法において、前記半導体装置のパッドの配置に
対応して印刷配線板に設けたスルーホールにリードピン
を挿入して半田付けし、前記リードピンの先端に対応す
る前記パッドのそれぞれを突き合わせて位置決めし、前
記リードピンの先端と前記パッドを半田付けして前記半
導体装置と前記印刷配線板を電気的に接続する手段を含
むことを特徴とする半導体装置の実装方法。In a pad grid array package type semiconductor device mounting method, lead pins are inserted into through holes provided in a printed wiring board corresponding to the arrangement of pads of the semiconductor device and soldered to the tips of the lead pins. Mounting of a semiconductor device characterized by comprising means for positioning the corresponding pads against each other and soldering the tips of the lead pins and the pads to electrically connect the semiconductor device and the printed wiring board. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27646188A JPH02122556A (en) | 1988-10-31 | 1988-10-31 | Method of mounting semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27646188A JPH02122556A (en) | 1988-10-31 | 1988-10-31 | Method of mounting semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02122556A true JPH02122556A (en) | 1990-05-10 |
Family
ID=17569768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27646188A Pending JPH02122556A (en) | 1988-10-31 | 1988-10-31 | Method of mounting semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02122556A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5283489A (en) * | 1991-07-04 | 1994-02-01 | Mitsuba Electric Manufacturing Co. Ltd. | Structure for terminal section of motor |
| WO1999047903A1 (en) * | 1998-03-18 | 1999-09-23 | The Furukawa Electric Co., Ltd. | Image processor for observing optical fiber |
| JP2011082303A (en) * | 2009-10-06 | 2011-04-21 | Ibiden Co Ltd | Circuit board, and semiconductor module |
| CN108615716A (en) * | 2018-04-28 | 2018-10-02 | 上海移远通信技术股份有限公司 | Wireless communication module and wireless communication apparatus comprising it |
| US10354036B2 (en) * | 2015-07-15 | 2019-07-16 | Yamaha Hatsudoki Kabushiki Kaisha | Model data generation device, method of generating model data, mounting reference point determination device, and method of determining mounting reference point |
-
1988
- 1988-10-31 JP JP27646188A patent/JPH02122556A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5283489A (en) * | 1991-07-04 | 1994-02-01 | Mitsuba Electric Manufacturing Co. Ltd. | Structure for terminal section of motor |
| WO1999047903A1 (en) * | 1998-03-18 | 1999-09-23 | The Furukawa Electric Co., Ltd. | Image processor for observing optical fiber |
| JP2011082303A (en) * | 2009-10-06 | 2011-04-21 | Ibiden Co Ltd | Circuit board, and semiconductor module |
| US10354036B2 (en) * | 2015-07-15 | 2019-07-16 | Yamaha Hatsudoki Kabushiki Kaisha | Model data generation device, method of generating model data, mounting reference point determination device, and method of determining mounting reference point |
| CN108615716A (en) * | 2018-04-28 | 2018-10-02 | 上海移远通信技术股份有限公司 | Wireless communication module and wireless communication apparatus comprising it |
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