JPS5428582A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5428582A
JPS5428582A JP9435977A JP9435977A JPS5428582A JP S5428582 A JPS5428582 A JP S5428582A JP 9435977 A JP9435977 A JP 9435977A JP 9435977 A JP9435977 A JP 9435977A JP S5428582 A JPS5428582 A JP S5428582A
Authority
JP
Japan
Prior art keywords
semiconductor device
aboid
deterioration
bonding
material containing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9435977A
Other languages
Japanese (ja)
Inventor
Toshiyuki Fujii
Takashi Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9435977A priority Critical patent/JPS5428582A/en
Publication of JPS5428582A publication Critical patent/JPS5428582A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To aboid the deterioration of the dielectric strength by pressure-bonding the element and the solder material containing lead or tin via the Ni layer on the copper plate in order to form a laminated plate electrode.
COPYRIGHT: (C)1979,JPO&Japio
JP9435977A 1977-08-05 1977-08-05 Semiconductor device Pending JPS5428582A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9435977A JPS5428582A (en) 1977-08-05 1977-08-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9435977A JPS5428582A (en) 1977-08-05 1977-08-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5428582A true JPS5428582A (en) 1979-03-03

Family

ID=14108092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9435977A Pending JPS5428582A (en) 1977-08-05 1977-08-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5428582A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61266222A (en) * 1985-05-20 1986-11-25 Diafoil Co Ltd Extrusion molding and device therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61266222A (en) * 1985-05-20 1986-11-25 Diafoil Co Ltd Extrusion molding and device therefor

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