JPS5362471A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5362471A
JPS5362471A JP13813576A JP13813576A JPS5362471A JP S5362471 A JPS5362471 A JP S5362471A JP 13813576 A JP13813576 A JP 13813576A JP 13813576 A JP13813576 A JP 13813576A JP S5362471 A JPS5362471 A JP S5362471A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrode
positive
substrate
contact resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13813576A
Other languages
Japanese (ja)
Inventor
Kenzo Hatada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13813576A priority Critical patent/JPS5362471A/en
Publication of JPS5362471A publication Critical patent/JPS5362471A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Abstract

PURPOSE: To make connection easy and positive and perform connection of small contact resistance by forming recessed and raised bumps on the electrode of a substrate and external lead terminals.
COPYRIGHT: (C)1978,JPO&Japio
JP13813576A 1976-11-16 1976-11-16 Semiconductor device Pending JPS5362471A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13813576A JPS5362471A (en) 1976-11-16 1976-11-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13813576A JPS5362471A (en) 1976-11-16 1976-11-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5362471A true JPS5362471A (en) 1978-06-03

Family

ID=15214797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13813576A Pending JPS5362471A (en) 1976-11-16 1976-11-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5362471A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59136949A (en) * 1983-01-27 1984-08-06 Seiko Epson Corp Semiconductor integrated circuit
JPH03133137A (en) * 1989-10-19 1991-06-06 Ibiden Co Ltd Bump for electronic component mounting
US7129586B2 (en) 2003-06-27 2006-10-31 Denso Corporation Flip chip packaging structure and related packaging method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59136949A (en) * 1983-01-27 1984-08-06 Seiko Epson Corp Semiconductor integrated circuit
JPH03133137A (en) * 1989-10-19 1991-06-06 Ibiden Co Ltd Bump for electronic component mounting
US7129586B2 (en) 2003-06-27 2006-10-31 Denso Corporation Flip chip packaging structure and related packaging method

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