JPS62163347A - Substrate for mounting electronic part - Google Patents
Substrate for mounting electronic partInfo
- Publication number
- JPS62163347A JPS62163347A JP61004656A JP465686A JPS62163347A JP S62163347 A JPS62163347 A JP S62163347A JP 61004656 A JP61004656 A JP 61004656A JP 465686 A JP465686 A JP 465686A JP S62163347 A JPS62163347 A JP S62163347A
- Authority
- JP
- Japan
- Prior art keywords
- recess
- section
- electronic component
- protrusion
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は電子部品搭載用基板、特にその基材に電子部品
を塔・成するための凹部を有する電子部品搭成用基板に
関するものであり、ざらに詳細には、・：＋ｌ ’に度
実装が要求される半導体素子塔載用基板として１例えば
時計やカメラ等の内装基板あるいはチ、プキャＩＪア、
ピングリントアレイなどのパンケージ用基板に応用され
る−［子部品搭載用基板に関するものである。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a substrate for mounting electronic components, and particularly to a substrate for mounting electronic components having a concave portion in the base material for mounting electronic components. , Roughly in detail, as a board for mounting a semiconductor element that requires frequent mounting, for example, an interior board for a watch or camera, or a
It is applied to a pan cage board such as a pin print array - [Relates to a board for mounting child components.
（従来の技ｌよｔ）
近年、半導体素子等の電子部品を実装するに際し１回路
形成されるプリント配線板にキャビティすなわち凹部を
設け、この凹部内に」−記の電子部品を＋７ｉ１定実装
して用いることが多い。このように凹部を基板に形成す
るのは、回路の高富度化の飲請かある場合、部品実装の
高さが制限される場合、前密度薄型基板や極めて限定さ
れた部分に多数の接続導体を形成しなければならない場
合、４パ導体、に子を基板とともにパッケージ化しなけ
ればならない場合等、種々な場合に当該凹部を有効に利
用することができるからである。(Conventional technique) In recent years, when mounting electronic components such as semiconductor elements, a cavity or recess is provided in a printed wiring board on which one circuit is formed, and electronic components of ``-'' are mounted at a constant rate of +7i1 within this recess. It is often used. Forming recesses in this way on a board is recommended when there is a need to increase the density of circuits, when the height of component mounting is limited, when there is a high density thin board, or when there are many connection conductors in extremely limited areas. This is because the recessed portion can be effectively used in various cases, such as when a 4-pass conductor or connector must be packaged together with a board.
ところで、このよう公都合のよい凹部ではあるが、従来
のこの種凹部にあっては、その形成がザグリ加工による
ミーリング加圧することと、その後の各種処理を残すこ
と等によって、ち該凹部の断面形状が通常第６図及び第
７図に示したようになっている。なお、ここでいう各種
の処理とは、凹部形成後の基板に回路を形成するための
メンキや溶剤洗浄等の種々な液処理等、さらにその後の
種々な熱処理がある。By the way, although such a concave portion is convenient, conventional concave portions of this type are formed by milling and pressurizing by counterboring, and by leaving various subsequent treatments, etc., and the cross section of the concave portion is The shape is usually as shown in FIGS. 6 and 7. The various treatments mentioned here include various liquid treatments such as coating and solvent cleaning for forming circuits on the substrate after the recesses are formed, and various subsequent heat treatments.
第６図に示したような状態の凹部（３０）は、ザグリ加
工後にうおけるメンキ工程等の液処理がなされたもので
あって、凹部（３０）の開口縁（３１）から垂直に下し
た而（３３）と底面（３２）とが直角に交差しているの
である。これに対して、第７図に示した状態の凹部（３
０）にあっては、ザグリ加工後メッキ工程等による液処
理、多層構造とするための熱処理等の工程が付加された
後の状ｙＥのものを示しており、この凹部（３０）にあ
っては、各種の処理によって基板を構成している基材自
体の膨潤または熱収縮による大村内部の応力差によって
、凹部（３０）の開０縁（３１）から底面（３２）に至
る側面（３４）と底面（３２）とが鋭角で交差している
のである。The recess (30) in the state shown in Fig. 6 has been subjected to a liquid treatment such as a spacing process after counterbore processing, and is vertically lowered from the opening edge (31) of the recess (30). However, (33) and the bottom surface (32) intersect at right angles. On the other hand, the recess (3) in the state shown in FIG.
0) shows the state yE after counterbore processing, liquid treatment by plating process, heat treatment to form a multilayer structure, etc. The side surface (34) from the open edge (31) of the recess (30) to the bottom surface (32) is caused by the stress difference inside Omura due to the swelling or thermal contraction of the base material itself that constitutes the substrate through various treatments. and the bottom surface (32) intersect at an acute angle.
いずれにしても、従来の基板に形成された凹部の断面形
状が上述のような形状、すなわち、凹部（３０）の開口
縁（３１）から垂直に下した而（３３）と底面（３２）
とが直角に交差しているか、あるいは凹部（３０）の開
口縁（３１）から底面（３２）に至る側面（３４）と底
面（３２）とが鋭角で交差していると、次のような諸問
題が発生する可能性が高い。つまり、凹部（３０）にお
いて上述したような形状になっていると、その底面（３
２）と昨直に下した面（３３）や底面（３２）に至る側
面（３４）との交差部分において内部応力が来由し易く
、この交Ｘ’Ｘ部分を起点とするワレや亀裂か５該プリ
ント配線基板の大村内部に発生し易くなるのである。In any case, the cross-sectional shape of the recess formed in the conventional substrate is the shape described above, that is, the recess (30) is vertically lowered from the opening edge (31) of the recess (33) and the bottom surface (32).
If they intersect at a right angle, or if the side surface (34) from the opening edge (31) of the recess (30) to the bottom surface (32) intersects at an acute angle, the following There is a high possibility that various problems will occur. In other words, if the recess (30) has the shape described above, the bottom surface (30)
Internal stress is likely to occur at the intersection between 2) and the side (34) leading to the surface (33) and bottom surface (32) that was just lowered, and cracks or cracks may occur starting from this intersection X'X. 5. It is easy for the problem to occur inside the printed wiring board.
問題はこれだけではない。つまり、この凹部（３０）に
金属被膜からなる導体層を別途形成しようとする場合に
は、この導体層の形成はメッキによって行なわれること
が多いから、このようなメッキ作業において凹部（３０
）の底面（３２）部分に断面形状が直角あるいは鋭角の
交差部分があれば、この部分にメッキ液やメンキ前処理
液が残留し易くなる。それだけではなく、この交差部分
においては、メッキの電流密度が低くなることから、形
成されたメ・、キ層は部分的に薄くなるのである。従っ
て、このように形成されたメッキ層は、当該凹部（３０
）との密着性に劣ってメ・ンキ層自身の強度が弱くなり
、メッキにより形成されるへき導体層が基材から剥離し
たり、破断したりしてしまうという問題が発生し得るの
である。This is not the only problem. In other words, if a conductor layer made of a metal film is to be separately formed in the recess (30), this conductor layer is often formed by plating, so the recess (30) is
) If there is an intersection with a right-angled or acute-angled cross section on the bottom surface (32), the plating solution or coating pretreatment solution tends to remain in this section. Not only that, but because the plating current density is lower at this intersection, the formed metal layer becomes partially thinner. Therefore, the plating layer formed in this way is
), the strength of the coating layer itself is weakened, and problems may arise in which the conductor layer formed by plating peels off from the base material or breaks.
（発明が解決しようとする問題点）
本発明は以上のような実状に鑑みてなされたもので、そ
の解決しようとする問題点は、従来のプリント配線基板
において発生、していた、その凹部近傍におけるワレや
亀裂であり、さらには従来のプリント配線基板において
形成されている導体層の密着性及び強度が劣ることであ
る。(Problems to be Solved by the Invention) The present invention has been made in view of the above-mentioned circumstances, and the problems to be solved are the problems that occur in the vicinity of the recesses that occur in conventional printed wiring boards. Furthermore, the adhesion and strength of the conductive layer formed in conventional printed wiring boards are poor.
そして、本発明の目的とするところは、この種のプリン
ト配線板の凹部内における断面形状を積極的に変更する
ことによって、凹部近傍においてワレや亀裂が生じない
ことは勿論のこと、凹部の内面に形成した導体層が容易
に剥離等の現象を生しないようにすることができる電子
部品搭載用基板を簡単な構成によって提供することにあ
る。The purpose of the present invention is to actively change the cross-sectional shape of the recess in this type of printed wiring board, so that not only cracks and cracks do not occur in the vicinity of the recess, but also the inner surface of the recess. It is an object of the present invention to provide a substrate for mounting electronic components with a simple structure, which can prevent a conductor layer formed on the substrate from easily peeling off or other phenomena.
（問題点を解決するための手段）
以上の問題点を解決するために本発明が採った手段は、
実施例に対応する第１図〜第５図を参照して説明すると
、
電子部品（１４）を搭載するための凹部（１２）を有す
る電子部品搭載用基板において。(Means for solving the problems) The means taken by the present invention to solve the above problems are as follows:
An explanation will be given with reference to FIGS. 1 to 5, which correspond to embodiments: An electronic component mounting board having a recess (12) for mounting an electronic component (14).
前記凹部（１２）の底面（１３）周辺に、凹部（１２）
の開口縁（１２ａ）より垂直に下した面（２１）と、前
記門、七Ｉｔ（１２）の底面（１３）の延長面（２２）
との交差部分（２３）から、前記凹部（１２）の中央部
方向に向けて出る突出部（２０）を形成したことを特徴
とする゛電子部品搭載用基板（１１）
である。A recess (12) is formed around the bottom surface (13) of the recess (12).
A surface (21) perpendicularly lower than the opening edge (12a) of the gate, and an extension surface (22) of the bottom surface (13) of the gate, 7It (12).
This electronic component mounting board (11) is characterized in that a protrusion (20) is formed extending toward the center of the recess (12) from the intersection (23) with the recess (12).
つまり、電子部品搭載用基板（１１）の凹部（１２）近
傍に突出部（２０）を積極的に形成することによって、
凹部（１２）の開口縁（１２ａ）から屯直に下した面（
２１）と底面（１３）の延長面（２２）との交差部分（
２３）において凹部（１２）の断面形状が直角あるいは
鋭角にはならないようにしたのである。That is, by actively forming the protrusion (20) near the recess (12) of the electronic component mounting board (11),
The surface directly down from the opening edge (12a) of the recess (12) (
21) and the extension surface (22) of the bottom surface (13) (
In 23), the cross-sectional shape of the recess (12) is not a right angle or an acute angle.
（発明の作用）
本発明は以上のような手段を採ることによって以下のよ
うな作用がある。すなわち、゛電子部品搭載用基板（１
１）の凹部（１２）近傍において突出部（２０）を設け
ることにより、当該凹部（１２）の断面形状が直角ある
いは鋭角にはならないようにしたのであるから、この突
出部（２０）によって゛ｉｆｆ子部品子部品用５佐用基
板）の凹部（１２）近傍においての補強がなされたこと
になるのである。従って、電子部品搭載用基板（１１）
の凹部（１２）近傍においての各面の交差部分（２３）
に例え応力が集中したとしても、この応力は言わば分散
されることになるのである。(Actions of the Invention) By adopting the above-described measures, the present invention has the following effects. In other words, ``Substrate for mounting electronic components (1
By providing the protrusion (20) near the recess (12) in 1), the cross-sectional shape of the recess (12) is prevented from being a right angle or an acute angle. This means that the vicinity of the concave portion (12) of the IF component (substrate for component parts) has been reinforced. Therefore, the electronic component mounting board (11)
Intersection portion (23) of each surface near the concave portion (12) of
Even if stress is concentrated, this stress will be dispersed, so to speak.
また、電子部品搭載用基板（１１）の凹部（１２）近傍
においての各面の交差部分（２３）に突出部（２０）が
存在することによって、当該交差部分（２３）の近傍部
分にメッキ液やメッキ前処理液が残留することかなくな
るのであり、また交差部分（２３）の近傍部分における
メッキの電１ｉ、密度が低くなることはなく、所定厚さ
のメッキ層を形成することが可能となっているのである
。Furthermore, since the protrusion (20) is present at the intersection (23) of each surface near the recess (12) of the electronic component mounting board (11), the plating solution is deposited in the vicinity of the intersection (23). Therefore, there is no residual plating pretreatment solution, and the plating density in the vicinity of the intersection (23) does not decrease, making it possible to form a plating layer of a predetermined thickness. It has become.
（実施例）
次に、上記のような本発明の構成を１図面に示した具体
例に従ってより詳細に説明する。(Example) Next, the configuration of the present invention as described above will be explained in more detail according to a specific example shown in one drawing.
第１図には、本発明に係る電子部品搭載用基板（１１）
を採用して形成した電子部品搭載用ピングリッドアレイ
（ＩＯＡ）の縦断面図が示してあり、この電子部品搭載
用基板（１１）の凹部（１２）内には、第２図及び第３
図に示したように、電子部品搭載用基板（１１）と一体
的な突出部（２ｏ）が凹ＦＩＢ （＋２）の中心部分に
向けて出されているのである。FIG. 1 shows an electronic component mounting board (11) according to the present invention.
A vertical cross-sectional view of a pin grid array (IOA) for mounting electronic components formed by adopting the above method is shown.
As shown in the figure, a protrusion (2o) integral with the electronic component mounting board (11) is projected toward the center of the concave FIB (+2).
なお、この電子部品搭載用ビングリ、ドアレイ（ＩＯＡ
）にあっては、その電子部品搭載用基板（１１）の凹部
（１２）内に半導体素子（１４）を固定支持した後、こ
の半導体素子（１４）と゛電子部開基・成用基板（１１
）上に形成した導体回路とをポンディングワイヤ（１４
ａ）によってそれぞれ接続して、当該半導体素−／−（
１４）の上部を電子部品搭載用基板（１１）に接着した
メタルキャップ（１５）によって４ｎ ２７したもので
ある。また、この電子部品搭載用ビングリ、ドアレイ（
ＩＯＡ）にあっては、その′電子部品搭載用基板（１１
）に形成した各スルーホール内に導体ピン（１Ｂ）のＬ
Ａ部を強制嵌合することによって、その名の通りのピン
グリッドアレイとしたものである。In addition, this Bingley for mounting electronic components, door array (IOA)
), after the semiconductor element (14) is fixedly supported in the recess (12) of the electronic component mounting board (11), the semiconductor element (14) and the electronic part opening/production board (11) are fixedly supported.
) and the conductor circuit formed on the bonding wire (14
a), and the semiconductor element −/−(
14) is covered with a metal cap (15) bonded to the electronic component mounting board (11). In addition, this Bingley for mounting electronic components, door array (
IOA), its electronic component mounting board (11
) into each through-hole formed in the conductor pin (1B).
By forcibly fitting the A part, it is a pin grid array as the name suggests.
この電子部品搭載用ピンクリントアレイ（ＩＯＡ）を構
成している電子部品搭載用基板（＋１）に形成した突出
部（２０）は、当、咳′ＩＶ子部品搭載用基板（１１）
に対して次のような関係にしである。すなわち、第２図
及び第３図に示したように、凹部（１２）の底面（１３
）周辺に、凹部（１２）の開口縁（１２ａ）より垂直に
ドした而（２１）と、凹部（１２）の底面（１３）の延
長面（２２）との交差部分（２３）から、凹部（１２）
の中央部方向に向けて出される突出部（２０）を形成し
たのである。この関係をより詳細に図示したのが第５図
である。The protrusion (20) formed on the electronic component mounting board (+1) constituting this electronic component mounting pin array (IOA) is connected to the IV child component mounting board (11).
The relationship is as follows. That is, as shown in FIGS. 2 and 3, the bottom surface (13) of the recess (12)
) around the opening edge (12a) of the recess (12), from the intersection (23) of the extension surface (22) of the bottom surface (13) of the recess (12), (12)
A protrusion (20) is formed that extends toward the center of the tube. FIG. 5 illustrates this relationship in more detail.
この第５図から明らかなように、凹部（１２）の開［］
縁（＋２８）から垂直に下した面（２１）と、底面（１
３）の延長面（２２）との交差部分（２３）を中心に見
ると、突出部（２０）は少なくとも凹部（１２）の中央
部方向に向けて出されていることになるのである。これ
によって、当該凹部（１２）の底面（１３）近傍におい
ては直角部分あるいは鋭角部分が全く存在しないのであ
る。As is clear from FIG. 5, the opening of the recess (12) []
The vertical surface (21) from the edge (+28) and the bottom surface (1
When looking at the intersection (23) with the extended surface (22) of 3), the protrusion (20) is projected at least toward the center of the recess (12). As a result, there is no right angle portion or acute angle portion near the bottom surface (13) of the recess (12).
この突出部（２０）は、以上のように凹部（１２）の底
面（１３）近傍において直角部分あるいは鋭角部分のイ
ｆ在を無くすためのものであるから、この条件を満たす
ような形状のものであればそれで十分であり、その形状
は次のように種々考えることができる。まず、この突出
部（２０）の形状は基本的には。Since this protrusion (20) is intended to eliminate the presence of a right-angled or acute-angled portion near the bottom surface (13) of the recess (12) as described above, it has a shape that satisfies this condition. If so, that is sufficient, and its shape can be considered in various ways as follows. First, the shape of this protrusion (20) is basically as follows.
当１核突出部（２０）の凹部（１２）内に露出する面が
、凹部（＋２）（７）開口縁（１２ａ）と凹部（１２）
ノ底面（１３）の外周縁とを連結する面に対して凹部（
１２）の中央部方向と反対側に位置すればよい、突出部
（２ｏ）の凹部（１２）内に露出する面が凹部（１２）
の開口縁（１２ａ）と凹部（１２）の底面（１３）の外
周縁とを連結する面よりも凹部（１２）の中央部方向に
位置していると。The surface exposed in the recess (12) of the first nuclear protrusion (20) is connected to the recess (+2) (7) opening edge (12a) and the recess (12).
A recess (
The surface exposed in the recess (12) of the protrusion (2o) should be located on the opposite side to the central part of the recess (12).
and the opening edge (12a) of the recess (12) and the outer peripheral edge of the bottom surface (13) of the recess (12).
当該突出部（２０）が凹部（１２）内に突出することに
なり、このように形成することは困難であるだけでなく
、例えば凹部（１２）内にメッキ層を形成した場合に、
このメッキ層の強度が弱くなるからである。このような
条件を満足するためには、第２図及び第５図の図示左半
分において示したように、突出部（２０）の凹部（１２
）内に露出する°面を平面として形成してもよく、また
第３図及び第５図の図示右半分にて示したように、凹部
（１２）の中央部に向けて凹となる球面として形成して
もよいのである。The protrusion (20) will protrude into the recess (12), and it is not only difficult to form it in this way, but also, for example, when a plating layer is formed inside the recess (12),
This is because the strength of this plating layer becomes weaker. In order to satisfy such conditions, as shown in the left half of FIG. 2 and FIG.
) may be formed as a flat surface, or as a spherical surface that becomes concave toward the center of the recess (12), as shown in the right half of FIGS. 3 and 5. It may be formed.
以上のような条件の突出部（２０）を形成するには、突
出部（２０）の凹部（１２）内に露出する面に対応する
切削面を有する回転刃（バイト）によってザグリ加工す
るのが最も効率が良い。このザグリ加工をするためにも
、電子部品搭載用基板（１１）の材質としては樹脂系素
材を使用するのがよく、本実施例にあっては、この電子
部品搭載用基板（１１）の基材としてガラスエポキシ樹
脂、ガラスポリイミド樹脂、カラストリアジン樹脂から
なる基材を使用した。In order to form the protrusion (20) under the above conditions, it is recommended to perform counterboring using a rotary blade (bit) having a cutting surface corresponding to the surface exposed in the recess (12) of the protrusion (20). Most efficient. In order to perform this counterboring process, it is preferable to use a resin material as the material for the electronic component mounting board (11), and in this embodiment, the base material for the electronic component mounting board (11) is A base material made of glass epoxy resin, glass polyimide resin, and calastriazine resin was used as the material.
また、第１図に示した′電子部品搭載用基板（１１）に
おける突出部（２０）にあっては、その凹部（１２）内
に露出する面が、凹部（１２）の他の面とともに金属メ
ッキ被膜で覆っである。このようにするのは、凹部（１
２）に金属被膜を設けることにより大村内部を通じての
湿気の侵入を防止して封止信頼性を向上させるとともに
、金属被膜自身を設置導体用の導体回路として採用し、
また該被膜を外部リードと接続させるように設計配線し
て半導体素子より発生する熱を前記被膜により速やかに
外部へ放散させる効果を持たせるためである。In addition, in the protrusion (20) of the electronic component mounting board (11) shown in FIG. It is covered with a plating film. To do this, the recess (1
2) By providing a metal coating, we prevent moisture from entering through the inside of the Omura and improve sealing reliability, and the metal coating itself is used as a conductor circuit for the installed conductor.
Further, by designing and wiring the film so as to connect it to an external lead, the film has the effect of quickly dissipating heat generated from the semiconductor element to the outside.
第４図は、第１図に示した′重子部品搭載用ビングリッ
ドアレイ（ＩＯＡ）とはタイプのツなるチップキャリア
パッケージ（ＩＯＢ）に１本発明を実施した状態を示す
縦断面図である。このチップキャリアパッケージ（ＩＯ
Ｂ）においても、凹部（１２）の底面（１３）周辺に、
凹部（１２）の開口縁（＋２ａ）より昨直に下した面（
２１）と、凹部（１２）の底面（１３）の延長面（２２
）との交差部分（２３）から、凹部（１２）の中央部方
向に向けて出される突出部（２０）が形成しであるので
ある。なお、このチップキャリアパッケージ（ＩＯＢ）
においては、凹部（１２）内に載置固定した半導体素子
（１４）の周囲に封止樹脂（１７）を滴下して、この封
止樹脂（１７）が周囲に流れ出ないようにするために、
電子部品搭載用基板（１１）の上面に樹脂封止枠（１８
）が固定しである。FIG. 4 is a longitudinal cross-sectional view showing a state in which the present invention is implemented in a chip carrier package (IOB), which is of a type different from the bin grid array (IOA) shown in FIG. This chip carrier package (IO
Also in B), around the bottom surface (13) of the recess (12),
The surface directly below the opening edge (+2a) of the recess (12) (
21) and an extension surface (22) of the bottom surface (13) of the recess (12).
) A protrusion (20) is formed that extends toward the center of the recess (12) from the intersection (23) with the recess (12). Furthermore, this chip carrier package (IOB)
In order to prevent the sealing resin (17) from flowing out to the surroundings by dropping the sealing resin (17) around the semiconductor element (14) placed and fixed in the recess (12),
The resin sealing frame (18) is placed on the top surface of the electronic component mounting board (11).
) is fixed.
（発明の効果）
以上詳述したように、本発明にあっては、上記の各実施
例にて例示した如く、
電子部品（１４）を搭載するための凹部（１２）を有す
る電子部品搭載用基板において、
凹部（１２）の底面（１３）周辺に、凹部（１２）の開
口縁（＋２ａ）より垂直に下した面（２１）と、凹部（
１２）の底面（１３）の延長面（２２）との交差部分（
２３）から、凹部（１２）の中央部方向に向けて出る突
出部（２０）を形成したこと
にその特徴があり、これにより、凹部（１２）近傍にお
いてワレや亀裂が生じないことは勿論のこと。(Effects of the Invention) As detailed above, the present invention provides an electronic component mounting device having a recess (12) for mounting an electronic component (14), as exemplified in each of the above embodiments. In the substrate, around the bottom surface (13) of the recess (12), there is a surface (21) perpendicularly lower than the opening edge (+2a) of the recess (12), and a surface (21) that is vertically downward from the opening edge (+2a) of the recess (12).
12) at the intersection of the bottom surface (13) with the extension surface (22) (
23), its feature lies in the formation of the protrusion (20) that protrudes toward the center of the recess (12), which naturally prevents cracks and cracks from occurring near the recess (12). thing.
凹部（１２）の内面に形成した導体層が容易に剥敲等の
現象を生じないようにすることができる電子部品搭載用
基板を簡単な構成によって提供することができるのであ
り、半導体素子が実装されたパッケージとしても高い信
頼性をさらに追求することのできる基板として極めて有
利なのである。It is possible to provide a substrate for mounting electronic components with a simple structure, which can prevent the conductive layer formed on the inner surface of the recess (12) from easily peeling off, etc., so that semiconductor elements can be mounted. It is extremely advantageous as a substrate that can further pursue high reliability even as a package.
第１図は本発明を実施した′市子部品塔・成用ピングリ
ッドアレイの縦断面図、第２図は本発明に係る電子部品
搭載用基板を示す縦断面図、第３図は第２図の他の実施
例を示す縦断面図、第４図は本発明を実施したチップキ
ャリアパッケージの縦断面図、第５図は突出部の各個を
示すための第２図の要部拡大縦断面図、第６図及び第７
図は従来の電子部品搭載用基板を示す縦断面図である。
（以下余白）
符 号 の 説 明
１０Ａ・・・電子部品搭載用ピングリッドアレイ。
１０Ｂ・・・チップキャリアパフケージ、 １１・・・
電子部品搭載用基板、１２・・・凹部、１２ａ・・・開
口縁、１３・・・底面１４・・・半導体素子、２０・・
・突出部、２１・・・垂直に下した面、２２・・・底面
の延長面、２３・・・交差部分。FIG. 1 is a vertical cross-sectional view of a pin grid array for IC parts tower/composition according to the present invention, FIG. 2 is a vertical cross-sectional view showing a board for mounting electronic components according to the present invention, and FIG. FIG. 4 is a vertical cross-sectional view of a chip carrier package embodying the present invention; FIG. 5 is an enlarged vertical cross-sectional view of the main part of FIG. 2 to show each of the protrusions. Figures 6 and 7
The figure is a vertical cross-sectional view showing a conventional electronic component mounting board. (Left below) Explanation of code 10A: Pin grid array for mounting electronic components. 10B...Chip carrier puff cage, 11...
Electronic component mounting board, 12... recess, 12a... opening edge, 13... bottom surface 14... semiconductor element, 20...
・Protrusion, 21... Vertically lowered surface, 22... Extended surface of bottom surface, 23... Intersecting part.
Claims (1)
搭載用基板において、 前記凹部の底面周辺に、前記凹部の開口縁より垂直に下
した面と、前記凹部の底面の延長面との交差部分から、
前記凹部の中央部方向に向けて出る突出部を形成したこ
とを特徴とする電子部品搭載用基板。 ２）、前記突出部の前記凹部内に露出する面が、前記開
口縁と前記凹部底面の外周縁とを連結する面に対して前
記凹部の中央部方向と反対側に位置するようにしたこと
を特徴とする特許請求の範囲第１項に記載の電子部品搭
載用基板。 ３）、前記突出部は、前記凹部をザグリ加工することに
より形成したことを特徴とする特許請求の範囲第１項ま
たは第２項に記載の電子部品搭載用基板。 ４）、前記突出部の前記凹部内に露出する面の形状は、
平面であることを特徴とする特許請求の範囲第１項〜第
３項のいずれかに記載の電子部品搭載用基板。 ５）、前記突出部の前記凹部内に露出する面の形状は、
前記凹部の中央部側の面が凹となる球面であることを特
徴とする特許請求の範囲第１項〜第３項のいずれかに記
載の電子部品搭載用基板。 ６）、前記突出部の前記凹部内に露出する面は、凹部の
他の面とともに金属メッキ被膜で覆われていることを特
徴とする特許請求の範囲第１項〜第５項のいずれかに記
載の電子部品搭載用基板。[Claims] 1) In an electronic component mounting board having a recess for mounting an electronic component, around the bottom of the recess, a surface perpendicularly lower than the opening edge of the recess, and a bottom surface of the recess. From the intersection with the extended plane of
A board for mounting an electronic component, characterized in that a protrusion is formed that projects toward the center of the recess. 2) The surface of the protrusion exposed in the recess is located on the opposite side of the direction toward the center of the recess with respect to the surface connecting the opening edge and the outer peripheral edge of the bottom surface of the recess. An electronic component mounting board according to claim 1, characterized in that: 3) The electronic component mounting board according to claim 1 or 2, wherein the protrusion is formed by counterboring the recess. 4) The shape of the surface of the protrusion exposed in the recess is:
The electronic component mounting board according to any one of claims 1 to 3, which is flat. 5) The shape of the surface of the protrusion exposed in the recess is:
The electronic component mounting board according to any one of claims 1 to 3, wherein a surface on the center side of the recess is a concave spherical surface. 6) According to any one of claims 1 to 5, the surface of the protrusion exposed in the recess is covered with a metal plating film along with other surfaces of the recess. Board for mounting electronic components as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61004656A JPH07120730B2 (en) | 1986-01-13 | 1986-01-13 | Resin board with electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61004656A JPH07120730B2 (en) | 1986-01-13 | 1986-01-13 | Resin board with electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62163347A true JPS62163347A (en) | 1987-07-20 |
| JPH07120730B2 JPH07120730B2 (en) | 1995-12-20 |
Family
ID=11589984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61004656A Expired - Lifetime JPH07120730B2 (en) | 1986-01-13 | 1986-01-13 | Resin board with electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07120730B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0359639U (en) * | 1989-10-13 | 1991-06-12 | ||
| US5986337A (en) * | 1997-11-17 | 1999-11-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor element module and semiconductor device which prevents short circuiting |
| JP2009105344A (en) * | 2007-10-25 | 2009-05-14 | Ngk Spark Plug Co Ltd | Wiring substrate with built-in plate-like component, and manufacturing method therefor |
| WO2009096563A1 (en) * | 2008-01-30 | 2009-08-06 | Kyocera Corporation | Elastic wave device and method for manufacturing the same |
| US7859172B2 (en) | 2007-06-19 | 2010-12-28 | Epson Toyocom Corporation | Piezoelectric resonator, manufacturing method thereof and lid for piezoelectric resonator |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW459275B (en) | 1999-07-06 | 2001-10-11 | Semiconductor Energy Lab | Semiconductor device and method of fabricating the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4947978A (en) * | 1972-09-08 | 1974-05-09 |
-
1986
- 1986-01-13 JP JP61004656A patent/JPH07120730B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4947978A (en) * | 1972-09-08 | 1974-05-09 |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0359639U (en) * | 1989-10-13 | 1991-06-12 | ||
| US5986337A (en) * | 1997-11-17 | 1999-11-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor element module and semiconductor device which prevents short circuiting |
| US7859172B2 (en) | 2007-06-19 | 2010-12-28 | Epson Toyocom Corporation | Piezoelectric resonator, manufacturing method thereof and lid for piezoelectric resonator |
| JP2009105344A (en) * | 2007-10-25 | 2009-05-14 | Ngk Spark Plug Co Ltd | Wiring substrate with built-in plate-like component, and manufacturing method therefor |
| WO2009096563A1 (en) * | 2008-01-30 | 2009-08-06 | Kyocera Corporation | Elastic wave device and method for manufacturing the same |
| JPWO2009096563A1 (en) * | 2008-01-30 | 2011-05-26 | 京セラ株式会社 | Elastic wave device and manufacturing method thereof |
| JP5090471B2 (en) * | 2008-01-30 | 2012-12-05 | 京セラ株式会社 | Elastic wave device |
| US8384272B2 (en) | 2008-01-30 | 2013-02-26 | Kyocera Corporation | Acoustic wave device and method for production of same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07120730B2 (en) | 1995-12-20 |
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