JP3728317B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device that is used as a thin semiconductor device such as a thin IC memory card module and has a semiconductor element mounted on a wiring board (Printed Wiring Board; hereinafter referred to as PWB) in a surface mount type and a manufacturing method thereof. is there.

JP-A-55-56647

Of semiconductor integrated circuits used for watches, cameras, IC cards, etc., an extremely thin package structure with a thickness of about 0.5 to 2 mm is required. A conventional semiconductor device mounts a semiconductor element at a predetermined position of a lead frame and performs resin sealing, or as shown in Patent Document 1, a semiconductor element such as a semiconductor integrated circuit is formed on PWB made of glass epoxy or the like. Is directly mounted, the semiconductor element is connected to the metal wiring on the PWB with a wire , and then sealed with an epoxy resin or the like. That is, in the above document, a chip-on-board package is shown.

  A pattern serving as an external terminal is formed on the surface of the PWB, and this pattern is connected to a bonding pattern formed on the back surface of the PWB through a through hole. The semiconductor element is fixed to the back surface of the PWB using an adhesive, and a pad formed on the lower surface of the semiconductor element, that is, the surface not in contact with the PWB, is connected to the PWB bonding pattern with a wire. After the pad of the semiconductor element is connected to the surrounding bonding pattern, the semiconductor element is encapsulated with resin to complete the semiconductor device.

However, the conventional semiconductor device has the following problems.
In a semiconductor device using a lead frame, the thickness and area of the entire semiconductor device are increased. Further, according to the method disclosed in Patent Document 1, since it is necessary to form a pattern on the front and back surfaces of the PWB on which the semiconductor element is mounted, a double-sided substrate having a structure in which copper foil is attached to the front and back surfaces must be used. It was necessary to form a predetermined number of through holes. Further, in order to make the mounting portion of the semiconductor element thinner, it is necessary to carry out spot facing on the PWB. That is, there are major problems in terms of processing and cost, and technically satisfactory products cannot be obtained.

  An object of the present invention is to provide a small-sized semiconductor device having a simplified structure using a single-sided substrate, a small thickness, and a manufacturing method thereof.

According to the present invention, in a semiconductor device, a PWB having a through hole penetrating a first surface on which a wiring pattern is formed and a second surface facing the first surface, and a part of the wiring pattern are insulatively coated. A solder resist, a semiconductor element disposed on the second surface of the PWB such that a pad provided on the main surface is exposed from the through-hole, the second surface of the PWB, and the semiconductor element A film-shaped adhesive provided between the main surface and fixing the semiconductor element to the PWB, and the pad of the semiconductor element and the wiring pattern of the PWB are electrically connected through the through hole. A wire , a sealing material filled in the through-hole, and a conductor provided on the first surface of the PWB and electrically connected to the wiring pattern, the tip of the conductor being the PWB of It is characterized in the higher than the upper surface of the sealing member the serial first surface as a reference.

In the present invention, on the back side (second surface) of the single-sided PWB in which the through hole is formed, a semiconductor element is mounted so that the pad is exposed from the through hole, and these are fixed with a film-shaped adhesive, A wiring pattern on the surface (first surface) of the PWB and a pad of a semiconductor element are electrically connected by a wire , and the through hole is filled with a sealing material to constitute a semiconductor device. Furthermore, a conductor for electrically connecting to the wiring pattern on the surface of the PWB is provided. Thereby, the structure is simplified using a single-sided substrate, and a thin semiconductor device with a small thickness can be obtained.

After covering a part of the wiring pattern on the front surface of the PWB with a solder resist, a semiconductor element is fixed to the back surface with a thin film adhesive, and a wire is passed between the pad of the semiconductor element and the wiring pattern of the PWB through a through hole. Connecting. Furthermore, the through hole is filled with an epoxy resin sealing material, and the solder resist covered with the wiring pattern is also covered with this sealing material. Then, a conductor for external connection is provided on the wiring pattern so that the tip is higher than the sealing material.

FIG. 1 is a cross-sectional view of the semiconductor device of Reference Example 1 .
In this semiconductor device, a single-sided substrate PWB 10 is used, and a wiring pattern 11 is formed on the surface which is the first surface of the PWB 10. A semiconductor element 20 is mounted on the back surface, which is the second surface of the PWB 10. A through hole 12 is provided in the center of the PWB 10, and the terminal of the semiconductor element 20 and the wiring pattern 11 are connected by a wire that is a conductive material passing through the through hole 12. And the surface of the 1st surface of the semiconductor element 20, the back surface of the 2nd surface, and the through-hole 12 are sealed with sealing resin 30, such as an epoxy which is a sealing material.

  2A to 2C are configuration diagrams of the semiconductor device of FIG. FIG. 1A is a top view of the PWB, FIG. 2B is a top view of the semiconductor element, and FIG. 3C shows an adhesive for fixing the semiconductor element to the PWB.

  The PWB 10 is configured by using a base material such as glass epoxy, and wiring patterns 11 serving as eight terminals are formed on the surface of the PWB 10. Further, a through hole 12 for exposing a terminal of the semiconductor element is provided in the central portion of the PWB 10, and two through holes 13 for resin circulation, which will be described later, are provided in the end portion. Each wiring pattern 11 is extended from the vicinity of the outer periphery of the through hole 12.

  Eight bonding pads 21 are formed at the center of the surface of the semiconductor element 20. In addition, the adhesive 22 for fixing the semiconductor element 20 to the PWB 10 is a thin film, and in order to fix the periphery of the upper surface of the semiconductor element 20 to the PWB 10, it is formed in a frame shape as shown in FIG. Has been.

Next, a procedure for manufacturing the semiconductor device of FIG. 1 will be described with reference to the drawings.
3 (1) and 3 (2) are diagrams showing a method (part 1) for manufacturing the semiconductor device of FIG. 1 (FIG. 2). FIG. 3 (1) is a top view and FIG. 3 (2) is a cross-sectional view. It is.

  First, the semiconductor element 20 is fixed to the back side of the PWB 10 using the adhesive 22. At this time, each pad 21 on the surface of the semiconductor element 20 is disposed so as to be exposed through the through-hole 12 when viewed from the surface side of the PWB 10, and as indicated by a broken line in FIG. The periphery of the upper part is bonded to the back surface of the PWB 10 with a frame-shaped adhesive 22. Subsequently, each pad 21 is connected to each pattern 11 by a wire 23 which is a conductive material. That is, each pad 21 on the back side of the PWB 10 is connected to the corresponding pattern 11 on the surface of the PWB 10 via eight wires 23 passing through the inside of the through hole 12 as shown in FIG.

  4 (1) to 4 (3) are diagrams showing a method (part 2) for manufacturing the semiconductor device of FIG. 1 (FIG. 2), in which FIG. 1 (1) is a top view and FIG. , And (3) is a back view.

  After each pad 21 and the pattern 11 on the surface of the PWB 10 are connected, sealing molding with a sealing resin 30 such as an epoxy resin is performed. The extending part of the wiring pad 11, the through hole 12, the wire 23, and the semiconductor element 20 are sealed by sealing molding. During the sealing molding, the sealing resin 30 injected from the surface side of the PWB 10 passes through the through hole 13. Therefore, the sealing resin 30 wraps around the back surface of the PWB 10, and the semiconductor element 20 is completely covered by one injection as shown in FIG. That is, on the surface side of the PWB 10, the through holes 12, 13, the wires 23, the pads 21, and the like are covered with the sealing resin 30, and on the back side of the PWB 10, the outside of the semiconductor element 20 is entirely covered with the sealing resin 30. .

As described above, in the first reference example, the semiconductor device is configured using the PWB 10 having the through hole 12, and the pad 21 and the wiring pattern 11 are connected via the through hole 12. Therefore, the single-sided substrate is connected to the PWB 10. Can be used. This facilitates pattern formation and eliminates the need for through-holes, thereby reducing the manufacturing cost of the PWB 10. Further, there is a follow-up ability to increase the element size accompanying an increase in the function of the semiconductor element 20 or to reduce the size accompanying an innovation in the formation technology of the semiconductor element 20, and various elements can be handled by a common PWB 10 structure. be able to. Further, since the PWB 10 itself can be formed thinly and with high accuracy, the thickness of the entire semiconductor device can be sufficiently reduced without requiring counter boring of a thick base material.

  The required area of the PWB 10 is substantially determined by the area of the region where the plurality of pads 21 are formed and the outer shape of the through hole 12. That is, since it is not necessary to take out the wire 23 from the outer shape of the semiconductor element 20 to the outside, for example, the area of the PWB 10 on which the wiring pattern 11 is formed can be made smaller than the area of the semiconductor element 20. The area of the entire semiconductor device is reduced.

5A to 5C are configuration diagrams of a semiconductor device showing Example 1 of the present invention. 1A is a top view of the PWB, FIG. 2B is a top view of the semiconductor element, and FIG. 3C shows an adhesive for fixing the semiconductor element to the PWB.

  The PWB 40 shown in FIG. 5A is configured using a base material such as glass epoxy, and a plurality of wiring patterns 41 are formed on the surface of the PWB 40. Each wiring pattern 41 constitutes a part of the terminal of the semiconductor device, and is formed so as to be arranged substantially evenly on both sides of the through hole 42. Further, an oval exposure through hole 42 is provided in the central portion of the PWB 40 so as to be vertically cut in a straight line. A bus bar 43 is formed between the wiring pattern 41 and the through hole 42. The bus bar 43 is covered with insulation by a solder resist (not shown).

  A plurality of bonding pads 51 are formed in one row at the center of the surface of the semiconductor element 50 of FIG. 5B mounted on the PWB 40. This structure is mainly used in large-capacity memory elements, and has a pad arrangement specification that conforms to a LOC (Lead on Chip) mounting structure. The adhesive 52 for fixing the semiconductor element 50 to the PWB 40 is a thin film, and is formed in a frame shape so that the upper periphery of the semiconductor element 50 can be fixed to the PWB 40.

  6 (1) to 6 (3) are diagrams showing a method of manufacturing the semiconductor device of FIG. 5, and a procedure for manufacturing the semiconductor device of FIG. 5 will be described with reference to FIG.

First, the semiconductor element 50 is fixed to the back side of the PWB 40 using the adhesive material 52. At this time, each pad 51 on the surface of the semiconductor element 50 is disposed so as to be exposed through the through hole 42 when viewed from the surface side of the PWB 40, and as shown by a broken line in FIG. The upper periphery is fixed to the back surface of PWB 40 with a frame-shaped adhesive 52.

  Subsequently, each pad 51 is connected to a plurality of wiring patterns 41 by wires 53. That is, as shown in FIG. 6A, each pad 51 on the back side of the PWB 40 is connected to each wiring pattern 41 via a plurality of wires 53 passing through the through holes 42. At this time, the bus bar crossing is performed, but since the bus bar 43 is covered with the solder resist, troubles such as a short circuit due to the drooping of the wire 53 are prevented.

Next, sealing molding with a sealing resin 60 such as epoxy is performed. During sealing molding with resin, the sealing resin 60 injected from the surface side of the PWB 40 covers the through holes 42, the wires 53, the pads 51, etc. on the surface side of the PWB 40 as shown in FIG. Is done. Subsequently, as shown in FIG. 6 (3), a conductor 61 such as a spherical solder that functions as a terminal for external connection has a tip that is higher than the upper surface of the sealing resin 60 with respect to the surface of the PWM 40. Temporarily fix to the pattern 41 with solder paste or the like so as to be higher. Thereby, the semiconductor device is completed.

FIG. 7 is a diagram showing a mounting form of the semiconductor device of FIG.
In the completed semiconductor device, the temporarily fixed side of the spherical conductor 61 is placed facing the other substrate 70, and this semiconductor device is mounted on the substrate 70 by a technique such as reflow mounting using solder paste. Implemented.

As described above, in the first embodiment, since the pad 51 and the pattern 41 are connected using the through hole 42, a semiconductor device having a pad arrangement conforming to the LOC mounting structure is formed using the lead frame. Compared to the case, the semiconductor device can be made much smaller and thinner. Here, if a semiconductor element whose surface is completely coated using means such as polyimide coating is used, a semiconductor element having a size equal to or larger than that of PWB 40 can be mounted. That is, a chip size or under chip size package is also possible.

  Moreover, since the bus bar 43 is covered with the solder resist, a short circuit trouble at the time of bonding across the bus bar is prevented. On the other hand, the degree of freedom of patterning in the PWB 40 is far greater than when a lead frame is used. That is, since the semiconductor device is connected to the substrate 70 using a plurality of conductors 61 independent of the bus bar 43 without using the lead frame, the bus bar is intentionally connected to the wire bond as in the case of the lead frame. It is no longer necessary to set near the wing point. Therefore, for example, the bus bar 43 can be set through the outside of the pattern 41. Therefore, it is not necessary to pay attention to loop control for the wiring route of the wire 53, which is advantageous in production.

  On the other hand, since the spherical conductor 61 is temporarily fixed on the pattern 41, it is mixedly mounted on the same substrate 70 together with a BGA (Ba11 Grid Array) which is a mounting form of a multi-pin LSI such as a CPU or a peripheral logic circuit. In this case, the solder reflow conditions can be matched.

FIG. 8 is a structural diagram of a semiconductor device showing Embodiment 2 of the present invention. Elements common to FIG. 5 are denoted by common reference numerals.

The PWB 80 used in the present embodiment is a PWB having the same configuration as the PWB 40 used in the first embodiment, and two new through holes 81 through which the sealing resin 60 flows are provided. 42 has the same configuration as the PWB 40. The semiconductor element 50 mounted on the PWB 80 has the same structure as that of the first embodiment.

In the case of manufacturing the semiconductor device of FIG. 8, as in the first embodiment, the semiconductor element 50 is fixed to a predetermined position on the back surface side of the PWB 80 with the adhesive 52 and exposed to the surface through the through hole 42 and the pattern. 41 is connected by a wire 53 passing through the through hole 42. After the pad 51 and the pattern 41 are connected, for example, resin sealing with the sealing resin 60 is performed from the surface side of the PWB 80. By the resin sealing, the front and back surfaces of the semiconductor element 50 are completely covered as shown in FIG.

  That is, at the time of resin sealing, the through-hole 42 allows the sealing resin 60 to flow. Therefore, the portion exposed by the through hole 42 as viewed from the surface of the PWB 80 of the semiconductor element 50 and the wire 53 are covered with the sealing resin 60A, and the portion exposed from the back surface of the PWB 80 of the semiconductor element 50 is Covered with sealing resin 60B.

As described above, in the second embodiment, the semiconductor device is configured by the PWB 80 provided with the through holes 42. Therefore, the exposed portion of the semiconductor element 50 can be covered all at once with the sealing resin 60, and the semiconductor device having the effect of the first embodiment can be given more reliable moisture resistance. it can.

FIG. 9 is a structural diagram of the semiconductor device of Reference Example 2. Elements common to those in FIG. 5 are denoted by common reference numerals.

When this semiconductor device is mounted on another substrate, a protrusion 62 for providing a predetermined clearance with this substrate is added to the semiconductor device of the first embodiment.

In this semiconductor device, a semiconductor element 50 is mounted on a PWB 40 similar to that in the first embodiment. A plurality of spherical conductors 61 are also temporarily fixed on the wiring pattern 41 as in the first embodiment. The portion exposed to the surface of the PWB 40 of the semiconductor element 50 and the wire 53 are sealed with a sealing resin 60 as shown in FIG. On the sealing resin 60, a protrusion 62 made of the same epoxy resin as the sealing resin 60 is provided. The manufacturing method of this semiconductor device is the same as that of the first embodiment, and the protrusions 62 are formed simultaneously with the resin sealing.

FIG. 10 is a diagram showing the semiconductor device of FIG. 9 mounted on another substrate.
When the semiconductor device is mounted on another substrate 70, the protrusion 62 serves as a support, and the distance between the semiconductor device and the substrate 70 becomes a desired value H.

As described above, since the protrusion 62 is provided in the reference example 2 , a desired clearance can be set between the sealing resin 60 and the substrate 70 of the semiconductor device. Therefore, the accuracy of the mounting dimensions is improved and a structure effective for performing flux cleaning after mounting and the like can be obtained.

The first and second embodiments described above are only for clarifying the technical contents of the present invention. The present invention is not limited to the first and second embodiments and is not construed in a narrow sense. Various modifications can be made within the scope of the claims of the present invention. Examples of such modifications include the following.

(1) Glass epoxy PW B4 0,80 in the above embodiment, although the Futomeju fat 6 0 is constituted by an epoxy resin, these materials are as long as it has excellent insulating properties and moisture resistance, It is also possible to configure with other materials.

(2) The conductor 61 may also be connected to the substrate 70. It is not limited to solder, and other alloys having excellent conductivity and workability can be used.

6 is a sectional view of a semiconductor device of Reference Example 1. FIG. It is a block diagram of the semiconductor device of FIG. FIG. 8 is a diagram showing a method (Part 1) of manufacturing the semiconductor device of FIG. FIG. 8 is a diagram showing a method (part 2) for manufacturing the semiconductor device of FIG. It is a block diagram of the semiconductor device which shows Example 1 of this invention. FIG. 6 is a diagram showing a method for manufacturing the semiconductor device of FIG. 5. It is a figure which shows the mounting form of the semiconductor device of FIG. It is a structural diagram of a semiconductor device showing Example 2 of the present invention. 10 is a structural diagram of a semiconductor device of Reference Example 2. FIG. It is a figure which shows the semiconductor device of FIG. 9 mounted in the other board | substrate.

Explanation of symbols

10, 40, 80 PWB
11, 41 Wiring pattern 12, 42 Through hole (for exposure)
13,81 Through hole (for resin distribution)
20, 50 Semiconductor element 21, 51 Pad 22, 52 Adhesive 23, 53 Wire 30, 60 Sealing resin 61 Conductor 62 Protrusion

Claims (19)

A printed wiring board formed with a through hole penetrating a first surface on which a wiring pattern is formed and a second surface facing the first surface;
A solder resist for insulatingly covering a part of the wiring pattern;
A semiconductor element disposed on the second surface of the printed wiring board such that a pad provided on a main surface is exposed from the through hole;
A film-shaped adhesive which is provided between the second surface of the printed wiring board and the main surface of the semiconductor element, and fixes the semiconductor element to the printed wiring board;
A wire that electrically connects the pad of the semiconductor element and the wiring pattern of the printed wiring board through the through hole;
A sealing material filled in the through hole;
A conductor provided on the first surface of the printed wiring board and electrically connected to the wiring pattern;
The semiconductor device according to claim 1, wherein a tip of the conductor is higher than an upper surface of the sealing material with respect to the first surface of the printed wiring board.   The semiconductor device according to claim 1, wherein the sealing material covers the solder resist.   The semiconductor device according to claim 2, wherein the sealing material is an epoxy resin.   The semiconductor device according to claim 1, wherein the pad is formed in a central portion of the main surface of the semiconductor element.   The semiconductor device according to claim 4, wherein the pad is disposed substantially parallel to one side of the printed wiring board.   6. The semiconductor device according to claim 5, wherein the pads are arranged in one row.   The semiconductor device according to claim 5, wherein the pads are arranged in at least two rows.   The semiconductor device according to claim 1, wherein the conductor is a terminal for connecting to an external device.   9. The semiconductor device according to claim 8, wherein the conductors are arranged in a row and symmetrically across the through hole.   The semiconductor device according to claim 9, wherein the conductor is made of solder and has a curved surface. The adhesive material is a semiconductor device according to claim 1, wherein the large frame shape der Rukoto than the outer periphery of the through hole. The encapsulant of claim 1 Symbol mounting semiconductor device, wherein the covering side surfaces of the semiconductor element. The encapsulant semiconductor device according to claim 1 Symbol mounting, characterized in that cover a back surface opposite to the main surface of the semiconductor element. 2. The semiconductor device according to claim 1 , wherein the printed wiring board has a second through hole that penetrates the first surface and the second surface thereof and does not allow the conductive material to pass therethrough . The semiconductor device according to claim 1 , wherein an edge of the printed wiring board that defines the through hole is located on an inner side than an edge that defines a side surface of the semiconductor element . Preparing a printed wiring board formed with a through hole penetrating a first surface on which a wiring pattern is formed and a second surface facing the first surface;
A step of insulatingly coating a part of the wiring pattern with a solder resist;
Preparing a semiconductor element having a pad on the main surface;
Preparing a film-shaped adhesive;
Fixing the semiconductor element on the second surface of the printed wiring board via the adhesive so that the pad of the semiconductor element is exposed from the through hole;
Electrically connecting the pads of the semiconductor element and the wiring pattern of the printed wiring board through wires through the through holes;
Filling the through hole with a sealing material;
The printed wiring board is electrically connected to the wiring pattern, and the tip of the printed wiring board is higher than an upper surface of the sealing material filling the through-hole with respect to the first surface of the printed wiring board. Providing a conductor on the first surface;
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 16, wherein the solder resist is covered with the sealing material . The method of manufacturing a semiconductor device according to claim 17 , wherein the sealing material covers the second surface of the printed wiring board and a side surface of the semiconductor element . The printed wiring board has a second through hole that passes through the first surface and the second surface and does not allow the conductive material to pass therethrough, and the sealing material passes through the second through hole and is formed on the semiconductor element. The method of manufacturing a semiconductor device according to claim 18, wherein the side surface is covered.

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