JPH07120730B2 - Resin board with electronic components - Google Patents

Resin board with electronic components

Info

Publication number
JPH07120730B2
JPH07120730B2 JP61004656A JP465686A JPH07120730B2 JP H07120730 B2 JPH07120730 B2 JP H07120730B2 JP 61004656 A JP61004656 A JP 61004656A JP 465686 A JP465686 A JP 465686A JP H07120730 B2 JPH07120730 B2 JP H07120730B2
Authority
JP
Japan
Prior art keywords
recess
electronic component
resin substrate
substrate
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61004656A
Other languages
Japanese (ja)
Other versions
JPS62163347A (en
Inventor
一 矢津
勝美 馬渕
Original Assignee
イビデン 株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by イビデン 株式会社 filed Critical イビデン 株式会社
Priority to JP61004656A priority Critical patent/JPH07120730B2/en
Publication of JPS62163347A publication Critical patent/JPS62163347A/en
Publication of JPH07120730B2 publication Critical patent/JPH07120730B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電子部品を搭載した樹脂基板に関し、時計、
カメラ等の内層基板、チップキャリア、ピングリッドア
レイ等に利用される。
The present invention relates to a resin substrate on which electronic parts are mounted, a timepiece,
It is used for inner layer substrates such as cameras, chip carriers, pin grid arrays, etc.

〔従来の技術〕[Conventional technology]

従来、半導体素子等の電子部品を実装するに際し、回路
形成されるプリント配線基板に凹部を設け、この凹部内
に上記半導体素子を固定実装して用いることが多い。こ
のように凹部を基板に形成するのは、回路の高密度化の
要請がある場合、部品実装の高さが制限される場合、高
密度薄型基板や極めて限定された部分に多数の接続導体
を形成しなければならない場合、半導体素子を基板とと
もにパッケージ化しなければならない場合等、種々な場
合に該凹部を有効に利用することができるからである。
Conventionally, when mounting an electronic component such as a semiconductor element, a printed wiring board on which a circuit is formed is often provided with a recess, and the semiconductor element is fixedly mounted in the recess for use. The formation of the recesses in the substrate as described above is performed in the case where there is a demand for high circuit density, when the height of component mounting is limited, and a large number of connection conductors are provided in a high-density thin substrate or a very limited portion. This is because the recess can be effectively used in various cases, such as when it has to be formed and when the semiconductor element has to be packaged together with the substrate.

しかし、この凹部にあっては、その形成がザグリ加工
(回転しているバイト等のその回転軸に直交する方向に
移動させることにより行う切削加工)によりミーリング
加工することと、その後の各種処理を施すこと等によっ
て、この凹部の断面形状が通常、第6図及び第7図に示
したようになっている。尚、ここでいう各種の処理と
は、凹部形成後の基板に回路を形成するためのメッキや
溶剤洗浄等の種々な液処理、更にその後の種々な熱処理
等がある。
However, in this recess, the formation is performed by counterboring (milling by moving a rotating bite or the like in a direction orthogonal to the rotation axis) and various subsequent processing. As a result of the application or the like, the cross-sectional shape of this recess is usually as shown in FIGS. 6 and 7. The various treatments mentioned here include various liquid treatments such as plating and solvent cleaning for forming a circuit on the substrate after forming the recesses, and further various heat treatments thereafter.

第6図に示す凹部30は、ザグリ加工におけるメッキ工程
等の液処理がなされたものであって、凹部30の開口縁31
から交差している。これに対して、第7図に示す凹部30
にあっては、ザグリ加工後メッキ工程等による液処理、
多層構造とするための熱処理等の工程が付加された後の
状態のものを示しており、この凹部30にあっては、各種
の処理によって基板を構成している基材自体の膨潤又は
熱収縮による基材内部の応力差によって、凹部30の開口
縁31から底面32に至る側面34と底面32とが鋭角で交差し
ている。
The recess 30 shown in FIG. 6 has been subjected to a liquid treatment such as a plating process in the spot facing process, and has an opening edge 31 of the recess 30.
Intersects from. On the other hand, the recess 30 shown in FIG.
In that case, liquid treatment such as plating process after spot facing,
It shows a state after a step such as heat treatment for forming a multilayer structure is added, and in this concave portion 30, swelling or heat shrinkage of the base material itself which constitutes the substrate by various treatments is shown. Due to the difference in stress inside the base material due to the above, the side surface 34 extending from the opening edge 31 of the recess 30 to the bottom surface 32 and the bottom surface 32 intersect at an acute angle.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

いずれにしても、従来の基板に形成された凹部の断面形
状が上述のような形状、即ち、凹部30の開口縁31から垂
直に下した面33と底面32とが直角に交差しているか、又
は凹部30と開口縁31から底面32に至る側面34と底面32と
が鋭角で交差していると、次のような問題が発生する可
能性が高い。つまり、その交差部分において内部応力が
集中し易く、この交差部分を起点とするワレや亀裂が該
プリント配線基板の基材内部に発生し易くなる。
In any case, the cross-sectional shape of the recess formed in the conventional substrate is the above-described shape, that is, whether the surface 33 and the bottom surface 32 vertically downward from the opening edge 31 of the recess 30 intersect at a right angle, Alternatively, when the recess 30 and the side surface 34 extending from the opening edge 31 to the bottom surface 32 and the bottom surface 32 intersect at an acute angle, the following problem is likely to occur. That is, internal stress is likely to concentrate at the intersection, and cracks or cracks starting from the intersection are likely to occur inside the base material of the printed wiring board.

また、この凹部30に金属被膜からなる導体層を別途形成
しようとする場合には、この導体層の形成はメッキによ
って行われることが多いので、このようなメッキ作業に
おいて凹部30の底面32部分に、断面形状か直角若しくは
鋭角の交差部分があれば、この部分にメッキ液やメッキ
処理液が残留しし易くなる。更に、この交差部分におい
ては、メッキの電流密度が低くなることから、形成され
たメッキ層は部分的に薄くなる。従って、このメッキ層
は、該凹部30との密着性に劣ってメッキ層自身の強度が
弱くなり、基材から剥離したり、破断したりしてしまう
という問題が発生し得る。
Further, when it is desired to separately form a conductor layer made of a metal film in the recess 30, since the formation of the conductor layer is often performed by plating, the bottom surface 32 of the recess 30 is formed in such plating operation. If there is a cross-sectional shape or a crossing of a right angle or an acute angle, the plating liquid or the plating treatment liquid is likely to remain in this portion. Furthermore, since the current density of plating is low at this intersection, the formed plating layer is partially thin. Therefore, this plating layer is inferior in adhesiveness to the concave portion 30 and the strength of the plating layer itself is weakened, which may cause a problem of peeling or breaking from the base material.

このため、例えば、特公昭49-47978号公報にて、第8図
に示すように、「第1面35と、この第1面35に設けられ
た有底形の窪みの底に形成された第2面36と、この第1
面35に鈍角をもって交わるように連続する上記窪みの周
壁面37とを有する絶縁物のパッケージ基板」が提案され
ている。この基板によれば、第1面35に鈍角をもって交
わる周壁面37上に配線部材38を断線の危険性を回避して
形成することができるだけでなく、この配線部材38と第
2面36上に実装した半導体素子14とのボンデイングワイ
ヤ39による電気的接続を容易に行えるものである。
For this reason, for example, in Japanese Patent Publication No. 49-47978, as shown in FIG. 8, "the first surface 35 and the bottom of the bottomed recess formed in the first surface 35 are formed. Second surface 36 and this first
An insulating package substrate having the above-described peripheral wall surface 37 of the recess which is continuous with the surface 35 at an obtuse angle is proposed. According to this substrate, not only the wiring member 38 can be formed on the peripheral wall surface 37 that intersects the first surface 35 with an obtuse angle while avoiding the risk of disconnection, but also on the wiring member 38 and the second surface 36. The electrical connection to the mounted semiconductor element 14 by the bonding wire 39 can be easily performed.

しかし、この第8図に示す従来のパッケージ基板におい
ては、周壁面37を第1面35に鈍角をもって交わるように
連続するものとして形成されているので、第1面35上の
有効面積が小さくなって、この第1面35上における配線
の自由度が大きく制限されることになる。また、周壁面
37には配線部材38が形成されるが、このような傾斜面上
にエッチングレジストあるいはメッキレジストを正確に
形成することは、実際上は非常に困難な作業である。ま
して、このような傾斜状態の周壁面37を有した絶縁基材
を、一般に市販されている板状の積層板から形成するこ
とは、非常に困難であるため、例えばこの傾斜している
周壁面37に対応した専用の型等を予め用意しなければな
らず、パッケージ基板のコストが非常に高くなる。
However, in the conventional package substrate shown in FIG. 8, since the peripheral wall surface 37 is formed continuously so as to intersect the first surface 35 at an obtuse angle, the effective area on the first surface 35 becomes small. Thus, the degree of freedom of wiring on the first surface 35 is greatly limited. Also, the surrounding wall
Although the wiring member 38 is formed on the wiring 37, it is a very difficult work in practice to accurately form the etching resist or the plating resist on such an inclined surface. Furthermore, since it is very difficult to form the insulating base material having the peripheral wall surface 37 in such an inclined state from a plate-like laminated plate which is generally commercially available, for example, the peripheral wall surface inclining. The special mold corresponding to 37 must be prepared in advance, and the cost of the package board becomes very high.

本発明は、上記問題点を克服するものであり、凹部近傍
のワレ、亀裂及びメッキの剥がれが生じにくく、搭載さ
れる電子部品の吸湿を防止し、基板上の有効面積を増大
させ、短距離にて電子部品と配線部材とを接続でき、且
つ容易に製造される凹部を有する、電子部品を搭載した
樹脂基板を提供するものである。
The present invention is to overcome the above problems, cracks near the recess, cracks and peeling of plating are less likely to occur, prevent moisture absorption of electronic components mounted, increase the effective area on the substrate, short distance In order to provide a resin substrate on which an electronic component is mounted, the electronic component and the wiring member can be connected to each other and which has a recess easily manufactured.

〔課題を解決するための手段〕[Means for Solving the Problems]

本発明の電子部品を搭載した樹脂基板は、電子部品搭載
用凹部を有する樹脂基板と、該樹脂基板の上面に形成さ
れた配線部材と、該樹脂基板の該凹部内に収納される電
子部品と、該電子部品と上記配線部材とを電気的に接続
する接続細線と、上記電子部品を上記凹部内に密封する
ための密封部材と、を備える、電子部品を搭載した樹脂
基板において、 上記凹部は、該凹部の開口縁より垂直に下した垂下面
と、平面的な底面と、該垂下面と該底面との延長面との
交差部分から上記凹部の内部空間の中心方向に向けて出
る突出部の表面を構成する傾斜面と、からなり、上記突
出部の縦断面が3角形であり、上記凹部はザグリ加工に
よって形成され、更にその内周全面は金属メッキ被膜に
覆われており、上記樹脂基板の上面は平滑面であり、上
記接続細線は該平滑面上に形成された配線基板と電子部
品とを接続していることを特徴とする。
A resin substrate on which an electronic component of the present invention is mounted includes a resin substrate having a recess for mounting an electronic component, a wiring member formed on the upper surface of the resin substrate, and an electronic component housed in the recess of the resin substrate. In the resin substrate on which the electronic component is mounted, including a connection thin wire that electrically connects the electronic component and the wiring member, and a sealing member for sealing the electronic component in the recess, A projecting portion that extends toward the center of the internal space of the recess from the intersection of the vertical bottom surface that is perpendicular to the opening edge of the recess, the planar bottom surface, and the extension surface of the vertical bottom surface and the bottom surface. The protrusion has a triangular cross section, the recess is formed by counterboring, and the entire inner circumference is covered with a metal plating film. The top surface of the substrate is smooth and The continuous thin line is characterized by connecting the wiring board formed on the smooth surface and the electronic component.

〔作用〕[Action]

本発明においては、凹部の開口縁より垂直な垂下面を有
し、突出部は、この垂下面と底面との延長面との交差部
分から凹部の内部空間の中心方向に向けて出るとともに
凹部内に露出する平面(傾斜面)を有し、その縦断面は
3角形である。従って、基板の上面の有効面積が大きく
なり、そのため、配線部材の配線の自由度が大きくな
る。更に、この突出部近傍が補強され、この部分に例え
応力が集中したとしても、この応力は分散され、更に、
この部分にメッキ液やメッキ前処理液が残留することが
なくなり、またメッキの電流密度が低くなることはな
く、所定厚さのメッキ層を形成することが可能となる。
In the present invention, the projection has a vertical lower surface that is perpendicular to the opening edge of the concave portion, and the projecting portion extends toward the center of the internal space of the concave portion from the intersection of the vertical lower surface and the extension surface of the bottom surface. It has a flat surface (inclined surface) exposed to the inside and its longitudinal section is a triangle. Therefore, the effective area of the upper surface of the substrate is increased, which increases the degree of freedom of wiring of the wiring member. Further, even if the stress is concentrated in this portion by reinforcing the vicinity of this protruding portion, this stress is dispersed, and further,
It is possible to form a plating layer having a predetermined thickness without the plating solution or the pretreatment solution for plating remaining on this portion and the current density of the plating not decreasing.

また、凹部はザグリ加工により形成されるので、容易に
且つ安価に形成できるとともに、一般に市販されている
板状の積層板を利用できる。
Further, since the concave portion is formed by counterboring, it can be easily and inexpensively formed, and a generally commercially available plate-shaped laminated plate can be used.

更に、本発明における配線部材は基板上面に形成されて
いるので、この接続配線は凹部上に突出することとな
る。従って、この凹部の深さを小さくできる。
Further, since the wiring member in the present invention is formed on the upper surface of the substrate, this connection wiring will protrude above the recess. Therefore, the depth of this recess can be reduced.

本発明では、その凹部内壁面の全面(即ち周壁面及び底
面)に金属メッキ被膜が形成されている。この被膜は、
主として電子部品が吸湿することを防止するためのもの
であり、これにより凹部内に配置された電子部品が、樹
脂基板を介して吸湿する不具合を防止できる。
In the present invention, the metal plating film is formed on the entire inner wall surface of the recess (that is, the peripheral wall surface and the bottom surface). This coating is
This is mainly for preventing the electronic components from absorbing moisture, and thus it is possible to prevent the electronic component arranged in the recess from absorbing moisture via the resin substrate.

〔実施例〕〔Example〕

次に、本発明を、図面に示した具体例に従ってより詳細
に説明する。
Next, the present invention will be described in more detail according to the specific examples shown in the drawings.

第1図は、本発明に係る電子部品(半導体素子)搭載用
基板11を採用して形成した、電子部品を搭載したピング
リッドアレイ10Aの縦断面図である。
FIG. 1 is a vertical cross-sectional view of a pin grid array 10A on which electronic components are mounted, which is formed by adopting an electronic component (semiconductor element) mounting substrate 11 according to the present invention.

この電子部品搭載用基板(以下、単に「搭載用基板」と
いう。)11の凹部12内には、第2図に示すように、搭載
用基板11と一体的な突出部20が凹部12の中心部分に向け
て出されているのである。この突出部20は、凹部内に露
出する面が平面(傾斜面)であり且つ縦断面が3角形で
ある。
In the recess 12 of the electronic component mounting substrate (hereinafter simply referred to as “mounting substrate”) 11, a protrusion 20 integral with the mounting substrate 11 is provided at the center of the recess 12 as shown in FIG. It is issued to the part. The protrusion 20 has a flat surface (inclined surface) exposed in the recess and a triangular cross section.

尚、このピングリッドアレイ10Aは、以下のようにして
作製される。即ち、まず、搭載用基板11の凹部12内に、
半導体素子14を固定支持する。その後、この半導体素子
14と搭載用基板11上に形成した導体回路とを、ボンディ
ングワイヤ14aによってそれぞれ接続する。次いで、こ
の半導体素子14の上部を、搭載用基板11に接着したメタ
ルキャップ15によって覆蓋した。また、この電子部品搭
載用ピングリッドアレイ10Aにあっては、その搭載用基
板11に形成した各スルーホール内に、導体ピン16の頭部
を強制嵌合することによって、その名の通りのピングリ
ッドアレイとしたものである。
The pin grid array 10A is manufactured as follows. That is, first, in the recess 12 of the mounting substrate 11,
The semiconductor element 14 is fixedly supported. Then this semiconductor element
The bonding wires 14a connect the 14 and the conductor circuit formed on the mounting substrate 11 to each other. Next, the upper portion of the semiconductor element 14 was covered with a metal cap 15 adhered to the mounting substrate 11. Further, in this electronic component mounting pin grid array 10A, the heads of the conductor pins 16 are forcibly fitted into the through holes formed in the mounting substrate 11 so that the pin as its name implies. It is a grid array.

この搭載用基板11に形成した突出部20は、搭載用基板11
に対して次のような関係にある。即ち、第2図に示すよ
うに、凹部12の底面13周辺に、凹部12の開口縁12aより
垂直に下した面(垂下面)21と、凹部12の底面13の延長
面22との交差部分23から、凹部12の内部空間の中心方向
に向けて出される突出部20を形成したのである。
The protrusion 20 formed on the mounting board 11 is
Has the following relationship. That is, as shown in FIG. 2, in the vicinity of the bottom surface 13 of the recess 12, a portion (vertical bottom surface) 21 vertically lower than the opening edge 12a of the recess 12 and an extension surface 22 of the bottom surface 13 of the recess 12 intersect. The protrusion 20 is formed from 23 toward the center of the internal space of the recess 12.

この関係をより詳細に図示したのが、第5図である。こ
の第5図から明らかなように、凹部12の開口縁12aから
垂下面21と、底面13の延長面22との交差部分23を中心に
見ると、突出部20は少なくとも凹部12の内部空間の中心
方向に向けて出されていることになるのである。これに
よって、この凹部12の底面13近傍においては、直角部分
あるいは鋭角部分が全く存在しない。
FIG. 5 illustrates this relationship in more detail. As is apparent from FIG. 5, when looking at the intersection 23 of the hanging lower surface 21 and the extension surface 22 of the bottom surface 13 from the opening edge 12a of the recess 12, the protrusion 20 is located at least in the internal space of the recess 12. It means that it is directed toward the center. As a result, in the vicinity of the bottom surface 13 of the recess 12, there is no right angle portion or acute angle portion.

この突出部20は、以上のように凹部12の底面13近傍にお
いて直角部分あるいは鋭角部分の存在を無くすためのも
のである。この凹部12は、凹部12の開口縁12aより垂直
に下した垂下面21と、凹部12の平面的な底面13と、該垂
下面と該底面との延長面との交差部分から凹部12の内部
空間の中心(方向)に向けて出されている傾斜面と、か
らなる。以上より、突出部20が凹部12内に突出すること
になり、このように形成することは容易であり、例えば
凹部12内にメッキ層を形成した場合に、このメッキ層の
強度が強くなる。
The projecting portion 20 is for eliminating the presence of a right angle portion or an acute angle portion in the vicinity of the bottom surface 13 of the recess 12 as described above. The recessed portion 12 has an inner surface of the recessed portion 12 that extends vertically from an opening edge 12a of the recessed portion 12, a planar bottom surface 13 of the recessed portion 12, and an intersection of the suspended lower surface and an extension surface of the bottomed surface. The inclined surface is directed toward the center (direction) of the space. As described above, the protrusion 20 protrudes into the recess 12, and it is easy to form in this way. For example, when a plating layer is formed in the recess 12, the strength of the plating layer becomes strong.

このような条件を満足するためには、第2図及び第5図
に示すように、突出部20の凹部12内に露出する面を平面
(傾斜面)として形成する。尚、上記直角部分或いは鋭
角部分をなくす方法としては、第3図(参考図)に示す
ように、凹部12の中心部に向けて凹となる球面として形
成することも考えられる。しかし、この場合には、垂下
面と底面との交差部分の強度が、十分とは言えない。
In order to satisfy such conditions, as shown in FIGS. 2 and 5, the surface of the protrusion 20 exposed in the recess 12 is formed as a flat surface (inclined surface). As a method of eliminating the right-angled portion or the acute-angled portion, as shown in FIG. 3 (reference drawing), it may be possible to form a spherical surface which is concave toward the central portion of the concave portion 12. However, in this case, it cannot be said that the strength of the intersecting portion between the vertically lower surface and the bottom surface is sufficient.

以上のような条件の突出部20を形成するには、突出部20
の凹部12内に露出する面に対応する切削面を有する回転
刃(バイト)によってザグリ加工をする。搭載用基板11
の材質としてはガラスエポキシ樹脂、ガラスポリイミド
樹脂又はガラストリアジン樹脂からなる基材を使用し
た。これは樹脂であるので、ザグリ加工をするためにも
好都合である。
To form the protrusion 20 under the above conditions, the protrusion 20
Counterboring is performed by a rotary blade (bite) having a cutting surface corresponding to the surface exposed in the concave portion (12). Mounting board 11
As the material of the above, a base material made of glass epoxy resin, glass polyimide resin or glass triazine resin was used. Since this is a resin, it is also convenient for counterboring.

また、突出部20の凹部12内に露出する面及び他の面(即
ち凹部の全内周面)は、金属メッキ被膜で覆われてい
る。このようにするのは、凹部12内面に金属被膜を設け
ることにより基材内部を通じての湿気の侵入を防止して
封止信頼性を向上させるとともに、金属被膜自身を接地
導体用の導体回路として採用し、またこの被膜を外部リ
ードと接続させるように設計配線して半導体素子より発
生する熱をこの被膜により速やかに外部へ放散させる効
果を持たせるためである。
The surface of the protrusion 20 exposed in the recess 12 and the other surface (that is, the entire inner peripheral surface of the recess) are covered with a metal plating film. This is done by providing a metal coating on the inner surface of the recess 12 to prevent moisture from penetrating through the inside of the base material and improving sealing reliability, and the metal coating itself is used as a conductor circuit for the ground conductor. In addition, this coating is designed and wired so as to be connected to the external leads, so that the heat generated from the semiconductor element can be quickly dissipated to the outside by the coating.

本実施例で用いた電子部品を搭載した基板において、そ
れに用いた搭載用基板に形成された凹部内には、所定の
突出部を有するので、凹部近傍においてワレや亀裂が生
じにくいし、凹部の内面に形成した導体層が容易に剥離
等の現象も生じにくい。また、ザグリ加工により所定の
凹部を形成するとともに、基板用の絶縁基材として一般
に市販されている板状の積層板を利用したので、最も簡
便で効果的な方法によって、且つ安価に形成することが
できた。
In the substrate on which the electronic component used in this example is mounted, since the predetermined recess is formed in the recess formed in the mounting substrate used therein, cracks and cracks are less likely to occur in the vicinity of the recess, and The conductor layer formed on the inner surface is less likely to cause a phenomenon such as peeling. Further, since a predetermined concave portion is formed by counterboring and a plate-like laminated plate which is generally commercially available is used as an insulating base material for the substrate, it can be formed by the simplest and most effective method at a low cost. I was able to.

更に、凹部の内周面全面にメッキ被膜が形成されている
ので、メタルキャップを被覆固定した後においては、樹
脂基板を介して湿気が凹部に進入することもない。従っ
て、電子部品の信頼性及び寿命を高めることができる。
Further, since the plated coating is formed on the entire inner peripheral surface of the recess, moisture does not enter the recess through the resin substrate after the metal cap is fixed by coating. Therefore, the reliability and life of the electronic component can be improved.

また、凹部は垂下面を有するので、搭載用基板11上の有
効面積を大きくすることができ、その上における配線の
自由度を大きくすることができた。しかも、半導体素子
の表面と搭載用基板の表面とが略同じ高さであり、至近
距離にあるので、この半導体素子と配線部材とをボンデ
イングワイヤにて接続するのに大変便利である。
In addition, since the concave portion has the hanging bottom surface, it is possible to increase the effective area on the mounting substrate 11 and increase the degree of freedom of wiring on the effective area. Moreover, since the surface of the semiconductor element and the surface of the mounting substrate are at substantially the same height and are in a close distance, it is very convenient to connect the semiconductor element and the wiring member with a bonding wire.

尚、本発明においては、前記具体的実施例に示すものに
限られず、目的、用途に応じて本発明の範囲内で種々変
更した実施例とすることができる。即ち、第4図(凹部
の内周面を被覆する金属被膜は省略されている。)は、
第1図に示した電子部品搭載用ピングリッドアレイ10A
とはタイプの異なるチップキャリアパッケージ10Bに、
本発明を実施した状態を示す縦断面図である。このチッ
プキャリアパッケージ10Bにおいても、凹部12の底面13
周辺に、凹部12の開口縁12aより垂下面21と、凹部12の
底面13の延長面22との交差部分23から、凹部12の内部空
間の中心方向に向けて出される突出部20が形成されてい
る。尚、このチップキャリアパッケージ10Bにおいて
は、凹部12内に接地固定した電子部品14の周囲に封止樹
脂17を滴下して、この封止樹脂17が周囲に流れ出ないよ
うにするために、電子部品搭載用基板11の上面に樹脂封
止枠18が固定してある。
The present invention is not limited to the specific examples described above, and various modifications may be made within the scope of the present invention depending on the purpose and application. That is, FIG. 4 (the metal coating covering the inner peripheral surface of the recess is omitted),
Pin grid array 10A for mounting electronic components shown in FIG.
In a different type of chip carrier package 10B,
It is a longitudinal section showing the state where the present invention was implemented. Also in this chip carrier package 10B, the bottom surface 13 of the recess 12 is
A protruding portion 20 is formed in the periphery from the opening edge 12a of the concave portion 12 and an intersecting portion 23 of the extending surface 22 of the bottom surface 13 of the concave portion 12 toward the center of the internal space of the concave portion 12. ing. In this chip carrier package 10B, in order to prevent the sealing resin 17 from flowing out to the periphery by dropping the sealing resin 17 around the electronic component 14 grounded and fixed in the concave portion 12, A resin sealing frame 18 is fixed to the upper surface of the mounting substrate 11.

〔発明の効果〕〔The invention's effect〕

本発明の電子部品を搭載した樹脂基板は、凹部近傍のワ
レ、亀裂及びメッキの剥がれが生じにくく、電子部品の
吸湿を防止し、基板上の有効面積を増大させて配線部材
の配線の自由度を高めることができ、電子部品と配線部
材との接続が容易にでき、且つ容易に製造される凹部を
有するものである。
The resin substrate on which the electronic component of the present invention is mounted is less likely to cause cracks in the vicinity of the recess, cracks and peeling of the plating, prevents moisture absorption of the electronic component, increases the effective area on the substrate, and provides freedom of wiring of the wiring member. It is possible to increase the connection efficiency, facilitate the connection between the electronic component and the wiring member, and have a recess that is easily manufactured.

【図面の簡単な説明】[Brief description of drawings]

第1図は実施例における電子部品を搭載したピングリッ
ドアレイの縦断面図、第2図は本発明に係る電子部品搭
載用基板を示す縦断面図、第3図は参考例としての搭載
用基板を示す縦断面図、第4図は本発明を実施したチッ
プキャリアパッケージの縦断面図、第5図は第2図に示
す突出部の要部拡大縦断面図、第6図は従来の電子部品
搭載用基板を示す縦断面図、第7図は第6図に示す基板
に後処理としての加熱処理等を行った後の状態を示す縦
断面図、第8図は従来の他の電子部品を搭載した基板を
示す縦断面図である。 〔符号の説明〕 10a;電子部品搭載用ピングリッドアレイ、10B;チップキ
ャリアパッケージ、11;電子部品搭載用基板、12;凹部、
12a;開口縁、13;底面、14;半導体素子、20;突出部、21;
垂直に下した面、22;底面の延長面、23;交差部分。
FIG. 1 is a vertical cross-sectional view of a pin grid array on which an electronic component is mounted in an embodiment, FIG. 2 is a vertical cross-sectional view showing an electronic component mounting substrate according to the present invention, and FIG. 3 is a mounting substrate as a reference example. FIG. 4 is a vertical cross-sectional view of a chip carrier package embodying the present invention, FIG. 5 is an enlarged vertical cross-sectional view of a main part of a protrusion shown in FIG. 2, and FIG. 6 is a conventional electronic component. FIG. 7 is a vertical cross-sectional view showing a mounting substrate, FIG. 7 is a vertical cross-sectional view showing a state after the substrate shown in FIG. 6 is subjected to heat treatment as a post-treatment, and FIG. 8 is another conventional electronic component. It is a longitudinal cross-sectional view showing a mounted substrate. [Description of Reference Signs] 10a; electronic component mounting pin grid array, 10B; chip carrier package, 11; electronic component mounting substrate, 12; recess,
12a; opening edge, 13; bottom surface, 14; semiconductor element, 20; protruding portion, 21;
Vertically lowered surface, 22; bottom extension, 23; intersection.

フロントページの続き (56)参考文献 特開 昭59−67686(JP,A) 特開 昭49−47978(JP,A) (社)金属表面技術協会監修,「電気め っきガイド’83」,昭和58年4月1日,全 国鍍金工業組合連合会発光,第30〜31頁 英一太著,「プラスチックメタライジン グ」,1985年11月15日,株式会社シーエム シー発行,第7〜14頁 大島啓治外2名編,「熱硬化性樹脂の圧 縮成形/トランスファ成形」,昭和41年11 月15日,株式会社プラスチック・エージ発 行,第163〜171頁Continuation of the front page (56) References JP-A-59-67686 (JP, A) JP-A-49-47978 (JP, A) Supervised by Japan Metal Surface Technology Association, "Electric plating guide '83", April 1, 1983, National Federation of Plating Industry Associations, Luminescence, pp. 30-31, Eiichita, "Plastic Metallizing," November 15, 1985, CMC, Inc., 7th- Page 14 Keiji Oshima, 2 ed., “Pressure molding / transfer molding of thermosetting resin”, November 15, 1964, issued by Plastic Age Co., Ltd., pp.163-171

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】電子部品搭載用凹部を有する樹脂基板と、
該樹脂基板の上面に形成された配線部材と、該樹脂基板
の該凹部内に収納される電子部品と、該電子部品と上記
配線部材とを電気的に接続する接続細線と、上記電子部
品を上記凹部内に密封するための密封部材と、を備え
る、電子部品を搭載した樹脂基板において、 上記凹部は、該凹部の開口縁より垂直に下した垂下面
と、平面的な底面と、該垂下面と該底面との延長面との
交差部分から上記凹部の内部空間の中心方向に向けて出
る突出部の表面を構成する傾斜面と、からなり、上記突
出部の縦断面が3角形であり、上記凹部はザグリ加工に
よって形成され、更にその内周全面は金属メッキ被膜に
覆われており、 上記樹脂基板の上面は平滑面であり、上記接続細線は該
平滑面上に形成された配線基板と電子部品とを接続して
いることを特徴とする電子部品を搭載した樹脂基板。
1. A resin substrate having a recess for mounting an electronic component,
A wiring member formed on the upper surface of the resin substrate, an electronic component housed in the recess of the resin substrate, a connection thin wire for electrically connecting the electronic component and the wiring member, and the electronic component. A resin substrate having an electronic component mounted thereon, comprising: a sealing member for hermetically sealing the inside of the recess, wherein the recess has a hanging bottom surface perpendicular to an opening edge of the recess, a planar bottom surface, and the hanging surface. An inclined surface forming a surface of a protruding portion that extends from the intersection of the lower surface and the extension surface of the bottom surface toward the center of the inner space of the recess, and the vertical cross section of the protruding portion is a triangle. The concave portion is formed by counterboring, the entire inner circumference is covered with a metal plating film, the upper surface of the resin substrate is a smooth surface, and the connection thin wire is a wiring board formed on the smooth surface. Is characterized by connecting the Equipped with a resin substrate the electronic components.
JP61004656A 1986-01-13 1986-01-13 Resin board with electronic components Expired - Lifetime JPH07120730B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61004656A JPH07120730B2 (en) 1986-01-13 1986-01-13 Resin board with electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61004656A JPH07120730B2 (en) 1986-01-13 1986-01-13 Resin board with electronic components

Publications (2)

Publication Number Publication Date
JPS62163347A JPS62163347A (en) 1987-07-20
JPH07120730B2 true JPH07120730B2 (en) 1995-12-20

Family

ID=11589984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61004656A Expired - Lifetime JPH07120730B2 (en) 1986-01-13 1986-01-13 Resin board with electronic components

Country Status (1)

Country Link
JP (1) JPH07120730B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9052551B2 (en) 1999-07-06 2015-06-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same

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Publication number Priority date Publication date Assignee Title
JP2505359Y2 (en) * 1989-10-13 1996-07-31 住友ベークライト株式会社 Semiconductor mounting board
JP3374732B2 (en) * 1997-11-17 2003-02-10 三菱電機株式会社 Semiconductor element module and semiconductor device
US7859172B2 (en) 2007-06-19 2010-12-28 Epson Toyocom Corporation Piezoelectric resonator, manufacturing method thereof and lid for piezoelectric resonator
JP5112005B2 (en) * 2007-10-25 2013-01-09 日本特殊陶業株式会社 Wiring board with built-in plate-shaped component and manufacturing method thereof
US8384272B2 (en) 2008-01-30 2013-02-26 Kyocera Corporation Acoustic wave device and method for production of same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4947978A (en) * 1972-09-08 1974-05-09

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
(社)金属表面技術協会監修,「電気めっきガイド’83」,昭和58年4月1日,全国鍍金工業組合連合会発光,第30〜31頁
大島啓治外2名編,「熱硬化性樹脂の圧縮成形/トランスファ成形」,昭和41年11月15日,株式会社プラスチック・エージ発行,第163〜171頁
英一太著,「プラスチックメタライジング」,1985年11月15日,株式会社シーエムシー発行,第7〜14頁

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9052551B2 (en) 1999-07-06 2015-06-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US9069215B2 (en) 1999-07-06 2015-06-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US9395584B2 (en) 1999-07-06 2016-07-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same

Also Published As

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