JPH09172104A - Board for semiconductor device - Google Patents
Board for semiconductor deviceInfo
- Publication number
- JPH09172104A JPH09172104A JP33044795A JP33044795A JPH09172104A JP H09172104 A JPH09172104 A JP H09172104A JP 33044795 A JP33044795 A JP 33044795A JP 33044795 A JP33044795 A JP 33044795A JP H09172104 A JPH09172104 A JP H09172104A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- solder resist
- semiconductor device
- thickness
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＢＧＡ（Ball Grid Arra
y)パッケージ等を用いた半導体装置の半導体素子を搭載
する基板に用いる半導体装置用基板に関する。The present invention relates to a BGA (Ball Grid Arra).
y) A substrate for a semiconductor device used as a substrate on which a semiconductor element of a semiconductor device using a package or the like is mounted.
【０００２】[0002]
【従来の技術】ＢＧＡパッケージやＰＧＡ（Pin Grid A
rray) パッケージを用いた半導体装置の半導体素子を搭
載する基板として、近年、製造コスト等の理由からプリ
ント配線基板が用いられるようになってきた。図６(a)
、(b) はＢＧＡパッケージで用いられている基板の従
来例の上面図、底面図である。この基板１０は上面の中
央部に半導体素子を搭載するためのダイアタッチ部１２
が設けられ、底面にはんだボール等の外部接続端子を接
合するためのランド部１４が設けられている。2. Description of the Related Art BGA packages and PGA (Pin Grid A)
In recent years, a printed wiring board has come to be used as a board on which a semiconductor element of a semiconductor device using an (rray) package is mounted, for reasons such as manufacturing cost. Fig. 6 (a)
, (B) are a top view and a bottom view of a conventional example of a substrate used in a BGA package. This substrate 10 has a die attach portion 12 for mounting a semiconductor element in the center of the upper surface.
And a land portion 14 for joining an external connection terminal such as a solder ball is provided on the bottom surface.
【０００３】基板１０の上面には配線パターン１６が設
けられるが、この配線パターン１６は基板の一方の面に
搭載される半導体素子と、基板の他方の面に接合される
はんだボール等の外部接続端子とを電気的に接続するた
めのものである。配線パターン１６の一端には半導体素
子と電気的に接続するためのボンディング部１６ａが設
けられ、配線パターン１６の他端はビア（プリント基板
でのスルーホールの意を含む）に接続して基板の底面に
設けられるランド部１４に電気的に接続する。A wiring pattern 16 is provided on the upper surface of the substrate 10. The wiring pattern 16 is connected to a semiconductor element mounted on one surface of the substrate and an external connection such as a solder ball bonded to the other surface of the substrate. It is for electrically connecting to the terminal. A bonding portion 16a for electrically connecting to a semiconductor element is provided at one end of the wiring pattern 16, and the other end of the wiring pattern 16 is connected to a via (including the meaning of a through hole in a printed circuit board) of the board. It is electrically connected to the land portion 14 provided on the bottom surface.
【０００４】基板１０の表裏面には配線パターン１６の
ボンディング部１６ａとランド部１４を除き配線パター
ンやビア部分を保護するソルダレジスト１８が被覆され
る。図６(a) に示すように基板１０の一方の面でダイア
タッチ部１２の周囲で枠状にソルダレジスト１８を被覆
しない領域は配線パターン１６のボンディング部１６ａ
を露出する部分（露出部２０ａ）である。図７に従来の
基板１０の断面図を示す。ボンディング部１６ａとラン
ド部１４を除いてソルダレジスト１８が被覆されてい
る。なお、基板１０の他方の面でダイアタッチ部１２に
対応する領域に配置するランド部１４ａ搭載した半導体
素子の放熱性を向上させるために設けたサーマルビアと
接続している。The front and back surfaces of the substrate 10 are covered with a solder resist 18 which protects the wiring pattern and vias except for the bonding portions 16a and the land portions 14 of the wiring pattern 16. As shown in FIG. 6 (a), a region around the die attach portion 12 on one surface of the substrate 10 where the solder resist 18 is not covered is a bonding portion 16 a of the wiring pattern 16.
Is a portion (exposed portion 20a) that exposes. FIG. 7 shows a cross-sectional view of the conventional substrate 10. The solder resist 18 is covered except for the bonding portion 16 a and the land portion 14. It should be noted that the other surface of the substrate 10 is connected to a thermal via provided to improve heat dissipation of the semiconductor element mounted with the land portion 14a arranged in a region corresponding to the die attach portion 12.
【０００５】[0005]
【発明が解決しようとする課題】ところで、半導体装置
に用いるプリント配線基板では、半導体装置の小型化、
薄型化の要請から０．２ｍｍ厚といった非常に薄い基板
が使用されるようになってきたことから、基板に反りが
あらわれることが問題になっている。本発明者はこの基
板の反りについて検討した結果、基板１０の両面に塗布
したソルダレジスト１８に起因するものであることを見
いだした。すなわち、半導体装置に用いるプリント配線
基板では上記のように基板の一方の面と他方の面とでソ
ルダレジスト１８の被覆領域が異なることとソルダレジ
スト１８を同じ厚さ（５０〜７０μｍ）としていること
から、ソルダレジスト１８を塗布した後に熱硬化させた
際の収縮度が基板の一方の面と他方の面とで異なり、こ
れによって基板の反りが生じる。By the way, in the printed wiring board used for the semiconductor device, the semiconductor device is downsized,
Since a very thin substrate having a thickness of 0.2 mm has come to be used due to the demand for thinning, it is a problem that the substrate warps. As a result of examining the warp of the substrate, the present inventor has found that it is caused by the solder resist 18 applied on both surfaces of the substrate 10. That is, in the printed wiring board used for the semiconductor device, as described above, the one surface and the other surface of the board have different coverage areas of the solder resist 18, and the solder resist 18 has the same thickness (50 to 70 μm). Therefore, the degree of shrinkage when the solder resist 18 is applied and then thermally cured is different between the one surface and the other surface of the substrate, which causes the substrate to warp.
【０００６】図６(a) 、(b) に示す従来の基板１０で、
半導体素子を搭載する一方の面と外部接続端子を接合す
る他方の面でのソルダレジスト１８の被覆面積を比較す
ると、基板の一方の面を１として他方の面ではランド部
１４、１４ａの設置数によって若干ばらつき約１．３〜
１．５となる。基板の他方の面ではランド部１４、１４
ａが露出するが、基板の一方の面ではボンディング部１
６ａが比較的大きく露出する結果、全体としてのソルダ
レジスト１８の被覆面積は基板の一方の面の方が小さく
なる。In the conventional substrate 10 shown in FIGS. 6 (a) and 6 (b),
Comparing the coverage areas of the solder resist 18 on the one surface on which the semiconductor element is mounted and the other surface on which the external connection terminals are joined, the number of lands 14 and 14a installed on one surface of the substrate is 1 and on the other surface. Slight variation due to approx. 1.3 ~
It becomes 1.5. On the other surface of the substrate, the land portions 14, 14
Although a is exposed, the bonding portion 1 is formed on one surface of the substrate.
As a result of the relatively large exposure of 6a, the overall coverage area of the solder resist 18 is smaller on one side of the substrate.
【０００７】半導体装置用基板として用いるプリント配
線基板は従来は比較的厚いもの（１．２〜１．６ｍｍ厚
程度）が使用されており、一定の強度があったことから
基板の反りが大きくあらわれることがなく、さほど問題
とされなかったのに対し、最近は半導体装置の小型化の
要請から板厚の薄いプリント配線基板（０．３〜０．６
ｍｍ厚程度）が使用されるようになってきたことから、
基板の強度が低下し、基板の反りが生じやすく、その結
果、基板の反りが問題になってきたものである。Conventionally, a printed wiring board used as a substrate for a semiconductor device is relatively thick (about 1.2 to 1.6 mm thick), and since it has a certain strength, the warp of the board appears largely. However, recently, due to the demand for miniaturization of the semiconductor device, the printed wiring board (0.3 to 0.6
mm thickness) has come to be used,
The strength of the substrate is lowered and the substrate is likely to warp, and as a result, the substrate warpage has become a problem.
【０００８】このような半導体装置用基板の反りは、基
板と半導体素子との密着性を低下させ、基板から半導体
素子が剥離しやすくなったり、基板に搭載した半導体素
子に応力を作用させて、半導体装置としての信頼性を阻
害させるという問題がある。本発明は、このような半導
体装置の基板として用いる半導体装置用基板の反りの問
題を解消することを目的とするものである。Such warpage of the substrate for a semiconductor device reduces the adhesion between the substrate and the semiconductor element, makes it easier for the semiconductor element to peel from the substrate, or causes stress to act on the semiconductor element mounted on the substrate. There is a problem of impairing the reliability as a semiconductor device. An object of the present invention is to solve the problem of warpage of a semiconductor device substrate used as a substrate of such a semiconductor device.
【０００９】[0009]
【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち、基板の一方の面
に、半導体素子を搭載するダイアタッチ部と一端が前記
半導体素子と電気的に接続するボンディング部を成す配
線パターンとが設けられ、基板の他方の面に、外部接続
端子を設けるためのランド部がビアを介して前記配線パ
ターンと電気的に接続して設けられ、前記ボンディング
部及び前記ランド部を露出して基板の両面がソルダレジ
ストによって被覆され、前記基板の一方の面の前記ソル
ダレジストの被覆面積と前記基板の他方の面の前記ソル
ダレジストの被覆面積との比率が約１：１．３〜１：
１．７であり、かつ、前記基板の一方の面を被覆するソ
ルダレジストの厚さと前記基板の他方の面を被覆するソ
ルダレジストの厚さとの比率が３：１〜１．５：１の範
囲であることを特徴とする。また、前記基板の一方の面
の前記ソルダレジストの被覆面積と前記基板の他方の面
の前記ソルダレジストの被覆面積との比率が約１：１．
５であることを特徴とする。また、前記ボンディング部
が前記ダイアタッチ部の近傍に設けられたことを特徴と
する。また、基板の一方の面に、半導体素子を搭載する
ダイアタッチ部と一端が前記半導体素子と電気的に接続
するボンディング部を成す配線パターンとが設けられ、
基板の他方の面に、外部接続端子を設けるためのランド
部がビアを介して前記配線パターンと電気的に接続して
設けられ、前記ボンディング部及び前記ランド部を露出
して基板の両面がソルダレジストによって被覆された半
導体装置用基板において、前記ランド部が前記基板の一
方の面を被覆するソルダレジストの領域と対応する他方
の面の領域に設けられ、前記基板の他方の面を被覆する
ソルダレジストの領域が前記基板の一方の面を被覆した
ソルダレジストの領域と対応した領域であり、前記基板
の一方の面のソルダレジストの厚さと他方の面のソルダ
レジストの厚さが略同一であることを特徴とする。ま
た、基板の一方の面を被覆するソルダレジストの領域が
複数の独立した領域に分割されていることを特徴とす
る。The present invention has the following constitution in order to achieve the above object. That is, a die attach portion on which a semiconductor element is mounted and a wiring pattern whose one end constitutes a bonding portion for electrically connecting to the semiconductor element are provided on one surface of the substrate, and an external connection terminal is provided on the other surface of the substrate. A land portion for providing the wiring portion is electrically connected to the wiring pattern via a via, the bonding portion and the land portion are exposed, and both surfaces of the substrate are covered with a solder resist. The ratio of the area covered by the solder resist to the area covered by the solder resist on the other surface of the substrate is about 1: 1.3 to 1: 1.
1.7, and the ratio of the thickness of the solder resist coating one surface of the substrate to the thickness of the solder resist coating the other surface of the substrate is in the range of 3: 1 to 1.5: 1. Is characterized in that. Further, the ratio of the area covered with the solder resist on one surface of the substrate to the area covered with the solder resist on the other surface of the substrate is about 1: 1.
5 is characterized. Further, the bonding portion is provided in the vicinity of the die attach portion. Further, on one surface of the substrate, a die attach portion on which a semiconductor element is mounted and a wiring pattern forming a bonding portion whose one end is electrically connected to the semiconductor element are provided.
A land portion for providing an external connection terminal is provided on the other surface of the substrate by electrically connecting to the wiring pattern through a via, and the bonding portion and the land portion are exposed so that both surfaces of the substrate are soldered. In a semiconductor device substrate covered with a resist, the land portion is provided in a region of the other surface corresponding to a region of a solder resist covering one surface of the substrate, and a solder covering the other surface of the substrate. The resist region is a region corresponding to the solder resist region covering one surface of the substrate, and the thickness of the solder resist on one surface of the substrate and the thickness of the solder resist on the other surface are substantially the same. It is characterized by In addition, the area of the solder resist covering one surface of the substrate is divided into a plurality of independent areas.
【００１０】[0010]
【発明の実施の形態】以下、本発明の好適な実施形態を
添付図面に基づいて詳細に説明する。本発明に係る半導
体装置用基板の第１の実施形態は、基板の一方の面と他
方の面を被覆するソルダレジストを異なる厚さに設定す
ることによって基板の反りを抑えるものである。すなわ
ち、本実施形態の半導体装置用基板はソルダレジストの
被覆領域を図６に示す従来例と同様に、基板の一方の面
ではダイアタッチ部１２の周囲に配置されるボンディン
グ部１６ａの領域と基板の他方の面ではランド部１４を
除く部分とし、基板の一方の面と他方の面のソルダレジ
スト１８の厚さを変えるようにすることを特徴とする。Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. The first embodiment of the semiconductor device substrate according to the present invention suppresses warpage of the substrate by setting different thicknesses of the solder resist coating one surface and the other surface of the substrate. That is, in the semiconductor device substrate of the present embodiment, the solder resist coating region is similar to the conventional example shown in FIG. 6, and on one surface of the substrate, the region of the bonding portion 16a arranged around the die attach portion 12 and the substrate. The other surface is a portion excluding the land portion 14, and the thickness of the solder resist 18 on one surface and the other surface of the substrate is changed.
【００１１】なお、基板の一方の面でダイアタッチ部１
２の周囲に配線パターン１６のボンディング部１６ａを
配置する構成はワイヤボンディング法によって半導体素
子と配線パターンとを接続する場合で、たとえばフリッ
プチップボンディング法によって半導体素子と配線パタ
ーンとを接続する場合はダイアタッチ部１２の領域内で
半導体素子とボンディングする領域部分を除いてソルダ
レジスト１８をコーティングする。このように半導体素
子と配線パターン１６との電気的接続はワイヤボンディ
ング法に限るものではない。It should be noted that the die attach portion 1 is formed on one surface of the substrate.
The configuration in which the bonding portion 16a of the wiring pattern 16 is arranged around 2 is a case where the semiconductor element and the wiring pattern are connected by the wire bonding method, for example, when the semiconductor element and the wiring pattern are connected by the flip chip bonding method. The solder resist 18 is coated in the area of the touch portion 12 except for the area where the semiconductor element is bonded. As described above, the electrical connection between the semiconductor element and the wiring pattern 16 is not limited to the wire bonding method.
【００１２】図１に本実施形態での基板１０の断面図を
示す。基板１０上でのソルダレジスト１８の被覆領域は
図７に示す従来例と同様であるが、基板１０の一方の面
を被覆するソルダレジスト１８の厚さが他方の面での厚
さよりも厚く形成されている。１４ａは基板１０の他方
の面でダイアタッチ部１２に対応する領域に配置するラ
ンド部で、ダイアタッチ部１２に接続するサーマルビア
と接続している。配線パターン１６に電気的に接続する
ランド部１４は、基板１０の他方の面でダイアタッチ部
１２に対応する領域を除く領域に配置する。FIG. 1 shows a sectional view of the substrate 10 in this embodiment. The coverage area of the solder resist 18 on the substrate 10 is the same as that of the conventional example shown in FIG. 7, but the thickness of the solder resist 18 that covers one surface of the substrate 10 is made thicker than the thickness on the other surface. Has been done. 14 a is a land portion arranged in the region corresponding to the die attach portion 12 on the other surface of the substrate 10, and is connected to a thermal via connected to the die attach portion 12. The land portion 14 electrically connected to the wiring pattern 16 is arranged on the other surface of the substrate 10 in a region other than the region corresponding to the die attach portion 12.
【００１３】本実施形態の半導体装置用基板は基板１０
で半導体素子を搭載する面を被覆するソルダレジスト１
８の厚さを基板１０でランド部１４、１４ａを設けた他
方の面を被覆するソルダレジスト１８の厚さよりも厚く
することにより、基板１０の反りを抑えたものである。
すなわち、本実施形態の半導体装置用基板では基板の両
面を被覆するソルダレジスト１８の厚さを調節すること
により、基板の両面でのソルダレジスト１８の収縮度を
バランスさせ、これによって基板の反り防止を図ってい
る。The semiconductor device substrate of this embodiment is the substrate 10.
Solder resist 1 that covers the surface on which the semiconductor element is mounted with
The warp of the substrate 10 is suppressed by making the thickness of No. 8 thicker than the thickness of the solder resist 18 covering the other surface of the substrate 10 on which the land portions 14 and 14a are provided.
That is, in the semiconductor device substrate of the present embodiment, by adjusting the thickness of the solder resist 18 that covers both surfaces of the substrate, the degree of shrinkage of the solder resist 18 on both surfaces of the substrate is balanced, thereby preventing warpage of the substrate. I am trying to
【００１４】表１に、基板の一方の面と他方の面を被覆
するソルダレジスト１８の厚さを変えた場合に、基板の
反りがどのようにあらわれるかを実験した結果を示す。
サンプルの基板は３０ｍｍ角で、図６に示す従来例と同
様に、基板の一方の面では矩形のダイアタッチ部１２の
周囲に露出部２０ａを設け、他方の面ではランド部１
４、１４ａを除いてソルダレジスト１８を塗布する。表
１で示した値は、各々１０個のサンプルについて測定し
た結果である。なお、基板１０に塗布するソルダレジス
ト１８は配線パターン１６を被覆した際にソルダレジス
ト１８の表面が平坦になるように厚さを設定する必要が
ある。従来の半導体装置用基板ではこのことを考慮して
ソルダレジスト１８の厚さを５０〜７０μｍとしてい
る。実験ではソルダレジスト１８の基準となる厚さを７
０μｍとした。表でAVG.は基板の平均反り量、MAX.は基
板の最大反り量、MIN.は基板の最小反り量を示す。Table 1 shows the results of experiments on how the warp of the substrate appears when the thickness of the solder resist 18 covering one surface and the other surface of the substrate is changed.
The substrate of the sample is 30 mm square, and similarly to the conventional example shown in FIG. 6, the exposed portion 20a is provided around the rectangular die attach portion 12 on one surface of the substrate and the land portion 1 is formed on the other surface.
Solder resist 18 is applied except for portions 4 and 14a. The values shown in Table 1 are the results measured for 10 samples each. The thickness of the solder resist 18 applied to the substrate 10 must be set so that the surface of the solder resist 18 becomes flat when the wiring pattern 16 is covered. In the conventional semiconductor device substrate, the thickness of the solder resist 18 is set to 50 to 70 μm in consideration of this fact. In the experiment, the standard thickness of the solder resist 18 is set to 7
It was set to 0 μm. In the table, AVG. Is the average warp amount of the substrate, MAX. Is the maximum warp amount of the substrate, and MIN. Is the minimum warp amount of the substrate.
【００１５】[0015]
【表１】 [Table 1]
【００１６】表１では、基板の一方の面と他方の面に被
覆したソルダレジストの厚さを、ソルダレジスト表／裏
の欄で示している。たとえば、ソルダレジスト表／裏が
７０／４０とは基板の一方の面と他方の面のソルダレジ
ストの厚さを各々７０μｍ、４０μｍとしたことを意味
する。基板の両面に塗布したソルダレジスト１８の被覆
面積の比率は従来の基板と同様で（基板の一方の面のソ
ルダレジストの被覆面積）：（基板の他方の面のソルダ
レジストの被覆面積）＝１：１．５である。表中で反り
方向が凸とあるのは当該サンプルで基板の一方の面が外
側に凸となる向きに反ったことを示す。In Table 1, the thickness of the solder resist coated on one surface and the other surface of the substrate is shown in the front and back columns of the solder resist. For example, the front / back side of the solder resist is 70/40, which means that the thicknesses of the solder resist on one surface and the other surface of the substrate are 70 μm and 40 μm, respectively. The ratio of the coated area of the solder resist 18 applied to both surfaces of the substrate is the same as that of the conventional substrate (the coated area of the solder resist on one surface of the substrate): (the coated area of the solder resist on the other surface of the substrate) = 1 : 1.5. In the table, the warp direction is convex means that one surface of the substrate in the sample is warped in a direction in which it is convex outward.
【００１７】表１で、Ｎｏ．１、６、８は本実施形態の
半導体装置用基板の比較例としての実験結果であり、基
板の両面でソルダレジスト１８の厚さを同じくした基板
で、基板の厚さが異なるサンプルについての結果であ
る。これらの測定結果は半導体装置を薄型にするため厚
さの薄い基板を使用すると、基板の反りが問題になるこ
とを示している。In Table 1, No. 1, 6 and 8 are experimental results as a comparative example of the semiconductor device substrate of the present embodiment, and are results of samples in which the thickness of the solder resist 18 is the same on both surfaces of the substrate and the thickness of the substrate is different. Is. These measurement results indicate that when a thin substrate is used to make the semiconductor device thin, warpage of the substrate becomes a problem.
【００１８】Ｎｏ．２、３、４、５は本実施形態に対応
する測定結果で、基板の厚さが０．２ｍｍの基板に対
し、基板の一方の面と他方の面で異なる厚さにソルダレ
ジスト１８を塗布した場合の反り量を測定した結果を示
す。この実験結果からはＮｏ．４の場合が反りを抑える
のにもっとも有効で、次いで、Ｎｏ．３、Ｎｏ．２の順
に有効であることがわかる。Ｎｏ．４の場合は従来品
（Ｎｏ．１）とくらべて基板の反り量が１／５程度まで
減少し、Ｎｏ．３、Ｎｏ．２の場合は従来品の基板の反
り量の１／２程度まで減少している。Ｎｏ．５のサンプ
ルは他のサンプルとは逆向きに反り、反り量は従来品の
３／４程度である。Ｎｏ．７は基板の厚さが０．４ｍｍ
の基板に対しての実験結果で、Ｎｏ．６の比較例とくら
べて基板の反り量が１／２程度まで減少している。No. 2, 3, 4, and 5 are measurement results corresponding to the present embodiment, in which a solder resist 18 is applied to a substrate having a thickness of 0.2 mm at different thicknesses on one surface and the other surface of the substrate. The results of measuring the amount of warp in the case of performing are shown. No. The case of No. 4 is the most effective in suppressing the warp, and then No. 4 is used. 3, No. It turns out that it is effective in the order of 2. No. In the case of No. 4, the warp amount of the substrate was reduced to about 1/5 as compared with the conventional product (No. 1). 3, No. In the case of 2, the warp amount of the conventional substrate is reduced to about 1/2. No. The sample No. 5 warps in the opposite direction to the other samples, and the amount of warpage is about 3/4 that of the conventional product. No. 7 has a substrate thickness of 0.4 mm
No. Compared with the comparative example of No. 6, the warp amount of the substrate is reduced to about 1/2.
【００１９】これらの実験結果は、基板の一方の面と他
方の面に塗布するソルダレジスト１８の厚さの比率を約
３：１〜１．５：１に設定することによって基板の反り
を有効に抑えることができることを示す。なお、本実験
結果は基板の一方の面と他方の面でのソルダレジスト１
８の被覆面積の比率が１：１．５の場合であるが、ラン
ド部の配置数によってソルダレジストの被覆面積が１：
１．３〜１：１．７程度の基板についても同様に有効と
考えられる。The results of these experiments show that the warp of the substrate is effective by setting the thickness ratio of the solder resist 18 applied to one surface of the substrate to the other surface to about 3: 1 to 1.5: 1. It can be suppressed to. The results of this experiment are based on the solder resist 1 on one surface and the other surface of the substrate.
8 is the case where the ratio of the covered area is 1: 1.5, but the covered area of the solder resist is 1: depending on the number of arranged land portions.
It is considered that a substrate having a thickness of 1.3 to 1: 1.7 is similarly effective.
【００２０】上記実施形態では基板の一方の面と他方の
面のソルダレジスト１８の厚さを変えて基板の反りを抑
えたが、別の方法として、基板の両面に塗布するソルダ
レジスト１８の厚さを同じくし、図２、３に示すように
基板の両面でのソルダレジスト１８の被覆領域を同じく
することによって基板の反りを抑える方法がある。In the above-described embodiment, the thickness of the solder resist 18 on one surface and the other surface of the substrate is changed to suppress the warp of the substrate. However, as another method, the thickness of the solder resist 18 applied to both surfaces of the substrate may be changed. In the same manner, there is a method of suppressing the warp of the substrate by making the coating areas of the solder resist 18 on both surfaces of the substrate the same as shown in FIGS.
【００２１】図２は本発明に係る半導体装置用基板の第
２実施形態を示す。図２(a) は基板１０の半導体素子を
搭載する面の平面図、図２(b) は外部接続端子を接合す
る面の平面図である。基板の一方の面でのソルダレジス
ト１８の被覆領域は図６に示す従来例と同様でダイアタ
ッチ部１２の周囲のボンディング部１６ａを枠状に露出
させている。一方、基板の他方の面のソルダレジスト１
８の被覆領域は、ランド部１４、１４ａと、基板１０の
一方の面の露出部２０ａに対応して設けた露出部２０ｂ
を除いた領域である。露出部２０ｂは基板の一方の面に
設けた露出部２０ａと同一配置で同一形状に設けるもの
である。FIG. 2 shows a second embodiment of the semiconductor device substrate according to the present invention. 2A is a plan view of the surface of the substrate 10 on which the semiconductor element is mounted, and FIG. 2B is a plan view of the surface to which the external connection terminals are joined. The coverage area of the solder resist 18 on one surface of the substrate is the same as in the conventional example shown in FIG. 6, and the bonding portion 16a around the die attach portion 12 is exposed like a frame. On the other hand, the solder resist 1 on the other surface of the substrate
The covering region 8 includes the land portions 14 and 14a and the exposed portion 20b provided corresponding to the exposed portion 20a on one surface of the substrate 10.
It is the area excluding. The exposed portion 20b has the same arrangement and the same shape as the exposed portion 20a provided on one surface of the substrate.
【００２２】図３に上記実施形態の基板１０の断面図を
示す。基板１０の一方の面でダイアタッチ部１２の周囲
のボンディング部１６ａが露出して露出部２０ａとなっ
ており、この露出部２０ａに対応して基板１０の他方の
面に露出部２０ｂが設けられている。１４は配線パター
ン１６と電気的に接続されたランド部、１４ａはダイア
タッチ部１２に接続するサーマルビアと接続するランド
部である。露出部２０ｂは基板１０が露出する領域で、
この領域内にはランド部１４を配置しない。FIG. 3 shows a sectional view of the substrate 10 of the above embodiment. The bonding portion 16a around the die attach portion 12 is exposed on one surface of the substrate 10 to form an exposed portion 20a, and the exposed portion 20b is provided on the other surface of the substrate 10 corresponding to the exposed portion 20a. ing. Reference numeral 14 is a land portion electrically connected to the wiring pattern 16, and reference numeral 14 a is a land portion connected to a thermal via connected to the die attach portion 12. The exposed portion 20b is a region where the substrate 10 is exposed,
The land portion 14 is not arranged in this area.
【００２３】図４は基板の一方の面の露出部２０ａと他
方の面の露出部２０ｂを対応して設けた実施形態で、基
板１０の両面を被覆するソルダレジスト１８の被覆領域
を複数の独立した領域に分割した実施形態を示す。この
実施形態の半導体装置用基板も第２実施形態と同様に基
板の一方の面と他方の面を被覆するソルダレジスト１８
の厚さを同一にするとともに、基板の一方の面に設ける
露出部２０ａと同一形状の露出部２０ｂを基板の他方の
面に対応させて設けてソルダレジスト１８を塗布する。FIG. 4 shows an embodiment in which an exposed portion 20a on one surface of the substrate and an exposed portion 20b on the other surface are provided in correspondence with each other. An embodiment divided into the divided regions is shown. The semiconductor device substrate of this embodiment is also a solder resist 18 that covers one surface and the other surface of the substrate as in the second embodiment.
Of the same thickness, the exposed portion 20a provided on one surface of the substrate and the exposed portion 20b having the same shape are provided corresponding to the other surface of the substrate, and the solder resist 18 is applied.
【００２４】図４(a) は基板１０の一方の面の平面図、
図４(b) は基板１０の他方の面の平面図である。この実
施形態の基板１０ではダイアタッチ部１２の周囲を枠状
に露出してボンディング部１６ａを露出させるととも
に、この枠状に設けた露出部のコーナー部と基板のコー
ナー部との間を一定幅で露出させてソルダレジスト１８
を被覆している。基板１０の他方の面では、図４(b) に
示すように露出部２０ａと対応する領域に同一形状で露
出部２０ｂを設ける。ランド部１４、１４ａは露出部２
０ｂを除く範囲に配置する。FIG. 4 (a) is a plan view of one surface of the substrate 10,
FIG. 4B is a plan view of the other surface of the substrate 10. In the substrate 10 of this embodiment, the periphery of the die attach portion 12 is exposed in a frame shape to expose the bonding portion 16a, and a constant width is provided between the corner portion of the exposed portion provided in the frame shape and the corner portion of the substrate. Exposed with solder resist 18
Is coated. On the other surface of the substrate 10, as shown in FIG. 4B, an exposed portion 20b having the same shape is provided in a region corresponding to the exposed portion 20a. The land portions 14 and 14a are exposed portions 2
It is arranged in the range excluding 0b.
【００２５】表２は基板の一方の面と他方の面を被覆す
るソルダレジスト１８の被覆領域を一致させた場合に基
板１０の反りがどのように生じるかを実験した結果を示
す。サンプルで用いた基板１０のソルダレジスト１８の
被覆領域は図２に示した実施形態と同様である。使用し
た基板は表１での実験で使用したものと同じものであ
り、測定方法および測定条件は前述した表１の場合と同
様である。この測定では基板の一方の面と他方の面での
ソルダレジスト１８の被覆領域を一致させるから、基板
の一方の面と他方の面でのソルダレジスト１８の被覆領
域の比率は１：１となる。Table 2 shows the result of an experiment on how the warp of the substrate 10 occurs when the coating areas of the solder resist 18 for coating one surface of the substrate and the other surface of the substrate are matched. The coverage area of the solder resist 18 of the substrate 10 used in the sample is the same as that of the embodiment shown in FIG. The substrate used is the same as that used in the experiment in Table 1, and the measurement method and the measurement conditions are the same as those in Table 1 described above. In this measurement, the coverage areas of the solder resist 18 on one surface and the other surface of the substrate are matched, so that the ratio of the coverage area of the solder resist 18 on one surface and the other surface of the substrate is 1: 1. .
【００２６】[0026]
【表２】 [Table 2]
【００２７】表２で、Ｎｏ．９の測定結果はソルダレジ
スト１８の被覆領域を基板の一方の面と他方の面で一致
させ、かつ一方の面と他方の面のソルダレジスト１８の
厚さを一致させた場合、Ｎｏ．１０の測定結果はソルダ
レジスト１８の被覆領域を一致させ、かつ基板の一方の
面のソルダレジスト１８の厚さを他方の面のソルダレジ
スト１８の厚さよりも厚くした場合である。実験結果
は、ソルダレジストの厚さを基板の両面で一致させた場
合に有効で、基板の両面での厚さを変えると反りが大き
くあらわれることを示す。Ｎｏ．９の測定結果は従来品
（Ｎｏ．１）の反り量に比較して、１／３程度の反り量
となっている。In Table 2, No. The measurement result of No. 9 was No. 9 when the coverage area of the solder resist 18 was matched on one surface and the other surface of the substrate, and the thickness of the solder resist 18 on one surface and the other surface was matched. The measurement result of No. 10 is the case where the coating areas of the solder resist 18 are made to coincide with each other, and the thickness of the solder resist 18 on one surface of the substrate is made thicker than the thickness of the solder resist 18 on the other surface. The experimental results show that it is effective when the thickness of the solder resist is made to be the same on both sides of the substrate, and that when the thickness of both sides of the substrate is changed, a large amount of warpage appears. No. The measurement result of No. 9 is about 1/3 of the warp amount of the conventional product (No. 1).
【００２８】本実験結果は、基板の他方の面におけるソ
ルダレジスト１８の被覆領域を基板の一方の面でのソル
ダレジスト１８の被覆領域と対応させて同一形状とし、
基板の両面を被覆するソルダレジスト１８の厚さを一致
させることによって基板の反りを有効に抑えることがで
きることを示す。なお、この実施形態の場合は基板の他
方の面に設けるランド部１４はソルダレジスト１８の露
出部２０ｂを避けて配置する必要がある。The results of this experiment show that the coating area of the solder resist 18 on the other surface of the substrate is made to have the same shape by making it correspond to the coating area of the solder resist 18 on one surface of the substrate.
It is shown that the warp of the substrate can be effectively suppressed by making the thicknesses of the solder resists 18 covering both surfaces of the substrate the same. In this embodiment, the land portion 14 provided on the other surface of the substrate needs to be arranged so as to avoid the exposed portion 20b of the solder resist 18.
【００２９】図４に示したように基板１０の表面をソル
ダレジスト１８で被覆する際に、基板面を露出部で複数
の領域に分割するようにすると、ソルダレジスト１８を
硬化させる際の収縮を分散させることができ、基板１０
の反りを抑えるという効果がある。図５はこのように基
板１０をソルダレジスト１８で被覆する際に基板面を複
数の領域に分割する他の例として示すものである。図５
では、基板のランド部１４を形成する面で対角線方向に
一定幅で露出部２０ｂを設け、基板面を４つの領域に分
割してソルダレジスト１８を被覆している。このよう
に、基板１０をソルダレジスト１８で被覆する際に複数
の領域に分割することにより、ソルダレジスト１８は各
領域ごとに収縮するから基板の全面にソルダレジスト１
８を塗布した場合にくらべて基板の反りを抑えることが
可能になる。As shown in FIG. 4, when the surface of the substrate 10 is covered with the solder resist 18, if the surface of the substrate is divided into a plurality of regions at the exposed portions, shrinkage when the solder resist 18 is cured is reduced. Substrate 10 that can be dispersed
This has the effect of suppressing the warp of the. FIG. 5 shows another example of dividing the substrate surface into a plurality of regions when the substrate 10 is coated with the solder resist 18 as described above. FIG.
In the above, the exposed portion 20b is provided with a constant width in the diagonal direction on the surface forming the land portion 14 of the substrate, the substrate surface is divided into four regions, and the solder resist 18 is covered. Thus, when the substrate 10 is divided into a plurality of regions when the substrate 10 is covered with the solder resist 18, the solder resist 18 shrinks in each region, so that the solder resist 1 is formed on the entire surface of the substrate.
The warp of the substrate can be suppressed as compared with the case where 8 is applied.
【００３０】[0030]
【発明の効果】本発明に係る半導体装置用基板によれ
ば、上述したように、基板の一方の面と他方の面でのソ
ルダレジストの塗布面積が異なる場合には基板の一方の
面と他方の面で異なる厚さにソルダレジストを塗布する
こと、あるいは基板の一方の面と他方の面を被覆するソ
ルダレジストの領域を対応して設定して塗布面積を一致
させた場合には基板の一方の面と他方の面で同厚にソル
ダレジストを塗布することによって、従来の半導体装置
用基板で生じた反り量を１／２以下まで軽減することが
可能になった。これにより、半導体装置用基板に半導体
素子を搭載した際に半導体素子が基板から剥離したり、
半導体素子に余分の応力が加わることを抑制することが
でき、より信頼性の高い半導体装置用基板として提供す
ることができる等の著効を奏する。As described above, according to the semiconductor device substrate of the present invention, when the solder resist coating areas on one surface and the other surface of the substrate are different from each other, If the solder resist is applied in different thicknesses on one side of the board, or if the areas of the solder resist that cover one side and the other side of the board are set correspondingly and the application areas are matched, By applying the solder resist with the same thickness on the surface and the other surface, it is possible to reduce the amount of warpage that has occurred in the conventional semiconductor device substrate to 1/2 or less. Thereby, when the semiconductor element is mounted on the semiconductor device substrate, the semiconductor element peels from the substrate,
It is possible to suppress application of extra stress to the semiconductor element, and it is possible to provide a highly reliable substrate for a semiconductor device, and so on.
【図１】半導体装置用基板の第１実施形態の断面図であ
る。FIG. 1 is a cross-sectional view of a first embodiment of a semiconductor device substrate.
【図２】半導体装置用基板の第２実施形態の上下面の平
面図である。FIG. 2 is a plan view of the upper and lower surfaces of a semiconductor device substrate according to a second embodiment.
【図３】半導体装置用基板の第２実施形態の断面図であ
る。FIG. 3 is a cross-sectional view of a second embodiment of a semiconductor device substrate.
【図４】半導体装置用基板の第３実施形態の上下面の平
面図である。FIG. 4 is a plan view of upper and lower surfaces of a semiconductor device substrate according to a third embodiment.
【図５】半導体装置用基板の第４実施形態の底面図であ
る。FIG. 5 is a bottom view of the fourth embodiment of the semiconductor device substrate.
【図６】半導体装置用基板の従来例の上下面の平面図で
ある。FIG. 6 is a plan view of upper and lower surfaces of a conventional example of a semiconductor device substrate.
【図７】半導体装置用基板の従来例の断面図である。FIG. 7 is a cross-sectional view of a conventional example of a semiconductor device substrate.
１０ 基板 １２ ダイアタッチ部 １４ ランド部 １４ａ ランド部 １６ 配線パターン １６ａ ボンディング部 １８ ソルダレジスト ２０ａ、２０ｂ 露出部 10 substrate 12 die attach part 14 land part 14a land part 16 wiring pattern 16a bonding part 18 solder resist 20a, 20b exposed part
Claims (5)
るダイアタッチ部と一端が前記半導体素子と電気的に接
続するボンディング部を成す配線パターンとが設けら
れ、基板の他方の面に、外部接続端子を設けるためのラ
ンド部がビアを介して前記配線パターンと電気的に接続
して設けられ、前記ボンディング部及び前記ランド部を
露出して基板の両面がソルダレジストによって被覆さ
れ、前記基板の一方の面の前記ソルダレジストの被覆面
積と前記基板の他方の面の前記ソルダレジストの被覆面
積との比率が約１：１．３〜１：１．７であり、かつ、 前記基板の一方の面を被覆するソルダレジストの厚さと
前記基板の他方の面を被覆するソルダレジストの厚さと
の比率が３：１〜１．５：１の範囲であることを特徴と
する半導体装置用基板。1. A die attach portion on which a semiconductor element is mounted and a wiring pattern whose one end constitutes a bonding portion for electrically connecting to the semiconductor element are provided on one surface of the substrate, and the other surface of the substrate is provided. A land portion for providing an external connection terminal is provided to be electrically connected to the wiring pattern through a via, the bonding portion and the land portion are exposed, and both surfaces of the substrate are covered with a solder resist. The ratio of the solder resist coating area on one surface to the solder resist coating area on the other surface of the substrate is approximately 1: 1.3 to 1: 1.7, and one of the substrates The ratio of the thickness of the solder resist coating the surface of the substrate to the thickness of the solder resist coating the other surface of the substrate is in the range of 3: 1 to 1.5: 1.
被覆面積と前記基板の他方の面の前記ソルダレジストの
被覆面積との比率が約１：１．５であることを特徴とす
る請求項１記載の半導体装置用基板。2. A ratio of a coverage area of the solder resist on one surface of the substrate to a coverage area of the solder resist on the other surface of the substrate is about 1: 1.5. 1. The semiconductor device substrate according to 1.
近傍に設けられたことを特徴とする請求項１または２記
載の半導体装置用基板。3. The substrate for a semiconductor device according to claim 1, wherein a bonding portion is provided near the die attach portion.
るダイアタッチ部と一端が前記半導体素子と電気的に接
続するボンディング部を成す配線パターンとが設けら
れ、基板の他方の面に、外部接続端子を設けるためのラ
ンド部がビアを介して前記配線パターンと電気的に接続
して設けられ、前記ボンディング部及び前記ランド部を
露出して基板の両面がソルダレジストによって被覆され
た半導体装置用基板において、 前記ランド部が前記基板の一方の面を被覆するソルダレ
ジストの領域と対応する他方の面の領域に設けられ、前
記基板の他方の面を被覆するソルダレジストの領域が前
記基板の一方の面を被覆したソルダレジストの領域と対
応した領域であり、前記基板の一方の面のソルダレジス
トの厚さと他方の面のソルダレジストの厚さが略同一で
あることを特徴とする半導体装置用基板。4. A die attach portion on which a semiconductor element is mounted and a wiring pattern whose one end constitutes a bonding portion for electrically connecting to the semiconductor element are provided on one surface of the substrate, and the other surface of the substrate is provided. A semiconductor device in which a land portion for providing an external connection terminal is provided by being electrically connected to the wiring pattern through a via, and the bonding portion and the land portion are exposed and both surfaces of the substrate are covered with a solder resist. In the substrate for use, the land portion is provided in the area of the other surface corresponding to the area of the solder resist covering one surface of the substrate, and the area of the solder resist covering the other surface of the substrate is the area of the substrate. A region corresponding to the region of the solder resist covering one surface, the thickness of the solder resist on one surface of the substrate and the thickness of the solder resist on the other surface. Substrate for a semiconductor device which is characterized in that substantially the same.
トの領域が複数の独立した領域に分割されていることを
特徴とする請求項４記載の半導体装置用基板。5. The substrate for a semiconductor device according to claim 4, wherein a region of the solder resist covering one surface of the substrate is divided into a plurality of independent regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33044795A JP3370498B2 (en) | 1995-12-19 | 1995-12-19 | Substrate for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33044795A JP3370498B2 (en) | 1995-12-19 | 1995-12-19 | Substrate for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09172104A true JPH09172104A (en) | 1997-06-30 |
| JP3370498B2 JP3370498B2 (en) | 2003-01-27 |
Family
ID=18232726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33044795A Expired - Fee Related JP3370498B2 (en) | 1995-12-19 | 1995-12-19 | Substrate for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3370498B2 (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400672B1 (en) * | 1999-08-24 | 2003-10-08 | 앰코 테크놀로지 코리아 주식회사 | circuit board for semiconductor package |
| JP2008071912A (en) * | 2006-09-14 | 2008-03-27 | Matsushita Electric Ind Co Ltd | Resin wiring substrate and semiconductor device using it, and laminated semiconductor device |
| JPWO2006054637A1 (en) * | 2004-11-18 | 2008-05-29 | 松下電器産業株式会社 | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE |
| US7498522B2 (en) | 2006-01-30 | 2009-03-03 | Fujitsu Limited | Multilayer printed circuit board and manufacturing method thereof |
| JP2009194079A (en) * | 2008-02-13 | 2009-08-27 | Panasonic Corp | Wiring substrate for use in semiconductor apparatus, method for fabricating the same, and semiconductor apparatus using the same |
| JP2012019210A (en) * | 2010-07-09 | 2012-01-26 | Samsung Electro-Mechanics Co Ltd | Semiconductor package substrate and manufacturing method thereof |
| CN104022085A (en) * | 2013-03-01 | 2014-09-03 | 超威半导体(上海)有限公司 | Substrate |
| FR3009475A1 (en) * | 2013-07-30 | 2015-02-06 | St Microelectronics Grenoble 2 | ELECTRONIC DEVICE COMPRISING A SUBSTRATE PLATE PROVIDED WITH A LOCAL REINFORCING OR BALANCING LAYER |
| CN104661444A (en) * | 2015-02-16 | 2015-05-27 | 深圳华麟电路技术有限公司 | High-flatness rigid-flex board provided with ink windows shaped like dual nested rectangles and manufacturing method |
| JP2015162607A (en) * | 2014-02-27 | 2015-09-07 | 新光電気工業株式会社 | Wiring board, semiconductor device and wiring board manufacturing method |
| CN105451458A (en) * | 2014-08-19 | 2016-03-30 | 宁波舜宇光电信息有限公司 | Method for controlling trace deformation of rigid-flex board and PCB substrate semi-finished product |
-
1995
- 1995-12-19 JP JP33044795A patent/JP3370498B2/en not_active Expired - Fee Related
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400672B1 (en) * | 1999-08-24 | 2003-10-08 | 앰코 테크놀로지 코리아 주식회사 | circuit board for semiconductor package |
| US8071881B2 (en) | 2004-11-18 | 2011-12-06 | Panasonic Corporation | Wiring board, method for manufacturing same and semiconductor device |
| JPWO2006054637A1 (en) * | 2004-11-18 | 2008-05-29 | 松下電器産業株式会社 | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE |
| JP4661787B2 (en) * | 2004-11-18 | 2011-03-30 | パナソニック株式会社 | Wiring board and manufacturing method thereof |
| US7498522B2 (en) | 2006-01-30 | 2009-03-03 | Fujitsu Limited | Multilayer printed circuit board and manufacturing method thereof |
| JP2008071912A (en) * | 2006-09-14 | 2008-03-27 | Matsushita Electric Ind Co Ltd | Resin wiring substrate and semiconductor device using it, and laminated semiconductor device |
| US7816783B2 (en) | 2006-09-14 | 2010-10-19 | Panasonic Corporation | Resin wiring substrate, and semiconductor device and laminated semiconductor device using the same |
| JP2009194079A (en) * | 2008-02-13 | 2009-08-27 | Panasonic Corp | Wiring substrate for use in semiconductor apparatus, method for fabricating the same, and semiconductor apparatus using the same |
| US8067698B2 (en) | 2008-02-13 | 2011-11-29 | Panasonic Corporation | Wiring substrate for use in semiconductor apparatus, method for fabricating the same, and semiconductor apparatus using the same |
| JP2012019210A (en) * | 2010-07-09 | 2012-01-26 | Samsung Electro-Mechanics Co Ltd | Semiconductor package substrate and manufacturing method thereof |
| CN104022085A (en) * | 2013-03-01 | 2014-09-03 | 超威半导体(上海)有限公司 | Substrate |
| FR3009475A1 (en) * | 2013-07-30 | 2015-02-06 | St Microelectronics Grenoble 2 | ELECTRONIC DEVICE COMPRISING A SUBSTRATE PLATE PROVIDED WITH A LOCAL REINFORCING OR BALANCING LAYER |
| US9420685B2 (en) | 2013-07-30 | 2016-08-16 | Stmicroelectronics (Grenoble 2) Sas | Electronic device comprising a substrate board equipped with a local reinforcing or balancing layer |
| JP2015162607A (en) * | 2014-02-27 | 2015-09-07 | 新光電気工業株式会社 | Wiring board, semiconductor device and wiring board manufacturing method |
| CN105451458A (en) * | 2014-08-19 | 2016-03-30 | 宁波舜宇光电信息有限公司 | Method for controlling trace deformation of rigid-flex board and PCB substrate semi-finished product |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP3370498B2 (en) | 2003-01-27 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |