JP2947563B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device technology, for example, a technology effective when applied to a semiconductor device using a plastic package substrate to which a printed wiring board technology is applied. .

[Conventional technology]

For example, regarding plastic package substrates, see Nikkei McGraw-Hill, Nikkei Electronics Supplement No.2.
Micro Devices, June 11, 1984 ", p. 129 to p. 168, comparing plastic package substrates with ceramic substrates, LCC using plastic package substrates
(Leadless Chip carrier) and PGA (Pin Grid Packa)
ge), and a method of manufacturing a plastic package substrate and the like are described in detail.

A general semiconductor device having a plastic package substrate will be described with reference to FIG.

Package substrate 50 made of high heat resistant plastic material
A wiring 51 made of copper or the like is formed in a complex pattern radially from the center of the upper surface along the outer peripheral direction.

In the center of the upper surface of the package substrate 50, copper (Cu)
A rectangular chip mounting portion 52 plated with nickel (Ni) -gold (Au) is patterned on the surface of the foil, and a semiconductor chip 53 on which a predetermined integrated circuit is formed is formed above the rectangular chip mounting portion 52.
Has been implemented.

On the upper surface of the package substrate 50, a hard protective film 54 made of a polyimide resin or the like is deposited from the viewpoint of moisture resistance, insulation between adjacent wires, or protection of the wires 51 from mechanical shock. However, the center is opened in a rectangular shape, and one end of the wiring 51 and the semiconductor chip 53 are exposed. Then, one end of the wiring 51 and the semiconductor chip 53 are electrically connected via a bonding wire 55.

One end of the wiring 51 exposed from the protective film 54 is subjected to Ni-Au plating in order from the lower layer from the viewpoint of corrosion prevention and connectivity with the bonding wire 55.

[Problems to be solved by the invention]

However, in the above-described conventional technology, for example, during a thermal history test, composite thermal stress from the protective film and metal plating concentrates on a wiring portion located at a boundary between the protective film covering region and the opening region. The present inventor has found that there is a problem that the wiring is deteriorated in that portion, and furthermore, there is a problem of disconnection.

Such a problem also occurs in a printed wiring board or the like on which electronic components such as resistors and capacitors and semiconductor electronic components such as a package containing a semiconductor chip are mounted.

Further, such a problem becomes more and more prominent with miniaturization of wiring.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of improving the life of wiring formed on a wiring board.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of the specification and the accompanying drawings.

[Means for Solving the Problems] Of the inventions disclosed in the present application, the outline of a representative one will be briefly described as follows.

That is, a semiconductor chip mounted on a hard printed wiring board, and a wiring pattern formed on the hard printed wiring board and electrically connected to the semiconductor chip,
A semiconductor device having a protective film formed on the hard printed wiring board and covering a part of the wiring, wherein the protection is mainly performed on a wiring portion in a boundary region between a covering region of the protective film and an opening region. In order to disperse the stress applied from the film itself, at least the line length of the boundary line of the protective film, which is in contact with the wiring, is extended, and the wiring portion in the region of the extended boundary line is separated from the other. The wiring is locally wider than the wiring portion, and the position of the wide portion of the wiring is shifted between adjacent wirings.

[Action]

According to the above-described first means, the durability of the wiring near the boundary line is improved, so that the life of the wiring can be improved even for finer wiring.

Embodiment 1 FIG. 1 is an enlarged plan view of a principal part of a package substrate showing a vicinity of a boundary between a covering region of a protective film formed on a package substrate and an opening region of a semiconductor device according to an embodiment of the present invention. Figure,
FIG. 2 is a partially enlarged plan view of the package substrate showing an opening shape of a protective film above the through hole of the package substrate, FIG. 3 is an overall plan view of the package substrate of the semiconductor device, and FIG. 5 (a) to 5 (c) are cross-sectional views of a main part of the package substrate showing a manufacturing process of the package substrate of the semiconductor device, and FIG. 6 (a) is a mask portion used for manufacturing the package substrate. FIG. 6B is an enlarged partial plan view of this mask.

The structure of the semiconductor device of the first embodiment will be described with reference to FIGS.

The semiconductor device of the first embodiment shown in FIG. 4 has a package substrate (hereinafter, referred to as a substrate) 1a which is a printed wiring board.
Is a PGA made of a plastic material such as a high heat-resistant glass epoxy resin.

In the center of the upper surface of the substrate 1a, for example, Ni-Au
A plated rectangular chip mounting portion 2 is formed, and on the upper surface thereof, for example, a semiconductor chip 3 having a gate array is bonded with an adhesive made of a low-stress resin containing a filler having high thermal conductivity. (Not shown).

At the periphery of the upper surface of the substrate 1a, for example, 208 through-holes 4a, which conduct between the upper surface and the back surface of the substrate 1a, are opened, and each of the through-holes 4a is caulked and soldered. The output pin 5 protrudes downward from the back surface of the substrate 1a.

On the upper surface of the substrate 1a, a plurality of wirings 6a made of copper (Cu) or the like are provided.
Are formed radially from the outer periphery of the chip mounting portion 2 along the outer peripheral direction of the substrate 1a, and a protective film 7 made of, for example, an epoxy-based thermosetting resin is deposited so as to cover these wirings 6a. However, a hole is opened in the center thereof, and one end of the wiring 6a and the semiconductor chip 3 are exposed.

In FIG. 3, a solid line A shown on the outer periphery of the chip mounting portion 2 indicates a boundary between the covering region of the protective film 7 covering the upper surface of the substrate 1a and the opening region.

Note that, as shown in FIG. 2, the protective film 7 is also opened above the through hole 4a. This is because Ni-Au plating (not shown) is applied to the upper part of the through hole 4a after the input / output pin 5 is inserted into the through hole 4a.

Although not shown, the surface of one end of the wiring 6a exposed from the protective film 7 is plated with Ni-Au. One end of the wiring 6a is electrically connected to the semiconductor chip 3 via a bonding wire 8 made of Cu, Au, or the like.

The other end of the wiring 6a is electrically connected to the input / output 5 via the through hole 4a.

A dam 9 made of aluminum (Al) or the like covered with aluminum oxide (Al ₂ O ₃ ) is provided on the upper surface of the protective film 7.
Are joined by a silicon-based adhesive (not shown).

The inside of the dam 9 is filled with an amount of silicon gel 10 that sufficiently covers the semiconductor chip 3 and the bonding wires 8.

A cap 11 made of Al or the like is joined to the upper part of the dam 9 with a silicon-based adhesive (not shown).

A metal plate 12 made of Cu or the like is formed below the semiconductor chip 3 and on the back surface of the substrate 1a in order to improve heat dissipation.

Next, referring to FIG. 1, the boundary between the covering region of the protective film 7 and the opening region will be described. In FIG. 1, a plurality of quadrangular regions formed at predetermined intervals along one side of the semiconductor chip 3 indicate bonding pads BP, and bonding wires 8 for connecting the bonding pads BP to the wirings 6a.
(See FIG. 4) is not shown to make the drawing easier to see.

In the first embodiment, the planar shape of the boundary line between the covering region of the protective film 7 and the opening region is uneven.

In a portion of the boundary line of the protective film 7 which is in contact with the wiring 6a, a concave portion 7a whose width gradually decreases toward the extending direction of the wiring 6a and the covering region of the protective film 7 is formed.

That is, conventionally, the boundary line of the protective film intersects linearly with the extending direction of the wiring, but in the first embodiment, the boundary line of the protective film 7 is located at a portion in contact with the wiring 6a. Recess
Due to the formation of 7a, the length of the boundary line at that portion is extended as compared with the conventional case, and the stress applied to this portion of the wiring 6a is dispersed.

An example of manufacturing such a substrate 1a will be described with reference to FIGS. 5 (a) to 5 (c) and FIGS. 6 (a) and 6 (b).

First, for example, 208 through holes 4a (see FIG. 4) are formed in predetermined portions of the substrate 1a on which the thin film 13 made of Cu or the like is formed on the upper and lower surfaces. A pattern 14 (hereinafter referred to as a resist) is formed (FIG. 5A).

Next, using the resist pattern 14 as a mask, the thin film 13 in a portion without the resist pattern 14 is removed by etching.
The chip mounting portion 2, the wiring 6a, and the metal plate 12 are patterned on the surface of 1a (FIG. 5 (b)).

Thereafter, the surface of the substrate 1a on which the chip mounting portion 2 and the wiring 6a are formed is opposed to the surface of the metal mask 15a to which the shielding plate 16a is joined.
Automatically align with a.

FIG. 6A shows a unit portion forming one substrate 1a of the metal mask 15a. A shielding plate 16a is joined to the opening area of the protective film 7, and A resin transmission net 17 is formed.

In the first embodiment, in order to make the plane shape of the boundary line between the covering region of the protective film 7 and the opening region irregular as described above, the four sides of the shielding plate 16a are formed as shown in FIG. A plurality of uneven patterns as shown are formed.

After the alignment of the metal mask 15a, an epoxy thermosetting resin solution is deposited on the substrate 1a via the metal mask 15a.

Then, the resin solution is heated at, for example, about 130 ° C. for 20 minutes or more to cure the resin solution.
a Protective film 7 to which the planar shape of the four sides is transferred is formed (fifth
Figure (c).

Thereafter, although not shown, Ni-Au plating is applied to the exposed portion of the wiring 6a and the inner wall of the through hole 4a, and the input / output pins 5 are inserted into the through hole 4a to manufacture the above-described substrate 1a.

As described above, according to the first embodiment, since the concave portion 7a is formed in the portion in contact with the wiring 6a in the boundary line between the covering region of the protective film 7 and the opening region, the line length of the boundary line in the portion is conventionally smaller. Since the stress applied to this portion of the wiring 6a is extended as compared with the above, the wiring portion near the boundary is prevented from deteriorating, and the life of the wiring 6a can be greatly improved.

As a result, for example, it is possible to prevent disconnection of the wiring 6a during the thermal history test.

Second Embodiment FIG. 7 is a package showing a planar shape of a wiring near a boundary between a covering region of a protective film formed on a package substrate and an opening region of a semiconductor device according to another embodiment of the present invention. It is a principal part enlarged plan view of a board | substrate.

In the second embodiment, as shown in FIG. 7, the boundary between the covering region of the protective film 7 and the opening region intersects linearly with the extending direction of the wiring 6b as in the related art. However, the width of the wiring 6b in the vicinity of the boundary of the protective film 7 is locally wider than the wiring portions other than this portion.

As described above, according to the second embodiment, the strength of the wiring portion near the boundary between the covering region of the protective film 7 and the opening region is maintained, and the resistance to the stress applied to this portion is secured. Is greatly improved, and for example, disconnection of the wiring 6b during a thermal history test can be prevented.

[Embodiment 3] Fig. 8 is a plan view of a protective film and wiring near a boundary between a covering region of a protective film and an opening region formed on a package substrate of a semiconductor device according to still another embodiment of the present invention. FIG. 9 is a plan view of a main part of a package substrate showing a shape, and FIG.
FIG. 2 is a partially enlarged plan view of a mask used for manufacturing the package substrate shown in FIG.

In the second embodiment, when the distance between the wirings 6b is reduced, the distance is determined by the wide portion formed in each wiring 6b. Therefore, even if the wiring 6b is miniaturized, the distance between the wirings 6b is further reduced. In some cases, the width cannot be reduced.

Therefore, in the third embodiment, as shown in FIG. 8, the position of the wide portion of the other wiring 6c is shifted in the direction in which the wiring 6c extends from the wide portion of the adjacent one wiring 6c. Are arranged.

Then, of the boundary between the covering region of the protective film 7 and the opening region, a portion in contact with the wiring 6c is located at a wide portion of each wiring 6c. As a result, since the line length of the portion of the boundary line of the protective film 7 that is in contact with the wiring 6c is extended as compared with the related art, the wiring portion near the boundary line is extended as in the case of the first embodiment. The applied stress is dispersed.

In addition, in order to form the shape of the boundary line of the protective film 7 in the third embodiment, for example, the pattern formed on the four sides of the shielding plate 16b is transferred by using a metal mask 15b shown in FIG. .

As described above, according to the third embodiment, the wide portions of the adjacent wirings 6c, 6c are arranged so as to be shifted from each other in the direction in which the wiring 6c extends. The distance between the wirings 6b, 6b described in the second embodiment can be made smaller.

In addition, the strength of the wiring portion in the vicinity of the boundary between the covering region of the protective film 7 and the opening region is maintained, and the line length of the portion of the boundary that is in contact with the wiring 6c is extended as compared with the related art. Since the stress applied to the part is dispersed, the wiring 6c
Can be greatly improved.

As a result, compared to only the case where the line length of the portion in contact with the wiring 6c of the boundary line is extended or the case where the wiring portion near the boundary line is locally widened, the tolerance of the wiring at the boundary line portion is reduced. Therefore, even in a substrate having finer wiring, the life of the wiring can be significantly improved.

Embodiment 4 FIG. 10 is a perspective view of a main part of a printed wiring board according to an embodiment of the present invention, and FIG. 11 is a boundary line between a covering area of a protective film formed on the printed wiring board and an opening area. FIG. 4 is an enlarged plan view of a main part of the printed wiring board showing the vicinity.

The wiring board according to the fourth embodiment shown in FIG. 10 is a multilayer printed wiring board (hereinafter, referred to as a printed board) on which electronic components such as capacitors and resistors and semiconductor electronic components such as a package containing a semiconductor chip are mounted. 1b.

The printed board 1b is made of glass epoxy resin or the like, and has six wiring layers made of Cu or the like.

At a predetermined position of the printed circuit board 1b, a through hole 4b that connects the upper surface and the back surface thereof is formed. On the upper and lower portions of the through hole 4b, lands 18 formed by applying metal plating to the surface of a copper foil are formed, and the upper and lower lands 18, 18 are made of Cu or the like provided on the inner wall of the through hole 4b. Is conducted through the metal plating.

Further, the through hole 4b is also connected to a predetermined wiring layer formed in an inner layer of the printed board 1b.

Although not shown, the above-described capacitor, resistor, or package lead is inserted into the through hole 4b.

The wiring layers on the upper and lower surfaces of the printed circuit board 1b
A pattern 6d is formed, and one end of the wiring 6d is connected to the land 18 of the through hole 4b.

The surface of the printed board 1b is covered with a protective film 7 so as to cover the wiring 6d, but the surfaces of the through holes 4b and the lands 18 are covered with the protective film 7 from the viewpoint of connectivity. Absent.

In the fourth embodiment, as shown in FIGS. 10 and 11, the line length of a portion of the boundary line which is in contact with the wiring 6d is longer than that of the related art, and the stress applied to the wiring portion near the boundary line is reduced. In addition to being dispersed, the wiring portion near the extended boundary line is wide.

In order to manufacture such a printed board 1b, it is manufactured by a normal printed wiring board manufacturing technique such as a subtractive method or a full additive method.

As described above, according to the fourth embodiment, of the boundary between the covering region of the protective film 7 and the opening region, the line length of the portion in contact with the wiring 6d is extended as compared with the related art, and the stress applied to this wiring portion is dispersed. At the same time, since the strength of the wiring portion near the boundary is maintained, the deterioration of the wiring portion can be prevented, and the life of the wiring 6d can be greatly improved.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even.

For example, in the first embodiment, in order to extend the line length of the portion in contact with the wiring in the boundary between the covering region of the protective film and the opening region, the width gradually decreases toward the covering region of the protective film 7. Although the case where such a concave portion is formed has been described, the present invention is not limited to this, and various changes can be made. As shown in FIG. 12, the wiring 6a extends in the direction in which the wiring 6a extends, Even if the recesses 7b having the same width are formed, a sufficient effect can be obtained.

In the second embodiment, the boundary of the protective film is
Although the case where the wiring is linear with respect to the direction in which the wiring is extended has been described, the present invention is not limited to this, and various changes can be made.
For example, as shown in FIG. 13, the line length of a portion of the boundary line that is in contact with the wiring 6e may be extended.

In this case, the resistance to the stress applied to that portion is improved as compared with the case where the wiring portion near the boundary line of the protective film is simply widened, so that the width of the wide portion of the wiring can be reduced accordingly. . As a result, the distance between adjacent wirings can be reduced.

Further, in the fourth embodiment, the case where the line length of the portion in contact with the wiring among the boundary lines is extended and the wiring portion near the boundary line of the protective film is widened, but the present invention is not limited to this. For example, as shown in FIG. 14, the effect can be obtained only by extending the line length of the portion in contact with the wiring 6e in the boundary of the protective film 7.

Further, in the first to fourth embodiments, the case where the protective film is made of an epoxy-based thermosetting resin has been described.
The present invention is not limited thereto, and may be variously modified. For example, an epoxy-based UV-curable resin, a polyimide-based thermosetting resin, or a polyimide-based UV-curable resin may be used.

In the first to third embodiments, the case where the present invention is applied to a package substrate on which a semiconductor chip is mounted has been described. However, the present invention is not limited to this. For example, a printed wiring board of a COB (Chip On Board) type in which the semiconductor chip is directly incorporated. Can be applied to

Further, in the first to third embodiments, the case where the substrate is applied to a glass epoxy resin having high heat resistance has been described. However, the present invention is not limited to this, and various applications are possible. For example, a plastic material such as a polyimide resin is also applied. be able to.

In the first to third embodiments, the case where the gate array is formed on the semiconductor chip has been described. However, the present invention is not limited to this, and various applications are possible. For example, a memory such as a semiconductor chip dynamic RAM or a static RAM may be used. Can also be applied to the case where is configured.

In the above description, the case where the invention made by the inventor is mainly applied to the PGA which is the field of application as the background has been described.However, the present invention is not limited to this, and various applications are possible. It can also be applied to devices.

〔The invention's effect〕

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

In other words, at least the line length of the boundary line between the cover region and the opening region of the protective film, which is in contact with the wiring, is extended, and the wiring portion near the extended boundary line is compared with the other wiring portions. By locally increasing the width, the stress applied to the wiring portion near the boundary line is dispersed, and the strength of the wiring portion near the boundary line is ensured. The wiring life can be improved even for fine wiring.

[Brief description of the drawings]

FIG. 1 is an enlarged plan view of an essential part of a package substrate showing a vicinity of a boundary between a cover region and a hole region of a protective film formed on a package substrate of a semiconductor device according to an embodiment of the present invention; Is a partially enlarged plan view of the package substrate showing an opening shape of the protective film above the through hole of the package substrate, FIG. 3 is an overall plan view of the package substrate of the semiconductor device, and FIG. 4 is a cross-sectional view of the semiconductor device. 5 (a) to 5 (c) are cross-sectional views of a main part of the package substrate showing a manufacturing process of the package substrate of the semiconductor device. FIG. 6 (a) is a partial plan view of a mask used for manufacturing the package substrate. FIG. 6 (b) is an enlarged partial plan view of this mask, and FIG. 7 is a boundary between a cover region and a hole region of a protective film formed on a package substrate of a semiconductor device according to another embodiment of the present invention. Wiring near the wire FIG. 8 is a plan view of a principal part of a package substrate showing a planar shape of FIG. 8. FIG. 8 is a boundary line between a covering region and a hole region of a protective film formed on a package substrate of a semiconductor device according to still another embodiment of the present invention. FIG. 9 is a plan view of a main part of a package substrate showing a planar shape of a protective film and wiring in the vicinity, FIG. 9 is a partially enlarged plan view of a mask used for manufacturing the package substrate shown in FIG. 8, and FIG. FIG. 11 is a perspective view of an essential part of an example of a printed wiring board, FIG. 11 is an enlarged plan view of an essential part of the printed wiring board showing the vicinity of a boundary between a covering region and an opening region of a protective film formed on the printed wiring board, FIG. 12 is an enlarged plan view of a main part of a package substrate showing a vicinity of a boundary between a covering region and an opening region of a protective film formed on a package substrate of a semiconductor device according to another embodiment of the present invention; Drawing shows still another embodiment of the present invention. FIG. 14 is an enlarged plan view of an essential part of the package substrate showing the planar shape of the protective film and the wiring near the boundary between the covering region and the opening region of the protective film formed on the package substrate of a certain semiconductor device; FIG. 15 is an enlarged plan view of a main part of a printed wiring board showing a vicinity of a boundary between a covering region of a protective film formed on the printed wiring board and an opening region according to another embodiment, and FIG. 15 includes a plastic package substrate. It is a partially cutaway perspective view of a general semiconductor device. 1a: Package board (printed wiring board), 1b: Printed board (wiring board), 2: Chip mounting part, 3 ...
Semiconductor chip, 4a, 4b: through hole, 5: input / output pin, 6a to 6f: wiring, 7: protective film, 7a, 7b: concave portion, 8: bonding wire, 9: dam, 10 ... silicon gel, 11 ... cap, 12 ... metal plate, 13 ... thin film, 14 ... resist pattern, 15a, 15b ... metal mask, 16a, 16b ... shielding plate, 17 ... resin transmission net, 18 ……
Land, BP ... Bonding pad, A ... Boundary, 50 ...
... Package board, 51 ... Wiring, 52 ... Chip mounting part,
53 ... semiconductor chip, 54 ... protective film, 55 ... bonding wire.

 ──────────────────────────────────────────────────の Continued on the front page (72) Koji Nakamura, Inventor 2326, Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Takashi Miwa 2326, Imai, Ome, Tokyo, Japan Device, Inc. Inside the development center (72) Atsushi Honda 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Toshihiro Tsuboi 5-2-1, Kamisumihoncho, Kodaira-shi, Tokyo・ S.I. Engineering Co., Ltd. (72) Inventor: Hiroshi Arai 145, Nakajima, Nanae-cho, Kameda-gun, Hokkaido Nichi-Hokukai Semiconductor Co., Ltd. (56) References JP-A-57-199228 (JP, A) JP-A-63-271997 (JP, A) JP-A-55-129472 (JP, U)

Claims (3)

(57) [Claims] A semiconductor chip mounted on a hard printed wiring board; a wiring pattern formed on the hard printed wiring board and electrically connected to the semiconductor chip;
A semiconductor device having a protective film formed on the hard printed wiring board and covering a part of the wiring, wherein the protection is mainly performed on a wiring portion in a boundary region between a covering region of the protective film and an opening region. In order to disperse the stress applied from the film itself, at least the line length of the boundary line of the protective film, which is in contact with the wiring, is extended, and the wiring portion in the region of the extended boundary line is separated from the other. A semiconductor device, which is locally wider than a wiring portion, and the position of the wide portion of the wiring is shifted between adjacent wirings. 2. The semiconductor device according to claim 1, wherein said semiconductor chip and said wiring are electrically connected through a bonding wire. 3. The semiconductor device according to claim 2, wherein a dam is provided on the protective film on the hard printed wiring board so as to surround the semiconductor chip, and the semiconductor chip is filled inside the dam. A semiconductor device comprising: a silicone gel that covers a wiring portion that is not covered with a bonding wire and a protective film; and a cap that is joined to an upper part of the dam and seals the semiconductor chip.