JPS61164076U - - Google Patents
Info
- Publication number
- JPS61164076U JPS61164076U JP4140686U JP4140686U JPS61164076U JP S61164076 U JPS61164076 U JP S61164076U JP 4140686 U JP4140686 U JP 4140686U JP 4140686 U JP4140686 U JP 4140686U JP S61164076 U JPS61164076 U JP S61164076U
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer film
- land
- upper layer
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005219 brazing Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 230000002265 prevention Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図及び第２図は従来の混成膜集積回路装置
を示す平面図、第３図は第２図に於ける主要部を
示す断面図、第４図はこの考案の混成膜集積回路
装置の一実施例を示す平面図である。
１……絶縁性基板上に形成された初段のベース
ランド、２……初段のエミツタランド、３……ア
ースランド、４……二段目のベースランド、５…
…二段目のエミツタランド、６……二段目のコレ
クタランド、７……抵抗パターン、８……初段の
トランジスタチツプ、９……二段目のトランジス
タチツプ、１０……初段のトランジスタチツプの
ベース電極とベースランドとを結ぶボンデイング
ワイヤ、１１……初段のトランジスタチツプのエ
ミツタ電極とエミツタランドとを結ぶボンデイン
グワイヤ、１２……二段目のトランジスタチツプ
のベース電極とベースランドとを結ぶボンデイン
グワイヤ、１３……二段目のトランジスタチツプ
のエミツタ電極とエミツタランドとを結ぶボンデ
イングワイヤ、１４……チツプコンデンサ、１５
……初段のエミツタランドに設けられたロウ材（
半田）の流れ防止用の溝、１６……二段目のベー
スランドに設けられたロウ材（ソルダー）の流れ
防止用の溝、１７……絶縁性基板、１８……膜回
路の下層膜、１９……半田、２０……初段のエミ
ツタランドに断続して設けられたロウ材（半田）
の流れ防止用の溝、２１……二段目のベースラン
ドに断続して設けられたロウ材（ソルダー）の流
れ防止用の溝。
1 and 2 are plan views showing a conventional hybrid film integrated circuit device, FIG. 3 is a sectional view showing the main parts of FIG. 2, and FIG. 4 is a plan view of a conventional hybrid film integrated circuit device. FIG. 2 is a plan view showing one embodiment. 1... First stage base land formed on an insulating substrate, 2... First stage emitter land, 3... Earth land, 4... Second stage base land, 5...
...Second stage emitter land, 6...Second stage collector land, 7...Resistance pattern, 8...First stage transistor chip, 9...Second stage transistor chip, 10...Base of first stage transistor chip Bonding wire connecting the electrode and base land, 11... Bonding wire connecting the emitter electrode of the first stage transistor chip and the emitter land, 12... Bonding wire connecting the base electrode of the second stage transistor chip and the base land, 13 ... Bonding wire connecting the emitter electrode of the second stage transistor chip and the emitter land, 14 ... Chip capacitor, 15
...The waxed wood installed in the first stage of Emitsuta Land (
Groove for preventing flow of solder (16)...Groove for preventing flow of brazing material (solder) provided on the second stage base land, 17...Insulating substrate, 18... Lower layer film of membrane circuit, 19...Solder, 20...Brazing material (solder) provided intermittently on the first emitter land
Groove for preventing flow of solder, 21...Groove for preventing flow of solder solder provided intermittently on the second stage base land.
Claims (1)
りも電気抵抗が高くロウ材となじまない下層膜を
含む多層膜回路を有し、前記上層膜の一部を除去
して下層膜を露出してなる抵抗パターンを有し、
前記上層膜上にロウ付けされた回路部品を有し、
前記ロウ付け部の近傍に前記上層膜を断続的に除
去して下層膜を露出せしめたロウ材の流れ防止部
を有することを特徴とする混成膜集積回路装置。 A multilayer film circuit is provided on an insulating substrate, including an upper layer film with a low electrical resistance and a lower layer film with a higher electrical resistance that is not compatible with the brazing material, and a part of the upper layer film is removed to expose the lower layer film. It has a resistance pattern of
having a circuit component brazed on the upper layer film,
A hybrid film integrated circuit device comprising a brazing material flow prevention part in which the upper film is intermittently removed to expose the lower film in the vicinity of the brazing part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4140686U JPS61164076U (en) | 1986-03-20 | 1986-03-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4140686U JPS61164076U (en) | 1986-03-20 | 1986-03-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61164076U true JPS61164076U (en) | 1986-10-11 |
Family
ID=30551200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4140686U Pending JPS61164076U (en) | 1986-03-20 | 1986-03-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61164076U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009206216A (en) * | 2008-02-26 | 2009-09-10 | Panasonic Electric Works Co Ltd | Light-emitting apparatus |
| WO2019187513A1 (en) * | 2018-03-29 | 2019-10-03 | 日本電気株式会社 | Electronic component |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS494156B1 (en) * | 1968-02-29 | 1974-01-30 | ||
| JPS5193762A (en) * | 1975-02-14 | 1976-08-17 | Sogosetsuzokutaino seizohoho |
-
1986
- 1986-03-20 JP JP4140686U patent/JPS61164076U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS494156B1 (en) * | 1968-02-29 | 1974-01-30 | ||
| JPS5193762A (en) * | 1975-02-14 | 1976-08-17 | Sogosetsuzokutaino seizohoho |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009206216A (en) * | 2008-02-26 | 2009-09-10 | Panasonic Electric Works Co Ltd | Light-emitting apparatus |
| WO2019187513A1 (en) * | 2018-03-29 | 2019-10-03 | 日本電気株式会社 | Electronic component |
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