JPH0252339U - - Google Patents

Info

Publication number
JPH0252339U
JPH0252339U JP12837688U JP12837688U JPH0252339U JP H0252339 U JPH0252339 U JP H0252339U JP 12837688 U JP12837688 U JP 12837688U JP 12837688 U JP12837688 U JP 12837688U JP H0252339 U JPH0252339 U JP H0252339U
Authority
JP
Japan
Prior art keywords
side bump
chip
bonded
substrate
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12837688U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12837688U priority Critical patent/JPH0252339U/ja
Publication of JPH0252339U publication Critical patent/JPH0252339U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案による配線基板の一実施例を示
す側面図、第2図及び第3図は従来の配線基板を
示す側面図である。 1……絶縁基板、2……配線パターン、3……
チツプ部品、4,10……接合部材、6……バン
プ、11,12……チツプ側、基板側バンプ、1
3……接合膜。
FIG. 1 is a side view showing an embodiment of a wiring board according to the present invention, and FIGS. 2 and 3 are side views showing a conventional wiring board. 1... Insulating board, 2... Wiring pattern, 3...
Chip parts, 4, 10... Joining member, 6... Bump, 11, 12... Chip side, board side bump, 1
3... Bonding film.

Claims (1)

【実用新案登録請求の範囲】 チツプ部品の電極に接合するチツプ側バンプと
、 配線パターンに接合する基板側バンプと、 上記チツプ側バンプ及び基板側バンプ間を接合
する異方性導電膜でなる接合膜と を有する接合部材によつて上記チツプ部品を上記
配線パターンに接合することを特徴とする配線基
板。
[Scope of Claim for Utility Model Registration] A bond consisting of a chip-side bump that is bonded to an electrode of a chip component, a substrate-side bump that is bonded to a wiring pattern, and an anisotropic conductive film that bonds between the chip-side bump and the substrate-side bump. A wiring board characterized in that the chip component is joined to the wiring pattern by a joining member having a film.
JP12837688U 1988-09-30 1988-09-30 Pending JPH0252339U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12837688U JPH0252339U (en) 1988-09-30 1988-09-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12837688U JPH0252339U (en) 1988-09-30 1988-09-30

Publications (1)

Publication Number Publication Date
JPH0252339U true JPH0252339U (en) 1990-04-16

Family

ID=31381660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12837688U Pending JPH0252339U (en) 1988-09-30 1988-09-30

Country Status (1)

Country Link
JP (1) JPH0252339U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998033217A1 (en) * 1997-01-24 1998-07-30 Rohm Co., Ltd. Semiconductor device and method for manufacturing thereof
JP2007294916A (en) * 2006-03-31 2007-11-08 Brother Ind Ltd Connecting structure, method of forming bump and the like

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998033217A1 (en) * 1997-01-24 1998-07-30 Rohm Co., Ltd. Semiconductor device and method for manufacturing thereof
JP2007294916A (en) * 2006-03-31 2007-11-08 Brother Ind Ltd Connecting structure, method of forming bump and the like

Similar Documents

Publication Publication Date Title
JPS5827935U (en) Hybrid integrated circuit device
JPH0252339U (en)
JPH0284368U (en)
JPS6237939U (en)
JPH0236476U (en)
JPH01125544U (en)
JPS6153934U (en)
JPS6413144U (en)
JPH01133734U (en)
JPH0334240U (en)
JPH0265339U (en)
JPH0422244U (en)
JPS6245837U (en)
JPH0211342U (en)
JPH02114934U (en)
JPH0343738U (en)
JPS62149870U (en)
JPS63157934U (en)
JPS61153373U (en)
JPH0254234U (en)
JPS6263936U (en)
JPS61182048U (en)
JPS6234431U (en)
JPH0286133U (en)
JPS6063970U (en) Chip component mounting structure