JPH01133734U - - Google Patents
Info
- Publication number
- JPH01133734U JPH01133734U JP1988029385U JP2938588U JPH01133734U JP H01133734 U JPH01133734 U JP H01133734U JP 1988029385 U JP1988029385 U JP 1988029385U JP 2938588 U JP2938588 U JP 2938588U JP H01133734 U JPH01133734 U JP H01133734U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wire bonding
- substrate
- bonding pads
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Description
第１図は本考案の実施例に係る半導体チツプ実
装用基板の平面図、第２図は第１図のＸ―Ｘ線矢
視断面図、第３図は従来の半導体チツプ実装用基
板の平面図、第４図及び第５図は第３図のワイヤ
ボンデイングパツド部の拡大図である。
１，１１；基板、２；半導体チツプ、３，１２
；ワイヤボンデイングパツド、４；半導体チツプ
パツド、５；第１ボンド点、６；第２ボンド点、
７；ワイヤ、８；短辺、９；ステツチ、１０；長
辺、Ｌ；第１ボンド点と第２ボンド点を結ぶ線、
Ｖ，Ｗ；ワイヤが片寄る方向。
Fig. 1 is a plan view of a semiconductor chip mounting board according to an embodiment of the present invention, Fig. 2 is a cross-sectional view taken along the line X--X of Fig. 1, and Fig. 3 is a plan view of a conventional semiconductor chip mounting board. 4 and 5 are enlarged views of the wire bonding pad portion of FIG. 3. 1, 11; Substrate, 2; Semiconductor chip, 3, 12
wire bonding pad, 4; semiconductor chip pad, 5; first bond point, 6; second bond point,
7; Wire, 8; Short side, 9; Stitch, 10; Long side, L; Line connecting the first bond point and the second bond point,
V, W: direction in which the wire is biased.
Claims (1)
ボンデイングパツドを配設してなる半導体チツプ
実装用基板において、前記各ワイヤボンデイング
パツドは、その長辺が当該パツドとこれに対応す
る半導体チツプのパツドとを結ぶ線と平行となる
ように配置されたことを特徴とする半導体チツプ
実装用基板。 In a semiconductor chip mounting board in which rectangular wire bonding pads are arranged around a mounting position of a semiconductor chip, each of the wire bonding pads has a long side that is connected to the corresponding pad of the semiconductor chip. 1. A substrate for mounting a semiconductor chip, characterized in that the substrate is arranged parallel to a line connecting the two.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988029385U JPH01133734U (en) | 1988-03-04 | 1988-03-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988029385U JPH01133734U (en) | 1988-03-04 | 1988-03-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01133734U true JPH01133734U (en) | 1989-09-12 |
Family
ID=31253552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988029385U Pending JPH01133734U (en) | 1988-03-04 | 1988-03-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01133734U (en) |
-
1988
- 1988-03-04 JP JP1988029385U patent/JPH01133734U/ja active Pending