JPS63182546U - - Google Patents
Info
- Publication number
- JPS63182546U JPS63182546U JP7316387U JP7316387U JPS63182546U JP S63182546 U JPS63182546 U JP S63182546U JP 7316387 U JP7316387 U JP 7316387U JP 7316387 U JP7316387 U JP 7316387U JP S63182546 U JPS63182546 U JP S63182546U
- Authority
- JP
- Japan
- Prior art keywords
- region
- lead
- chips
- fixing
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案による半導体装置の平面図、第
２図は従来の半導体装置の平面図である。
１は半導体装置、２，３，４は第１乃至第３の
チツプ、５，６，７，８は第１乃至第４のリード
、９，１０，１１は第１乃至第３の固着領域、１
２は引出し領域、１３，１４は第１および第２の
シヨツトキ接合領域、１５，１６は第１および第
２領域、１７，１８，１９，２０は金属細線であ
る。
FIG. 1 is a plan view of a semiconductor device according to the present invention, and FIG. 2 is a plan view of a conventional semiconductor device. 1 is a semiconductor device; 2, 3, and 4 are first to third chips; 5, 6, 7, and 8 are first to fourth leads; 9, 10, and 11 are first to third fixing regions; 1
2 is a lead-out area, 13 and 14 are first and second shot joint areas, 15 and 16 are first and second areas, and 17, 18, 19, and 20 are thin metal wires.
Claims (1)
のチツプと、１つのシヨツトキ接合を夫々有する
第２および第３のチツプと、前記第１のチツプを
固着するリードより導出した第１の固着領域と、
前記第２および第３のチツプを夫々固着し更に他
領域より電気的に接合するための第１および第２
領域を夫々有するリードより導出した第２および
第３の固着領域と、この第２および第３の固着領
域と前記第１の固着領域との間に設けられリード
より導出した引出し領域と、前記第１および第２
のシヨツトキ接合領域より第２および第３の固着
領域に有する前記第１および第２領域に夫々電気
的に接合する第１および第２の接合手段と、前記
第２および第３のチツプと前記リードより導出し
た引出し領域とを電気的に接合する第３および第
４の接合手段とを具備することを特徴とした半導
体装置。 a first having first and second shot joints;
a chip, second and third chips each having one shot joint, and a first fixing region derived from a lead fixing the first chip;
first and second chips for fixing the second and third chips, respectively, and for electrically connecting them from other regions;
a second and third fixed region led out from the lead each having a region; a lead-out region provided between the second and third fixed region and the first fixed region and led out from the lead; 1st and 2nd
first and second bonding means electrically bonding to the first and second regions, respectively, from the shot bonding region to the second and third fixing regions; and the second and third chips and the leads. A semiconductor device comprising third and fourth bonding means for electrically bonding a lead-out region led out from the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7316387U JPS63182546U (en) | 1987-05-15 | 1987-05-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7316387U JPS63182546U (en) | 1987-05-15 | 1987-05-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63182546U true JPS63182546U (en) | 1988-11-24 |
Family
ID=30917251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7316387U Pending JPS63182546U (en) | 1987-05-15 | 1987-05-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63182546U (en) |
-
1987
- 1987-05-15 JP JP7316387U patent/JPS63182546U/ja active Pending
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