JPH0459950U - - Google Patents

Info

Publication number
JPH0459950U
JPH0459950U JP1990102440U JP10244090U JPH0459950U JP H0459950 U JPH0459950 U JP H0459950U JP 1990102440 U JP1990102440 U JP 1990102440U JP 10244090 U JP10244090 U JP 10244090U JP H0459950 U JPH0459950 U JP H0459950U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
heat sink
adhesive
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990102440U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990102440U priority Critical patent/JPH0459950U/ja
Publication of JPH0459950U publication Critical patent/JPH0459950U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａ〜ｄはこの考案の一実施例である混成
集積回路装置の各製造工程を示す斜視図、平面図
および断面図、第２図ａ〜ｆは従来の混成集積回
路装置の各製造工程および不工合を説明する斜視
図、断面図である。 図において、１はヒートシンク、１ａは突起部
、２は基板、２ａは基板電極、２ｂは搭載部品、
３は接着剤、４はリード線、５は半田、６はワイ
ヤーを示す。なお、図中、同一符号は同一、また
は相当部分を示す。 Figures 1a to d are perspective views, plan views, and sectional views showing each manufacturing process of a hybrid integrated circuit device that is an embodiment of this invention, and Figures 2a to f are each manufacturing process of a conventional hybrid integrated circuit device. FIG. 2 is a perspective view and a cross-sectional view illustrating a process and defects. In the figure, 1 is a heat sink, 1a is a protrusion, 2 is a substrate, 2a is a substrate electrode, 2b is a mounting component,
3 indicates an adhesive, 4 a lead wire, 5 a solder, and 6 a wire. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板を接着剤にてヒートシンクに接着する構造
の混成集積回路装置において、前記接着剤の厚み
を均一にするため前記ヒートシンクの前記基板接
着面に３個以上の突起を設けたことを特徴とする
混成集積回路装置。 A hybrid integrated circuit device having a structure in which a substrate is bonded to a heat sink with an adhesive, characterized in that three or more protrusions are provided on the substrate bonding surface of the heat sink in order to make the thickness of the adhesive uniform. Integrated circuit device.
JP1990102440U 1990-09-28 1990-09-28 Pending JPH0459950U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990102440U JPH0459950U (en) 1990-09-28 1990-09-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990102440U JPH0459950U (en) 1990-09-28 1990-09-28

Publications (1)

Publication Number Publication Date
JPH0459950U true JPH0459950U (en) 1992-05-22

Family

ID=31846698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990102440U Pending JPH0459950U (en) 1990-09-28 1990-09-28

Country Status (1)

Country Link
JP (1) JPH0459950U (en)

Similar Documents

Publication Publication Date Title
JPH0459950U (en)
JPH031540U (en)
JPH0187547U (en)
JPS6413144U (en)
JPS58120662U (en) Chippukiyariya
JPS6296848U (en)
JPS63149546U (en)
JPH01130592U (en)
JPH0268451U (en)
JPS63187330U (en)
JPS62126836U (en)
JPS6263936U (en)
JPS6413145U (en)
JPH02122477U (en)
JPH02148569U (en)
JPH01125544U (en)
JPH0263548U (en)
JPH0470738U (en)
JPS62172101U (en)
JPS61102049U (en)
JPS62204327U (en)
JPH0162666U (en)
JPS59171350U (en) Semiconductor element mounting structure
JPH03122548U (en)
JPS59192851U (en) semiconductor equipment