JPH0263548U - - Google Patents
Info
- Publication number
- JPH0263548U JPH0263548U JP14365388U JP14365388U JPH0263548U JP H0263548 U JPH0263548 U JP H0263548U JP 14365388 U JP14365388 U JP 14365388U JP 14365388 U JP14365388 U JP 14365388U JP H0263548 U JPH0263548 U JP H0263548U
- Authority
- JP
- Japan
- Prior art keywords
- die
- bonded
- heat sink
- thick film
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
第１図ａ，ｂおよび第２図ａ，ｂはこの考案の
実施例をそれぞれ示す図で、各ａ図はダイスがヒ
ートシンクにダイボンドされた状態を示す上面図
、各ｂは厚膜混成集積回路装置の側面図、第３図
ａ，ｂは従来例を示す第１図、第２図と同様な上
面図および側面図である。
図において、１はダイス、２はヒートシンク、
３は絶縁性基板、４は導体ペースト、５はボンデ
イングワイヤ、６は半田である。なお、各図中の
同一符号は同一または相当部分を示す。
Figures 1a and 2b and 2a and 2b are diagrams showing embodiments of this invention, respectively, where each figure a is a top view showing a state in which the die is die-bonded to a heat sink, and each figure b is a thick film hybrid integrated circuit. A side view of the device, FIGS. 3a and 3b, are a top view and a side view similar to FIGS. 1 and 2, showing a conventional example. In the figure, 1 is a die, 2 is a heat sink,
3 is an insulating substrate, 4 is a conductive paste, 5 is a bonding wire, and 6 is a solder. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
スがダイボンドされたヒートシンクが固定され、
所要のワイヤボンデイングが施された構造の厚膜
混成集積回路において、前記ダイスがダイボンド
される前記ヒートシンク面に、階段上の段差を形
成し、この階段状の段差の低い方の面に前記ダイ
スをダイボンドするか、または前記ダイスとボン
デイング領域との間に所要幅の溝を形成して前記
ダイスをダイボンドしたことを特徴とする厚膜混
成集積回路装置。 A heat sink with a die bonded to it is fixed on an insulating substrate with a circuit formed on its surface.
In a thick film hybrid integrated circuit having a structure in which required wire bonding is performed, a step-like step is formed on the heat sink surface to which the die is die-bonded, and the die is placed on the lower side of the step-like step. A thick film hybrid integrated circuit device characterized in that the die is die-bonded, or the die is die-bonded by forming a groove of a required width between the die and the bonding region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14365388U JPH0263548U (en) | 1988-11-02 | 1988-11-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14365388U JPH0263548U (en) | 1988-11-02 | 1988-11-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0263548U true JPH0263548U (en) | 1990-05-11 |
Family
ID=31410665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14365388U Pending JPH0263548U (en) | 1988-11-02 | 1988-11-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0263548U (en) |
-
1988
- 1988-11-02 JP JP14365388U patent/JPH0263548U/ja active Pending