JPH0281043U - - Google Patents

Info

Publication number
JPH0281043U
JPH0281043U JP15943288U JP15943288U JPH0281043U JP H0281043 U JPH0281043 U JP H0281043U JP 15943288 U JP15943288 U JP 15943288U JP 15943288 U JP15943288 U JP 15943288U JP H0281043 U JPH0281043 U JP H0281043U
Authority
JP
Japan
Prior art keywords
lid
chip
frame
lead
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15943288U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15943288U priority Critical patent/JPH0281043U/ja
Publication of JPH0281043U publication Critical patent/JPH0281043U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の半導体パツケージ構造の実施
例を示す断面図、第2図はPGAタイプの他の実
施例を示す断面図、第3図は従来例を示す断面図
である。 図において、1はフレーム、3はICチツプ、
4はリツド、5,5′はリード、10はvia、
10′は導体パターンである。
FIG. 1 is a sectional view showing an embodiment of the semiconductor package structure of the present invention, FIG. 2 is a sectional view showing another embodiment of the PGA type, and FIG. 3 is a sectional view showing a conventional example. In the figure, 1 is a frame, 3 is an IC chip,
4 is lid, 5 and 5' are leads, 10 is via,
10' is a conductor pattern.

Claims (1)

【実用新案登録請求の範囲】 ICチツプ3等を有するフレーム1の下に、そ
れと同一寸法でセラミツクから成るリツド4を該
ICチツプ3等を封止するように接合し、 該リツド4の下面にリード5又は5′を取付け
、リツド4の内部にリード5又は5〓に接続する
導体パターン10又は10′を形成することを特
徴とする半導体パツケージ構造。
[Claims for Utility Model Registration] A lid 4 made of ceramic and having the same dimensions as the frame 1 is bonded to the bottom of the frame 1 having the IC chip 3 etc. so as to seal the IC chip 3 etc., and the lower surface of the lid 4 is A semiconductor package structure characterized in that a lead 5 or 5' is attached and a conductive pattern 10 or 10' is formed inside the lid 4 to connect to the lead 5 or 5'.
JP15943288U 1988-12-09 1988-12-09 Pending JPH0281043U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15943288U JPH0281043U (en) 1988-12-09 1988-12-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15943288U JPH0281043U (en) 1988-12-09 1988-12-09

Publications (1)

Publication Number Publication Date
JPH0281043U true JPH0281043U (en) 1990-06-22

Family

ID=31440643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15943288U Pending JPH0281043U (en) 1988-12-09 1988-12-09

Country Status (1)

Country Link
JP (1) JPH0281043U (en)

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