JPH01173946U - - Google Patents
Info
- Publication number
- JPH01173946U JPH01173946U JP6793988U JP6793988U JPH01173946U JP H01173946 U JPH01173946 U JP H01173946U JP 6793988 U JP6793988 U JP 6793988U JP 6793988 U JP6793988 U JP 6793988U JP H01173946 U JPH01173946 U JP H01173946U
- Authority
- JP
- Japan
- Prior art keywords
- chamfered
- electronic component
- carrier type
- chip carrier
- lower corner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図は本考案の実施例を示すリードレスチツ
プキヤリア型ＩＣの断面図、第２図は本考案のリ
ードレスチツプキヤリア型ＩＣの電極部の応力を
示す図、第３図は従来のリードレスチツプキヤリ
ア型ＩＣの外観図、第４図はその断面図、第５図
は従来のリードレスチツプキヤリア型ＩＣの実装
断面図、第６図は従来のセラミツクチツプキヤリ
アの製造工程図、第７図は従来のリードレスチツ
プキヤリア型ＩＣの電極部の形状を示す断面図、
第８図は従来のリードレスチツプキヤリア型ＩＣ
の電極部の応力を示す図である。
２１……リードレスチツプキヤリア型ＩＣ、２
２……セラミツクチツプキヤリア、２３……ＩＣ
チツプ、２４……金線又はアルミ線、２５……電
極、２６……キヤツプ。
Figure 1 is a cross-sectional view of a leadless chip carrier type IC showing an embodiment of the present invention, Figure 2 is a diagram showing stress in the electrode portion of the leadless chip carrier type IC of the present invention, and Figure 3 is a diagram showing the stress of the leadless chip carrier type IC of the present invention. 4 is a cross-sectional view of a leadless chip carrier type IC, FIG. 5 is a cross-sectional view of a conventional leadless chip carrier type IC, FIG. 6 is a manufacturing process diagram of a conventional ceramic chip carrier type IC, and FIG. The figure is a cross-sectional view showing the shape of the electrode part of a conventional leadless chip carrier type IC.
Figure 8 shows a conventional leadless chip carrier type IC.
It is a figure which shows the stress of the electrode part of. 21...Leadless chip carrier type IC, 2
2...Ceramic chippukiyaria, 23...IC
Chip, 24...gold wire or aluminum wire, 25...electrode, 26...cap.
Claims (1)
ス電子部品において、 前記下部角部の面取り加工を行い、前記側面、
面取り部及び下面に連続した電極を形成すること
を特徴とするリードレス電子部品の構造。[Claims for Utility Model Registration] In a leadless electronic component having electrodes on the side and bottom surfaces of the lower corner, the lower corner is chamfered, and the side and bottom corners are chamfered.
A structure of a leadless electronic component characterized by forming a continuous electrode on a chamfered portion and a lower surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6793988U JPH01173946U (en) | 1988-05-25 | 1988-05-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6793988U JPH01173946U (en) | 1988-05-25 | 1988-05-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01173946U true JPH01173946U (en) | 1989-12-11 |
Family
ID=31293276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6793988U Pending JPH01173946U (en) | 1988-05-25 | 1988-05-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01173946U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03184384A (en) * | 1989-12-13 | 1991-08-12 | Nec Corp | Optical module submount and manufacture thereof |
| JP2000164755A (en) * | 1998-11-25 | 2000-06-16 | Kyocera Corp | High-frequency circuit package |
-
1988
- 1988-05-25 JP JP6793988U patent/JPH01173946U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03184384A (en) * | 1989-12-13 | 1991-08-12 | Nec Corp | Optical module submount and manufacture thereof |
| JP2000164755A (en) * | 1998-11-25 | 2000-06-16 | Kyocera Corp | High-frequency circuit package |