JPH01104735U - - Google Patents

Info

Publication number
JPH01104735U
JPH01104735U JP20008287U JP20008287U JPH01104735U JP H01104735 U JPH01104735 U JP H01104735U JP 20008287 U JP20008287 U JP 20008287U JP 20008287 U JP20008287 U JP 20008287U JP H01104735 U JPH01104735 U JP H01104735U
Authority
JP
Japan
Prior art keywords
hybrid
chip
heat sink
generation density
heat generation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20008287U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP20008287U priority Critical patent/JPH01104735U/ja
Publication of JPH01104735U publication Critical patent/JPH01104735U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Wire Bonding (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例のハイブリツドIC
の要部を示す縦断面図、第2図は第1図の要部を
拡大して示す平面図、第3図は従来のハイブリツ
ドICの要部を示す縦断面図、第4図は第3図の
要部を拡大して示す平面図である。 11……セラミツク基板、12……ヒートシン
クブロツク、13……銀ろう、14……発熱密度
の大きいICチツプ、15……表面パターン、1
6……ボンデイングワイヤ、17……チツプ部品
、18……メタルキヤツプ、19……ウエルドリ
ング。
Figure 1 shows a hybrid IC according to an embodiment of the present invention.
2 is a plan view showing an enlarged view of the main part of FIG. 1, FIG. 3 is a longitudinal sectional view showing the main part of a conventional hybrid IC, and FIG. FIG. 3 is a plan view showing an enlarged main part of the figure. 11...Ceramic substrate, 12...Heat sink block, 13...Silver solder, 14...IC chip with high heat generation density, 15...Surface pattern, 1
6... Bonding wire, 17... Chip parts, 18... Metal cap, 19... Weld ring.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板上にヒートシンクブロツクを介して発熱密
度の大きいICチツプが搭載され、このICチツ
プと電極パターンとがワイヤボンデイングによつ
て接続されたハイブリツドICにおいて、前記ヒ
ートシンクブロツクを、前記ICチツプを搭載さ
れた側の角部を斜めに削除した形状としたことを
特徴とするハイブリツドIC。
In a hybrid IC, an IC chip with high heat generation density is mounted on a substrate via a heat sink block, and this IC chip and an electrode pattern are connected by wire bonding. A hybrid IC characterized by having a shape in which side corners are removed diagonally.
JP20008287U 1987-12-30 1987-12-30 Pending JPH01104735U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20008287U JPH01104735U (en) 1987-12-30 1987-12-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20008287U JPH01104735U (en) 1987-12-30 1987-12-30

Publications (1)

Publication Number Publication Date
JPH01104735U true JPH01104735U (en) 1989-07-14

Family

ID=31490508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20008287U Pending JPH01104735U (en) 1987-12-30 1987-12-30

Country Status (1)

Country Link
JP (1) JPH01104735U (en)

Similar Documents

Publication Publication Date Title
JPH01104735U (en)
JPH0279044U (en)
JPS62204365U (en)
JPH01173946U (en)
JPH022835U (en)
JPS6364055U (en)
JPS636731U (en)
JPH0258393U (en)
JPS61199046U (en)
JPS6427248U (en)
JPH01157424U (en)
JPS63200338U (en)
JPS61114849U (en)
JPH0385641U (en)
JPH031437U (en)
JPS6151737U (en)
JPH0179831U (en)
JPH0176057U (en)
JPS6292644U (en)
JPH0288240U (en)
JPS6344453U (en)
JPS62147345U (en)
JPH0229525U (en)
JPS6420339U (en)
JPS63197144U (en)