JPS6292644U - - Google Patents
Info
- Publication number
- JPS6292644U JPS6292644U JP1985185737U JP18573785U JPS6292644U JP S6292644 U JPS6292644 U JP S6292644U JP 1985185737 U JP1985185737 U JP 1985185737U JP 18573785 U JP18573785 U JP 18573785U JP S6292644 U JPS6292644 U JP S6292644U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- metal electrode
- heat sink
- brazing material
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 238000005219 brazing Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 claims 1
- 238000003466 welding Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
第１図はこの考案に係る半導体装置の一実施例
による概要構成を模式的に示す断面図であり、ま
た第２図は同上従来例による概要構成を模式的に
示す断面図である。
１１……半導体チツプ基板、１２……基板下部
電極面の金属電極、１２ａ……金属電極側面周囲
の突起部、１３……放熱板、１４……ロー材。
FIG. 1 is a sectional view schematically showing the general structure of an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a sectional view schematically showing the general structure of the conventional example. DESCRIPTION OF SYMBOLS 11... Semiconductor chip substrate, 12... Metal electrode on the lower electrode surface of the substrate, 12a... Protrusion around the side surface of the metal electrode, 13... Heat sink, 14... Brazing material.
Claims (1)
ロー材を用いて、金属電極および放熱板を順次に
溶着固定させて構成する半導体装置において、前
記金属電極の側面部周囲に突起部を突出形成させ
たことを特徴とする半導体装置。 In a semiconductor device configured by sequentially welding and fixing a metal electrode and a heat sink to a lower electrode surface of a semiconductor chip substrate using a brazing material such as solder, a protrusion is formed protruding around the side surface of the metal electrode. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985185737U JPS6292644U (en) | 1985-12-02 | 1985-12-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985185737U JPS6292644U (en) | 1985-12-02 | 1985-12-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6292644U true JPS6292644U (en) | 1987-06-13 |
Family
ID=31134644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985185737U Pending JPS6292644U (en) | 1985-12-02 | 1985-12-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6292644U (en) |
-
1985
- 1985-12-02 JP JP1985185737U patent/JPS6292644U/ja active Pending