JPS61102039U - - Google Patents
Info
- Publication number
- JPS61102039U JPS61102039U JP18608084U JP18608084U JPS61102039U JP S61102039 U JPS61102039 U JP S61102039U JP 18608084 U JP18608084 U JP 18608084U JP 18608084 U JP18608084 U JP 18608084U JP S61102039 U JPS61102039 U JP S61102039U
- Authority
- JP
- Japan
- Prior art keywords
- main surface
- fixed
- semiconductor element
- metal piece
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
第1図は本考案の一実施例図、第2図は従来装
置の一例図、第3図及び第4図はそれぞれ本考案
の実施例図である。
符号の説明、1……金属配線、2……基板、3
……金属片、4……半導体素子、5……ワイヤ、
6……はんだ、7……ビス、8……ヒートシンク
、9……金属片。
FIG. 1 shows an embodiment of the present invention, FIG. 2 shows an example of a conventional device, and FIGS. 3 and 4 show embodiments of the present invention. Explanation of symbols, 1...Metal wiring, 2...Substrate, 3
...Metal piece, 4...Semiconductor element, 5...Wire,
6...Solder, 7...Screw, 8...Heat sink, 9...Metal piece.
Claims (1)
た各電極にそれぞれ接続するように該主面に各金
属片を固着し、また他方の主面にも金属片を固着
し、上記薄板状の半導体素子を基板に垂直に配置
して該基板上に設けられた金属配線に上記各金属
片を固着したことを特徴とする半導体装置。 Each metal piece is fixed to one main surface of a thin plate-shaped semiconductor element so as to be connected to each electrode provided on the main surface, and a metal piece is also fixed to the other main surface of the thin plate-shaped semiconductor element. 1. A semiconductor device characterized in that a semiconductor element is arranged perpendicularly to a substrate, and each metal piece is fixed to a metal wiring provided on the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18608084U JPS61102039U (en) | 1984-12-10 | 1984-12-10 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18608084U JPS61102039U (en) | 1984-12-10 | 1984-12-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61102039U true JPS61102039U (en) | 1986-06-28 |
Family
ID=30743542
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18608084U Pending JPS61102039U (en) | 1984-12-10 | 1984-12-10 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61102039U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015005664A (en) * | 2013-06-21 | 2015-01-08 | 株式会社東芝 | Electronic component and method of manufacturing the same |
-
1984
- 1984-12-10 JP JP18608084U patent/JPS61102039U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015005664A (en) * | 2013-06-21 | 2015-01-08 | 株式会社東芝 | Electronic component and method of manufacturing the same |
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