JPS6244465U - - Google Patents
Info
- Publication number
- JPS6244465U JPS6244465U JP13579185U JP13579185U JPS6244465U JP S6244465 U JPS6244465 U JP S6244465U JP 13579185 U JP13579185 U JP 13579185U JP 13579185 U JP13579185 U JP 13579185U JP S6244465 U JPS6244465 U JP S6244465U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- mounting structure
- leads
- utility
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 5
- 239000004020 conductor Substances 0.000 claims 2
- 238000005476 soldering Methods 0.000 claims 2
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第１図はこの考案の一実施例による実装断面図
、第２図は従来の実装断面図である。
図において、１はトランジスタ、２はリード、
３は基板、４は半田、４ａは半田層である。なお
、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a sectional view of an implementation according to an embodiment of this invention, and FIG. 2 is a sectional view of a conventional implementation. In the figure, 1 is a transistor, 2 is a lead,
3 is a substrate, 4 is a solder, and 4a is a solder layer. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
を接合させて半田付けを行なう実装構造において
、上記半導体素子のリードに予備半田を施すと共
に上記基板の導体パターン上に予備半田を施し、
上記導体パターンと上記リードの接合面間に所定
厚さの半田層を形成したことを特徴とする半導体
素子の実装構造。 (2) 半導体素子は電力増幅用トランジスタであ
ることを特徴とする実用新案登録請求の範囲第１
項記載の半導体素子の実装構造。[Claims for Utility Model Registration] (1) In a mounting structure in which leads of a semiconductor element are bonded and soldered to a conductor pattern of a substrate, preliminary soldering is applied to the leads of the semiconductor element, and at the same time, Apply preliminary soldering,
A mounting structure for a semiconductor element, characterized in that a solder layer of a predetermined thickness is formed between the bonding surfaces of the conductor pattern and the lead. (2) Claim No. 1 for utility model registration, characterized in that the semiconductor element is a power amplification transistor.
Mounting structure of the semiconductor element described in .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13579185U JPS6244465U (en) | 1985-09-03 | 1985-09-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13579185U JPS6244465U (en) | 1985-09-03 | 1985-09-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6244465U true JPS6244465U (en) | 1987-03-17 |
Family
ID=31038312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13579185U Pending JPS6244465U (en) | 1985-09-03 | 1985-09-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6244465U (en) |
-
1985
- 1985-09-03 JP JP13579185U patent/JPS6244465U/ja active Pending
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