JPS62186428U - - Google Patents

Info

Publication number
JPS62186428U
JPS62186428U JP1986076833U JP7683386U JPS62186428U JP S62186428 U JPS62186428 U JP S62186428U JP 1986076833 U JP1986076833 U JP 1986076833U JP 7683386 U JP7683386 U JP 7683386U JP S62186428 U JPS62186428 U JP S62186428U
Authority
JP
Japan
Prior art keywords
integrated circuit
chip
circuit component
lead terminals
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986076833U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986076833U priority Critical patent/JPS62186428U/ja
Publication of JPS62186428U publication Critical patent/JPS62186428U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａ，ｂは本考案のパツケージの実施例を
示す水平及び垂直の断面図、第２図は本考案を両
面ＩＣチツプに適用した場合の実施例を示す垂直
断面図、第３図ａ，ｂは従来例を示す水平及び垂
直の断面図である。 第１図において、１はパツケージ本体、３，３
′はリード端子、３ａ，３′は一端部、５はＩＣ
チツプ、５ａは接続面である。 Figures 1a and b are horizontal and vertical sectional views showing an embodiment of the package of the present invention, Figure 2 is a vertical sectional view showing an embodiment of the present invention applied to a double-sided IC chip, and Figure 3a. , b are horizontal and vertical sectional views showing a conventional example. In Figure 1, 1 is the package body, 3, 3
' is a lead terminal, 3a, 3' is one end, 5 is an IC
The chip 5a is a connecting surface.

Claims (1)

【実用新案登録請求の範囲】 集積回路部品パツケージであつて、多数のリー
ド端子３の一端を細くしてチツプ収容個所の周囲
に臨ませ、 該リード端子３の一端部３ａ上に集積回路部品
のチツプ５の接続面５ａをマウントすると共に接
続し、 チツプ５とリード端子３の一部をパツケージ本
体１で気密封止する集積回路部品パツケージ。[Scope of Claim for Utility Model Registration] An integrated circuit component package, wherein one end of a large number of lead terminals 3 is made thin to face the periphery of a chip housing area, and an integrated circuit component is mounted on one end 3a of the lead terminals 3. This integrated circuit component package mounts and connects a connecting surface 5a of a chip 5, and hermetically seals a part of the chip 5 and lead terminals 3 with a package body 1.
JP1986076833U 1986-05-20 1986-05-20 Pending JPS62186428U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986076833U JPS62186428U (en) 1986-05-20 1986-05-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986076833U JPS62186428U (en) 1986-05-20 1986-05-20

Publications (1)

Publication Number Publication Date
JPS62186428U true JPS62186428U (en) 1987-11-27

Family

ID=30924279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986076833U Pending JPS62186428U (en) 1986-05-20 1986-05-20

Country Status (1)

Country Link
JP (1) JPS62186428U (en)

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