JPS6157555U - - Google Patents

Info

Publication number
JPS6157555U
JPS6157555U JP1984143239U JP14323984U JPS6157555U JP S6157555 U JPS6157555 U JP S6157555U JP 1984143239 U JP1984143239 U JP 1984143239U JP 14323984 U JP14323984 U JP 14323984U JP S6157555 U JPS6157555 U JP S6157555U
Authority
JP
Japan
Prior art keywords
board
electronic component
component mounting
electronic components
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1984143239U
Other languages
Japanese (ja)
Other versions
JPH039341Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984143239U priority Critical patent/JPH039341Y2/ja
Publication of JPS6157555U publication Critical patent/JPS6157555U/ja
Application granted granted Critical
Publication of JPH039341Y2 publication Critical patent/JPH039341Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、前記実用新案登録請求の範囲第1項
に基づいた本考案の電子部品搭載用基板の縦断面
図、第2図は、前記実用新案登録請求の範囲第3
項に基づいた本考案の電子部品搭載用基板の縦断
面図、第3図及び第4図は、前記実用新案登録請
求の範囲第4項に基づいた本考案の電子部品搭載
用基板の実施例の縦断面図、第5図は、前記実用
新案登録請求の範囲第5項に基づいた本考案の電
子部品搭載用基板の実施例の縦断面図、第6図は
、本考案の電子部品搭載用基板に半導体素子を実
装した状態の縦断面図、第7図は、従来の電子部
品搭載用基板の縦断面図である。 1…プリント配線用基板、2…金属被膜層、3
…はんだ層、4…金属板、5…電子部品搭載用凹
部、6…導体回路部、7…金属メツキ被膜、8…
半導体素子、9…ボンデイングワイヤー、10…
封止用樹脂。
FIG. 1 is a vertical cross-sectional view of the electronic component mounting board of the present invention based on claim 1 of the above-mentioned utility model registration, and FIG.
The vertical sectional views, FIGS. 3 and 4, of the electronic component mounting board of the present invention based on the above-mentioned utility model registration claim 4 are examples of the electronic component mounting board of the present invention based on the above-mentioned utility model registration claim 4. FIG. 5 is a longitudinal cross-sectional view of an embodiment of the electronic component mounting board of the present invention based on claim 5 of the above-mentioned utility model registration, and FIG. 6 is a vertical cross-sectional view of an embodiment of the electronic component mounting board of the present invention. FIG. 7 is a longitudinal sectional view of a conventional electronic component mounting substrate. 1... Printed wiring board, 2... Metal coating layer, 3
...Solder layer, 4...Metal plate, 5...Concave part for mounting electronic components, 6...Conductor circuit part, 7...Metal plating film, 8...
Semiconductor element, 9... Bonding wire, 10...
Sealing resin.

Claims (1)

【実用新案登録請求の範囲】 1 プリント配線用基板の金属被膜層に、金属板
が接合されていることを特徴とする電子部品搭載
用基板。 2 前記基板は有機系樹脂素材からなることを特
徴とする実用新案登録請求の範囲第1項記載の電
子部品搭載用基板。 3 前記金属板はプリント配線用基板の凹部内に
接合されていることを特徴とする実用新案登録請
求の範囲第1項又は第2項記載の電子部品搭載用
基板。 4 電子部品搭載用凹部底面に金属板の一部が露
出していることを特徴とする実用新案登録請求の
範囲第1項〜第3項記載の電子部品搭載用基板。 5 前記凹部内に金属メツキ被膜を有することを
特徴とする実用新案登録請求の範囲第4項記載の
電子部品搭載用基板。 6 前記基板は、チツプキヤリアであることを特
徴とする実用新案登録請求の範囲第1項〜第5項
記載の電子部品搭載用基板。 7 前記基板は、ピングリツドアレイであること
を特徴とする実用新案登録請求の範囲第1項〜第
5項記載の電子部品搭載用基板。
[Claims for Utility Model Registration] 1. A board for mounting electronic components, characterized in that a metal plate is bonded to a metal coating layer of a printed wiring board. 2. The electronic component mounting board according to claim 1, wherein the board is made of an organic resin material. 3. The electronic component mounting board according to claim 1 or 2, wherein the metal plate is bonded within a recess of a printed wiring board. 4. A substrate for mounting electronic components according to claims 1 to 3 of the utility model registration, characterized in that a part of the metal plate is exposed at the bottom of the recess for mounting electronic components. 5. The electronic component mounting board according to claim 4, which has a metal plating film in the recess. 6. The board for mounting electronic components according to claims 1 to 5, wherein the board is a chip carrier. 7. The electronic component mounting board according to claims 1 to 5, wherein the board is a pin grid array.
JP1984143239U 1984-09-20 1984-09-20 Expired JPH039341Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984143239U JPH039341Y2 (en) 1984-09-20 1984-09-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984143239U JPH039341Y2 (en) 1984-09-20 1984-09-20

Publications (2)

Publication Number Publication Date
JPS6157555U true JPS6157555U (en) 1986-04-17
JPH039341Y2 JPH039341Y2 (en) 1991-03-08

Family

ID=30701541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984143239U Expired JPH039341Y2 (en) 1984-09-20 1984-09-20

Country Status (1)

Country Link
JP (1) JPH039341Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50143072A (en) * 1974-05-08 1975-11-18
JPS5593286A (en) * 1979-01-10 1980-07-15 Hitachi Ltd Electronic circuit and method of fabricating same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50143072A (en) * 1974-05-08 1975-11-18
JPS5593286A (en) * 1979-01-10 1980-07-15 Hitachi Ltd Electronic circuit and method of fabricating same

Also Published As

Publication number Publication date
JPH039341Y2 (en) 1991-03-08

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