JPS62166636U - - Google Patents
Info
- Publication number
- JPS62166636U JPS62166636U JP5431986U JP5431986U JPS62166636U JP S62166636 U JPS62166636 U JP S62166636U JP 5431986 U JP5431986 U JP 5431986U JP 5431986 U JP5431986 U JP 5431986U JP S62166636 U JPS62166636 U JP S62166636U
- Authority
- JP
- Japan
- Prior art keywords
- pad
- bare chip
- semiconductor bare
- electrode
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011521 glass Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 8
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Description
第１図はこの考案の一実施例を示す平面図、第
２図は第１図に示したものの断面図、第３図は従
来のベアチツプ実装基板を示す平面図、第４図は
第３図に示したものの断面図である。
図において１は基板、２はダイボンデイングパ
ツド、３は回路導体パターン、４はワイヤボンデ
イングパツド、５は厚膜抵抗体、６，７，２０，
２１はオーバーコートガラスパターン、８はベア
チツプ、９は接着剤、１０は電極パツド、１１は
ボンデイングワイヤである。なお、各図中、同一
符号は同一又は相当部分を示す。
Fig. 1 is a plan view showing an embodiment of this invention, Fig. 2 is a cross-sectional view of what is shown in Fig. 1, Fig. 3 is a plan view showing a conventional bare chip mounting board, and Fig. 4 is the same as Fig. 3. FIG. In the figure, 1 is a substrate, 2 is a die bonding pad, 3 is a circuit conductor pattern, 4 is a wire bonding pad, 5 is a thick film resistor, 6, 7, 20,
21 is an overcoat glass pattern, 8 is a bare chip, 9 is an adhesive, 10 is an electrode pad, and 11 is a bonding wire. In each figure, the same reference numerals indicate the same or equivalent parts.
Claims (1)
、この半導体ベアチツプの大きさよりも全周方向
に大きく、中央に前記の半導体ベアチツプが取り
付けられたダイボンデイングパツドと、このダイ
ボンデイングパツドの周囲に配置され、前記の半
導体ベアチツプの各電極パツドとボンデイングワ
イヤで接続された複数のワイヤボンデイングパツ
ドと、前記のダイボンデイングパツドの各辺部に
おける前記の半導体ベアチツプの電極パツド位置
と対応した位置からこの半導体ベアチツプの各電
極パツドと前記ボンデイングワイヤで接続された
各ワイヤボンデイングパツドにかけて、前記の半
導体ベアチツプの各電極パツドと各ワイヤボンデ
イングパツドの１組ごとに形成され、前記のダイ
ボンデイングパツドにおける前記電極パツド位置
と対応した位置ではダイボンデイングパツドに重
ねて形成されたガラスパターンとを有することを
特徴とする半導体ベアチツプ実装基板。 a semiconductor bare chip having a plurality of electrode pads; a die bonding pad that is larger in the circumferential direction than the semiconductor bare chip and to which the semiconductor bare chip is attached in the center; and a die bonding pad arranged around the die bonding pad, A plurality of wire bonding pads are connected to each electrode pad of the semiconductor bare chip by bonding wires, and a plurality of wire bonding pads are connected to each electrode pad of the semiconductor bare chip from a position corresponding to the position of the electrode pad of the semiconductor bare chip on each side of the die bonding pad. Each electrode pad of the semiconductor bare chip and each wire bonding pad are formed for each set of each electrode pad and each wire bonding pad connected by the bonding wire, and the electrode in the die bonding pad is 1. A semiconductor bare chip mounting board comprising a glass pattern formed over a die bonding pad at a position corresponding to the pad position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5431986U JPS62166636U (en) | 1986-04-11 | 1986-04-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5431986U JPS62166636U (en) | 1986-04-11 | 1986-04-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62166636U true JPS62166636U (en) | 1987-10-22 |
Family
ID=30881199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5431986U Pending JPS62166636U (en) | 1986-04-11 | 1986-04-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62166636U (en) |
-
1986
- 1986-04-11 JP JP5431986U patent/JPS62166636U/ja active Pending