JPS63197357U - - Google Patents
Info
- Publication number
- JPS63197357U JPS63197357U JP8986887U JP8986887U JPS63197357U JP S63197357 U JPS63197357 U JP S63197357U JP 8986887 U JP8986887 U JP 8986887U JP 8986887 U JP8986887 U JP 8986887U JP S63197357 U JPS63197357 U JP S63197357U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- multilayer circuit
- sub
- flange
- chip module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
Description
第１図は本考案の一実施例の部分平面図および
第２図は第１図のＡ−Ａ線断面図である。
１……多層回路基板、２……亜鍔型改造パター
ン、２１，２２，５……パツド、２３……ブリツ
ジ線、３，６……絶縁層、４１，４２，４３……
窓、５１……金、５２……ニツケル、５３……銅
。
FIG. 1 is a partial plan view of an embodiment of the present invention, and FIG. 2 is a sectional view taken along line A--A in FIG. DESCRIPTION OF SYMBOLS 1... Multilayer circuit board, 2... Sub-flange type modified pattern, 21, 22, 5... Pad, 23... Bridge wire, 3, 6... Insulating layer, 41, 42, 43...
Window, 51...gold, 52...nickel, 53...copper.
Claims (1)
ＬＳＩチツプ同士及び外部との電気的接続を行う
ＬＳＩチツプモジユールにおいて、前記多層回路
基板の表面に形成され２つのパツドと、２つのパ
ツドを結ぶブリツジ線とからなる亜鍔型改造パタ
ーンと、前記亜鍔型改造パターンの一部を除いて
前記多層回路基板及び前記亜鍔型改造パターンの
表面を覆う絶縁層とを有することを特徴とするＬ
ＳＩチツプモジユール。 In an LSI chip module in which a plurality of LSI chips are mounted on a multilayer circuit board and the LSI chips are electrically connected to each other and to the outside, two pads formed on the surface of the multilayer circuit board and a bridge wire connecting the two pads are provided. and an insulating layer that covers the surfaces of the multilayer circuit board and the sub-flange-shaped modified pattern except for a part of the sub-flange-shaped modified pattern.
SI chip module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8986887U JPS63197357U (en) | 1987-06-10 | 1987-06-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8986887U JPS63197357U (en) | 1987-06-10 | 1987-06-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63197357U true JPS63197357U (en) | 1988-12-19 |
Family
ID=30949240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8986887U Pending JPS63197357U (en) | 1987-06-10 | 1987-06-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63197357U (en) |
-
1987
- 1987-06-10 JP JP8986887U patent/JPS63197357U/ja active Pending
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