JPS6364050U - - Google Patents
Info
- Publication number
- JPS6364050U JPS6364050U JP1986159285U JP15928586U JPS6364050U JP S6364050 U JPS6364050 U JP S6364050U JP 1986159285 U JP1986159285 U JP 1986159285U JP 15928586 U JP15928586 U JP 15928586U JP S6364050 U JPS6364050 U JP S6364050U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- semiconductor chip
- envelope
- metal wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 3
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第1図は本考案に係る半導体装置の構造を示す
概略断面図、第2図および第3図は従来の半導体
装置の構造を示す概略断面図である。
1……基板、5……半導体チツプ、6……金属
線、7……外部リード、8……外囲器。
FIG. 1 is a schematic sectional view showing the structure of a semiconductor device according to the present invention, and FIGS. 2 and 3 are schematic sectional views showing the structure of a conventional semiconductor device. 1... Board, 5... Semiconductor chip, 6... Metal wire, 7... External lead, 8... Envelope.
Claims (1)
、これら基板および半導体チツプと、外部リード
とが樹脂により封止されるとともに外囲器が形成
されてなる半導体装置において、 前記基板と外部リードとが可撓性および可塑性
を有する金属線によつてのみ連結されたことを特
徴とする半導体装置。[Claims for Utility Model Registration] A semiconductor device in which a semiconductor chip is mounted on a substrate having heat dissipating properties, the substrate, the semiconductor chip, and external leads are sealed with resin and an envelope is formed, A semiconductor device characterized in that the substrate and the external lead are connected only by a metal wire having flexibility and plasticity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986159285U JPS6364050U (en) | 1986-10-16 | 1986-10-16 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986159285U JPS6364050U (en) | 1986-10-16 | 1986-10-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6364050U true JPS6364050U (en) | 1988-04-27 |
Family
ID=31083569
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986159285U Pending JPS6364050U (en) | 1986-10-16 | 1986-10-16 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6364050U (en) |
-
1986
- 1986-10-16 JP JP1986159285U patent/JPS6364050U/ja active Pending
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