JPH0536275Y2 - - Google Patents
Info
- Publication number
- JPH0536275Y2 JPH0536275Y2 JP1988159576U JP15957688U JPH0536275Y2 JP H0536275 Y2 JPH0536275 Y2 JP H0536275Y2 JP 1988159576 U JP1988159576 U JP 1988159576U JP 15957688 U JP15957688 U JP 15957688U JP H0536275 Y2 JPH0536275 Y2 JP H0536275Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- conductor
- package
- semiconductor
- soldered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 18
- 229910000679 solder Inorganic materials 0.000 description 6
- 230000035882 stress Effects 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 230000006378 damage Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000035939 shock Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
(a) 考案の技術分野
本考案は半導体装置、特に高密度実装が可能な
半導体装置の実装構造に関する。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a mounting structure for a semiconductor device that allows high-density packaging.
(b) 従来技術と問題点
近年、ICやLSIなどの半導体集積回路を収容す
る容器としてリードレスパツケージが用いられて
いる。このパツケージは通常の外部リードを有す
る型のパツケージと同じく内部にICチツプを収
納してワイヤーボンデングされている。そのた
め、汎用化された組立法を採ることができ、且つ
外部リードの代わりに接続用の導体パツドが設け
られてコンパクトな構造となつており、別名をチ
ツプキヤリヤと呼ばれている。(b) Prior Art and Problems In recent years, leadless packages have been used as containers for housing semiconductor integrated circuits such as ICs and LSIs. This package houses an IC chip inside and is wire-bonded, just like a regular package with external leads. Therefore, a general-purpose assembly method can be used, and a conductor pad for connection is provided instead of an external lead, resulting in a compact structure, which is also called a chip carrier.
従つて、このようなパツケージは回路基板（プ
リント基板）上で他のパツケージより一層高密度
実装することができ、そのために重宝がられて各
方面で利用が活発化している構造である。 Therefore, such a package can be mounted on a circuit board (printed board) at a higher density than other packages, and for this reason, it is a structure that is highly valued and is increasingly being used in various fields.
第１図はこのパツケージ１を回路基板２に装着
した一実施例の構造断面図を示しており、１１は
ICチツプ、１２は導体パツド、１３はキヤツプ、
１４は放熱板で、本例は発熱量の大きいICの構
造を示したものである。また、第２図は第１図に
示すパツケージ１の回路基板２側から見た平面図
を示しており、図示のように多数の導体パツド１
２が設けられていて、パツド数は例えばLSIでは
200〜300個にも及ぶ多数個となる。このようなリ
ードレスパツケージは、第１図に示すように回路
基板２に設けられた接続用電極２１とパツケージ
１の導体パツド１２とが半田３（半田の厚みは約
50μｍ）で接合され、回路基板に装着される。 FIG. 1 shows a structural sectional view of an embodiment in which this package 1 is attached to a circuit board 2, and 11 is
IC chip, 12 is a conductor pad, 13 is a cap,
14 is a heat sink, and this example shows the structure of an IC that generates a large amount of heat. 2 is a plan view of the package 1 shown in FIG. 1 viewed from the circuit board 2 side.
2 is provided, and the number of pads is, for example, in LSI.
There are as many as 200 to 300 pieces. In such a leadless package, as shown in FIG.
50μm) and attached to the circuit board.
ところで、第１図のように装着すると、回路の
動作中に熱シヨツクが加わつた場合に、半田接合
部分で欠損が生じることがある。欠損とは半田３
にクラツクが入つて外れたり、あるいは回路基板
２から接続用電極２１が剥離したりすることで、
かような欠損は、回路基板２に形成された電子回
路の動作を不能にする致命傷になることは言うま
でもない。この欠損の主因は回路基板２がエポキ
シやポリイミドなどの有機樹脂製であつて熱膨脹
率が大きく、一方のパツケージ１はセラミツク製
で熱膨脹率が小さいため、半田接合部分にストレ
ス（歪）が加わつて破壊されるものである。 By the way, if the circuit is mounted as shown in FIG. 1, damage may occur at the solder joints if a thermal shock is applied during operation of the circuit. Deficiency is solder 3
If the circuit board 2 cracks and comes off, or if the connection electrode 21 peels off from the circuit board 2,
Needless to say, such a defect would be a fatal injury that would make the electronic circuit formed on the circuit board 2 inoperable. The main cause of this damage is that the circuit board 2 is made of organic resin such as epoxy or polyimide, which has a large coefficient of thermal expansion, while the package 1 is made of ceramic and has a small coefficient of thermal expansion, which causes stress (strain) to be applied to the solder joints. It is something that will be destroyed.
なお、パツケージの裏面に多数の端子ピンが植
設されている半導体パツケージが例えば特開昭58
−16552号公報において開示されているが、この
実装構造は特開昭58−16552号公報にも記載され
ているように、プリント板の穴に、パツケージ裏
面の端子ピンを挿入して半田付けするものであ
る。この場合端子ピンをプリント板に設けられた
穴に半田付け固定されてしまうので前記第１図の
構造の場合と同様の問題が発生する。 Note that a semiconductor package in which a large number of terminal pins are implanted on the back side of the package is disclosed in, for example, JP-A-58
This mounting structure is disclosed in Japanese Patent Application Laid-open No. 16552-16552, but as described in Japanese Patent Application Laid-open No. 58-16552, the terminal pins on the back of the package are inserted into the holes in the printed board and soldered. It is something. In this case, the terminal pins are soldered and fixed into holes provided in the printed circuit board, resulting in the same problem as in the structure shown in FIG. 1.
この場合、回路基板２をパツケージ１と同じ材
質のセラミツク基板にすれば、ストレスがなくな
つて破壊されないが、セラミツク基板は誘電率が
高い為に電子回路の動作を遅延させる悪影響があ
つて好ましくなく、特殊な場合を除いてはセラミ
ツク基板は殆ど用いられない。 In this case, if the circuit board 2 is made of a ceramic board made of the same material as the package 1, the stress will be removed and the board will not break. However, since the ceramic board has a high dielectric constant, it has the negative effect of delaying the operation of the electronic circuit, which is not preferable. Ceramic substrates are rarely used except in special cases.
(c) 考案の目的
本考案は上記の問題点を解消させるための半導
体実装回路装置を提案するものである。(c) Purpose of the invention The present invention proposes a semiconductor mounted circuit device to solve the above problems.
(d) 考案の構成
上記本考案の目的は、半導体素子を収容した半
導体パツケージと、複数個の接続用電極が表面に
設けられた回路基板と、該半導体パツケージの外
面の該回路基板に対向する部分に設けられた複数
個の導体パツドと、各々バネ性を有し、一端が該
導体パツドに当接して蝋づけされ、他端が該接続
用電極に当接して半田づけされた複数本の導体ピ
ンを有することを特徴とする半導体実装回路装置
によつて達成される。(d) Structure of the invention The object of the invention is to provide a semiconductor package containing a semiconductor element, a circuit board having a plurality of connection electrodes on its surface, and a circuit board on the outer surface of the semiconductor package facing the circuit board. A plurality of conductor pads provided in the section, each having a spring property, one end of which is in contact with the conductor pad and soldered, and the other end of which is in contact with the connection electrode and soldered. This is achieved by a semiconductor mounted circuit device characterized by having conductor pins.
(e) 考案の実施例
以下、図面を参照して実施例によつて詳細に説
明する。第３図、第４図は本考案にかかる一実施
例の断面図であり、まず第３図に示すようにパツ
ケージ１のすべての導体パツド１２に導体ピン４
を高融点金属で鑞づけしておく。(e) Examples of the invention Hereinafter, the invention will be explained in detail by examples with reference to the drawings. 3 and 4 are cross-sectional views of one embodiment of the present invention. First, as shown in FIG.
Brazed with high melting point metal.
かくして、第４図に示すように回路基板２の接
続用電極２１と導体ピン４とを半田づけする。そ
うすれば、回路基板２上の電子回路を動作させた
り中止したりして、加熱と冷却とが繰り返され熱
シヨツクが加わつても、導体パツドと電極との接
続部分で欠損を生じることはなくなる。 Thus, as shown in FIG. 4, the connection electrodes 21 of the circuit board 2 and the conductor pins 4 are soldered. In this way, even if the electronic circuit on the circuit board 2 is activated and deactivated, heating and cooling are repeated, and a thermal shock is applied, no damage will occur at the connection between the conductor pad and the electrode. .
第５図はその接続部分の拡大図を示している。
パツケージ１の導体パツド１２はセラミツク基板
を積層し焼結する際にメタライズ層として形成さ
れるが、このメタライズ層に導体ピン４を銀鑞５
で鑞づけしておき、表面をニツケルと金で鍍金し
たものとする。そして、導体パツド１２の広さを
0.2〜0.25mm角とすれば、これに長さ0.5〜1.5mm、
直径0.1〜0.2mm程度の導体ピンを鑞づけし、導体
ピンと回路基板２の電極２１とは当接して半田６
で接合する。電極２１は銅層に半田鍍金されたも
のである。また、導体ピン４はコバール、タング
ステン、モリブデンまたは銅合金などのバネ材で
作成される。 FIG. 5 shows an enlarged view of the connecting portion.
The conductor pads 12 of the package 1 are formed as a metallized layer when ceramic substrates are laminated and sintered.
The surface is plated with nickel and gold. Then, the width of the conductor pad 12 is
If it is 0.2 to 0.25 mm square, add a length of 0.5 to 1.5 mm,
A conductor pin with a diameter of about 0.1 to 0.2 mm is soldered, and the conductor pin and the electrode 21 of the circuit board 2 are brought into contact with each other and soldered 6.
Join with. The electrode 21 is a copper layer plated with solder. Further, the conductor pin 4 is made of a spring material such as Kovar, tungsten, molybdenum, or copper alloy.
半導体パツケージの電極と回路基板の電極間を
接続ピースを介して鑞づけしてストレスを吸収す
る構造が特開昭55−59746号公報に開示されてい
るが、この構造では接続ピースとして球状又はリ
ング状の接続体を使用しており、多数の接続ピー
ス間の間隔を小さくして高密度にするのは困難で
ある。さらに接続ピースは金属片を曲げ加工して
いるので、製作工数や費用が増大する。又半導体
パツケージのリード先端を回路基板の導体パツド
に当接して接続する構造例については特開昭56−
98853号公報に開示されている。しかし、この構
造であるとリード片は板状であり、このリード片
の厚さ方向に対して屈曲が可能であるが、リード
片の幅方向には屈曲しない。従つて、外部との接
続導体本数を増加させるため、上記特開昭56−
98853号公報に記載されている如くパツケージの
周囲側面にリード片を導出する構造にすると、何
れの方向に対してもリード片の柔軟性の効果が失
われてしまう。又、このようなリード片形状であ
ると、多数のリード片間の間隔を小さくして、高
密度にするのは困難である。 JP-A-55-59746 discloses a structure in which stress is absorbed by brazing between the electrodes of a semiconductor package and the electrodes of a circuit board via a connecting piece, but in this structure, the connecting piece is spherical or ring-shaped. It is difficult to achieve high density by reducing the spacing between a large number of connection pieces. Furthermore, since the connecting piece is made by bending a piece of metal, the number of manufacturing steps and costs increase. Furthermore, an example of a structure in which the lead tips of a semiconductor package are connected by contacting them with the conductor pads of a circuit board is disclosed in Japanese Patent Application Laid-Open No. 1986-56.
It is disclosed in Publication No. 98853. However, with this structure, the lead piece is plate-shaped and can be bent in the thickness direction of the lead piece, but not in the width direction of the lead piece. Therefore, in order to increase the number of external connection conductors,
If the structure is such that the lead pieces are led out from the peripheral side of the package as described in Japanese Patent No. 98853, the flexibility of the lead pieces will be lost in any direction. Furthermore, with such a shape of the lead pieces, it is difficult to reduce the distance between the many lead pieces and increase the density.
一方本考案の構造にすれば、導体ピン４は細線
であり、あらゆる方向に対しバネ性を有してお
り、又導体ピン４は回路基板２上に当接した状態
で鑞づけされているのであらゆる方向に柔軟に屈
曲可能となり、従つてストレスは、このピンで吸
収されるから熱ストレスによる破壊は防止され
る。又細い導体ピンであるので、多数のピン間の
間隔を小さくして、高密度にすることが可能であ
る。 On the other hand, with the structure of the present invention, the conductor pin 4 is a thin wire and has spring properties in all directions, and the conductor pin 4 is brazed in contact with the circuit board 2. It can be flexibly bent in all directions, and stress is absorbed by these pins, preventing breakage due to thermal stress. Furthermore, since the conductor pins are thin, the spacing between many pins can be reduced to achieve high density.
この導体ピン４は線材の切断によつて容易に製
作可能であり、従つてストレスの強さに応じて線
材の長さ、径、材質の変更も容易となり、又微小
形状となりうるので導体パツドの数が増大する傾
向にある超LSI等に有効に使用できる。 This conductor pin 4 can be easily manufactured by cutting the wire, and therefore the length, diameter, and material of the wire can be easily changed depending on the strength of the stress, and since it can be made into a minute shape, the conductor pad can be easily manufactured. It can be effectively used for ultra-LSIs, etc. whose number tends to increase.
上記の実施例は発熱量の大きいICの例である
が、ロジツク回路用など一般のICは第６図に示
すようなパツケージ裏面全体に導体パツド１２が
設けられており、これに図示のように導体ピン４
を鑞づけした構造、にすれば同様にストレスを除
去して破壊を防止することができる。 The above embodiment is an example of an IC that generates a large amount of heat, but general ICs such as those for logic circuits are provided with conductor pads 12 on the entire back surface of the package as shown in FIG. Conductor pin 4
A brazed structure can similarly remove stress and prevent breakage.
(f) 考案の効果
以上の説明から明らかなように、本考案によれ
ばパツケージ外面に形成された導体パツドに導体
ピンを取りつけて熱シヨツクの緩衝帯とするため
に、熱シヨツクにより半田接合部が欠損すること
なく、電子回路の信頼性が向上するものである。(f) Effect of the invention As is clear from the above explanation, according to the invention, the conductor pins are attached to the conductor pads formed on the outer surface of the package to serve as a buffer band for the thermal shock. This improves the reliability of electronic circuits without causing defects.
第１図は従来のパツケージを回路基板に装着し
た構造断面図例、第２図はそのパツケージの平面
図、第３図は本考案にかかる半導体パツケージの
断面図、第４図は本考案の一実施例による半導体
実装回路装置の断面図、第５図は第４図における
要部拡大図、第６図は本考案の他の実施例による
半導体実装回路装置の断面図を示す。
図中、１はパツケージ、２は回路基板、３，６
は半田、４は導体ピン、５は銀鑞、１２は導体パ
ツド、２１は接続用の電極を示している。
Figure 1 is an example of a structural cross-sectional view of a conventional package mounted on a circuit board, Figure 2 is a plan view of the package, Figure 3 is a cross-sectional view of a semiconductor package according to the present invention, and Figure 4 is an example of a semiconductor package according to the present invention. FIG. 5 is an enlarged view of the main part of FIG. 4, and FIG. 6 is a cross-sectional view of a semiconductor packaged circuit device according to another embodiment of the present invention. In the figure, 1 is a package, 2 is a circuit board, 3, 6
1 is solder, 4 is a conductor pin, 5 is silver solder, 12 is a conductor pad, and 21 is a connection electrode.
Claims (1)
板と、 該半導体パツケージの外面の該回路基板に対向
する部分に設けられた複数個の導体パツドと、 各々バネ性を有し、一端が該導体パツドに当接
して鑞づけされ、他端が該接続用電極に当接して
半田づけされた複数本の導体ピンを有することを
特徴とする半導体実装回路装置。[Claims for Utility Model Registration] A semiconductor package housing a semiconductor element, a circuit board having a plurality of connection electrodes provided on its surface, and a portion of the outer surface of the semiconductor package facing the circuit board. It has a plurality of conductor pads and a plurality of conductor pins each having a spring property, one end of which is brazed in contact with the conductor pad, and the other end of which is soldered in contact with the connection electrode. A semiconductor mounted circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988159576U JPH0536275Y2 (en) | 1988-12-08 | 1988-12-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988159576U JPH0536275Y2 (en) | 1988-12-08 | 1988-12-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0189752U JPH0189752U (en) | 1989-06-13 |
| JPH0536275Y2 true JPH0536275Y2 (en) | 1993-09-14 |
Family
ID=31440912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988159576U Expired - Lifetime JPH0536275Y2 (en) | 1988-12-08 | 1988-12-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0536275Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016048728A (en) * | 2014-08-27 | 2016-04-07 | 株式会社村田製作所 | Conductive post and manufacturing method of multilayer substrate using conductive post |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559746A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Semiconductor device and its mounting circuit device |
| JPS5743452A (en) * | 1980-08-28 | 1982-03-11 | Mitsubishi Electric Corp | Mounting structure for integrated circuit substrate |
| JPS5791586A (en) * | 1980-11-29 | 1982-06-07 | Tokyo Shibaura Electric Co | Hybrid integrated circuit device |
| JPS57121256A (en) * | 1981-01-21 | 1982-07-28 | Hitachi Ltd | Ceramic multilayer wiring structure |
| JPS57181144A (en) * | 1981-05-01 | 1982-11-08 | Toshiba Corp | Semiconductor device |
-
1988
- 1988-12-08 JP JP1988159576U patent/JPH0536275Y2/ja not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559746A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Semiconductor device and its mounting circuit device |
| JPS5743452A (en) * | 1980-08-28 | 1982-03-11 | Mitsubishi Electric Corp | Mounting structure for integrated circuit substrate |
| JPS5791586A (en) * | 1980-11-29 | 1982-06-07 | Tokyo Shibaura Electric Co | Hybrid integrated circuit device |
| JPS57121256A (en) * | 1981-01-21 | 1982-07-28 | Hitachi Ltd | Ceramic multilayer wiring structure |
| JPS57181144A (en) * | 1981-05-01 | 1982-11-08 | Toshiba Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0189752U (en) | 1989-06-13 |
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