JPH0184451U - - Google Patents
Info
- Publication number
- JPH0184451U JPH0184451U JP1987180780U JP18078087U JPH0184451U JP H0184451 U JPH0184451 U JP H0184451U JP 1987180780 U JP1987180780 U JP 1987180780U JP 18078087 U JP18078087 U JP 18078087U JP H0184451 U JPH0184451 U JP H0184451U
- Authority
- JP
- Japan
- Prior art keywords
- soldered
- semiconductor device
- flat part
- flat
- chevron
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 2
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の一実施例の構成図で、ａは平
面図、ｂは側面図、第２図ａ，ｂは本考案の実施
例の要部詳細図、第３図は従来例の構成図で、ａ
側面図、ｂは要部側断面図、ｃはリードの斜視図
である。
図において、１は半導体チツプ、２はセラミツ
クパツケージ、３は入出力パターン、４は電極、
５は印刷配線板、６はパツド、１０，２０はリー
ド、１１は硬鑞、１２は半田、２１は山形屈曲部
、２２，２３はフラツト部をそれぞれ示す。
Figure 1 is a block diagram of an embodiment of the present invention, where a is a plan view, b is a side view, Figures 2a and b are detailed views of the main parts of the embodiment of the present invention, and Figure 3 is a diagram of the conventional example. In the configuration diagram, a
A side view, b is a sectional side view of a main part, and c is a perspective view of the lead. In the figure, 1 is a semiconductor chip, 2 is a ceramic package, 3 is an input/output pattern, 4 is an electrode,
5 is a printed wiring board, 6 is a pad, 10 and 20 are leads, 11 is hard solder, 12 is solder, 21 is a chevron-shaped bent portion, and 22 and 23 are flat portions, respectively.
Claims (1)
４を、印刷配線板５の表面に配設したそれぞれの
パツド６に、リードを介して鑞付け実装する半導
体装置において、 該リード２０が、細幅の導電性金属板よりなり
、該電極４に硬鑞付けするフラツト部２２．該パ
ツド６に半田付けするフラツト部２３、及び両者
の該フラツト部２２，２３を連結する山形屈曲部
２１と、より構成されたことを特徴とする半導体
装置の実装構造。[Scope of Claim for Utility Model Registration] A semiconductor device in which electrodes 4 arranged on the bottom surface of a ceramic package 2 are brazed to respective pads 6 arranged on the surface of a printed wiring board 5 via leads. 20 is a flat part 22. which is made of a narrow conductive metal plate and is hard-soldered to the electrode 4. A semiconductor device mounting structure comprising: a flat part 23 to be soldered to the pad 6; and a chevron-shaped bent part 21 connecting the two flat parts 22, 23.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987180780U JPH0184451U (en) | 1987-11-27 | 1987-11-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987180780U JPH0184451U (en) | 1987-11-27 | 1987-11-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0184451U true JPH0184451U (en) | 1989-06-05 |
Family
ID=31472286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987180780U Pending JPH0184451U (en) | 1987-11-27 | 1987-11-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0184451U (en) |
-
1987
- 1987-11-27 JP JP1987180780U patent/JPH0184451U/ja active Pending