JPH03120041U - - Google Patents

Info

Publication number
JPH03120041U
JPH03120041U JP3017690U JP3017690U JPH03120041U JP H03120041 U JPH03120041 U JP H03120041U JP 3017690 U JP3017690 U JP 3017690U JP 3017690 U JP3017690 U JP 3017690U JP H03120041 U JPH03120041 U JP H03120041U
Authority
JP
Japan
Prior art keywords
cavity
plug
ceramic substrate
type package
provided around
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3017690U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3017690U priority Critical patent/JPH03120041U/ja
Publication of JPH03120041U publication Critical patent/JPH03120041U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bおよびcはそれぞれ本考案のプラ
グイン型パツケージの一実施例を示す上面図、側
面図および裏面図、第2図、第3図、第4図は第
1図の実施例の応用例を示す側面図、第5図、第
6図のa,bおよびcは、それぞれ従来例の上面
図、側面図および裏面図である。 1……セラミツク基板、2……シールリング、
3……ボンデイングパツド、4……外部接続リー
ドピン、5……キヤビテイ、6……バンプ、7…
…ヒートシンク、8……接続用パツケージ。
Figures 1a, b, and c are top, side, and back views showing an embodiment of the plug-in package of the present invention, respectively, and Figures 2, 3, and 4 are examples of the embodiment of Figure 1. A, b, and c in FIGS. 5 and 6 are a top view, a side view, and a back view of the conventional example, respectively. 1...Ceramic substrate, 2...Seal ring,
3... Bonding pad, 4... External connection lead pin, 5... Cavity, 6... Bump, 7...
...Heat sink, 8...Connection package.

Claims (1)

【実用新案登録請求の範囲】 半導体集積回路チツプを搭載するキヤビテイと
、前記キヤビテイの周囲に設けられた複数のボン
デイングパツドと、前記ボンデイングパツドの周
囲に設けられたシールリングとを備えた多層セラ
ミツク基板のキヤビテイを有する面に、前記ボン
デイングパツドと各々前記多層セラミツク基板内
の配線パターンで接続された外部接続用リードピ
ンが設けられているプラグイン型パツケージにお
いて、 多層セラミツク基板のキヤビテイを有する面と
は反対側の面に多数のバンプが設けられているこ
とを特徴とするプラグイン型パツケージ。
[Claims for Utility Model Registration] A multilayer device comprising a cavity in which a semiconductor integrated circuit chip is mounted, a plurality of bonding pads provided around the cavity, and a seal ring provided around the bonding pads. In a plug-in type package, the surface of the multilayer ceramic substrate having the cavity is provided with lead pins for external connection, each of which is connected to the bonding pad through a wiring pattern in the multilayer ceramic substrate. A plug-in type package characterized by having a large number of bumps on the opposite side.
JP3017690U 1990-03-22 1990-03-22 Pending JPH03120041U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3017690U JPH03120041U (en) 1990-03-22 1990-03-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3017690U JPH03120041U (en) 1990-03-22 1990-03-22

Publications (1)

Publication Number Publication Date
JPH03120041U true JPH03120041U (en) 1991-12-10

Family

ID=31532905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3017690U Pending JPH03120041U (en) 1990-03-22 1990-03-22

Country Status (1)

Country Link
JP (1) JPH03120041U (en)

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