JPH0245653U - - Google Patents
Info
- Publication number
- JPH0245653U JPH0245653U JP12508988U JP12508988U JPH0245653U JP H0245653 U JPH0245653 U JP H0245653U JP 12508988 U JP12508988 U JP 12508988U JP 12508988 U JP12508988 U JP 12508988U JP H0245653 U JPH0245653 U JP H0245653U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor
- land
- solder bumps
- side terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 239000000969 carrier Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の実施例に係る半導体装置を示
す破断斜視図、第２図は従来のチツプキヤリア式
の半導体装置を示す破断斜視図である。
１；ボード、２；接続ランド、３，１３；チツ
プキヤリア、３ａ，１３ａ；凹所、３ｂ，１３ｂ
；マウントランド、３ｃ，１３ｃ；ステツチラン
ド、４，１４；半導体ＩＣチツプ、５，１５；封
止樹脂、７，１７；リードフレーム、１６；はん
だバンプ、１７ａ；リードフレームとの接続用エ
リア。
FIG. 1 is a cutaway perspective view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cutaway perspective view showing a conventional chip carrier type semiconductor device. 1; Board, 2; Connection land, 3, 13; Chip carrier, 3a, 13a; Recess, 3b, 13b
Mount land, 3c, 13c; Stitch land, 4, 14; Semiconductor IC chip, 5, 15; Sealing resin, 7, 17; Lead frame, 16; Solder bump, 17a; Area for connection with lead frame.
Claims (1)
接続用ステツチランド及び半導体ＩＣチツプのマ
ウントランドがその表裏両面に形成され側面端子
がその側面に形成された基板と、前記マウントラ
ンドの上に搭載された半導体ＩＣチツプとを有す
る複数個のチツプキヤリアを備え、これらのチツ
プキヤリアを積層し、前記はんだバンプ及び側面
端子を介して前記半導体ＩＣチツプ間を接続した
ことを特徴とするマルチチツプの半導体装置。 A substrate having a plurality of solder bumps, a stitch land for connection with a semiconductor IC chip, and a mounting land for the semiconductor IC chip formed on both the front and back surfaces thereof, and side terminals formed on the side surfaces thereof, and a semiconductor mounted on the mounting land. 1. A multi-chip semiconductor device comprising a plurality of chip carriers each having an IC chip, these chip carriers being stacked, and the semiconductor IC chips being connected via the solder bumps and side terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12508988U JPH0245653U (en) | 1988-09-24 | 1988-09-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12508988U JPH0245653U (en) | 1988-09-24 | 1988-09-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0245653U true JPH0245653U (en) | 1990-03-29 |
Family
ID=31375383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12508988U Pending JPH0245653U (en) | 1988-09-24 | 1988-09-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0245653U (en) |
-
1988
- 1988-09-24 JP JP12508988U patent/JPH0245653U/ja active Pending
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