JPH0476048U - - Google Patents

Info

Publication number
JPH0476048U
JPH0476048U JP11884990U JP11884990U JPH0476048U JP H0476048 U JPH0476048 U JP H0476048U JP 11884990 U JP11884990 U JP 11884990U JP 11884990 U JP11884990 U JP 11884990U JP H0476048 U JPH0476048 U JP H0476048U
Authority
JP
Japan
Prior art keywords
heat dissipation
signal
laminated board
laminated substrate
signal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11884990U
Other languages
Japanese (ja)
Other versions
JP2508660Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11884990U priority Critical patent/JP2508660Y2/en
Publication of JPH0476048U publication Critical patent/JPH0476048U/ja
Application granted granted Critical
Publication of JP2508660Y2 publication Critical patent/JP2508660Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る半導体装置を示す斜視図
、第2図は本考案に係る半導体装置の要部を拡大
して示す断面図である。第3図a,bは本考案に
係る半導体装置をマザーボードに搭載した状態を
示す図で、同図aは平面図、同図bは縦断面図で
ある。第4図a,bは従来のPGA型の半導体装
置を示す図で、同図aは平面図、同図bは正面図
を示す。第5図はDIP型半導体装置を示す斜視
図、第6図はSOP型半導体装置を示す斜視図、
第7図は従来の半導体装置をプリント配線基板に
実装した状態を示す斜視図である。 11……半導体装置、12……信号配線積層基
板、13……放熱積層基板、14……LSIチツ
プ、15……信号ライン配線パターン、16……
貫通穴、17……信号端子、20……マザーボー
ド。
FIG. 1 is a perspective view showing a semiconductor device according to the present invention, and FIG. 2 is a sectional view showing an enlarged main part of the semiconductor device according to the present invention. Figures 3a and 3b are views showing the semiconductor device according to the present invention mounted on a motherboard, where figure a is a plan view and figure b is a longitudinal sectional view. FIGS. 4a and 4b are diagrams showing a conventional PGA type semiconductor device, with FIG. 4a showing a plan view and FIG. 4b showing a front view. FIG. 5 is a perspective view showing a DIP type semiconductor device, FIG. 6 is a perspective view showing an SOP type semiconductor device,
FIG. 7 is a perspective view showing a conventional semiconductor device mounted on a printed wiring board. DESCRIPTION OF SYMBOLS 11... Semiconductor device, 12... Signal wiring laminated board, 13... Heat dissipation laminated board, 14... LSI chip, 15... Signal line wiring pattern, 16...
Through hole, 17...signal terminal, 20...motherboard.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 伝熱材によつて形成され、信号端子が設けられ
てマザーボードに搭載される放熱用積層基板と、
前記信号端子に接続される配線パターンが設けら
れかつ半導体チツプが挿入される貫通穴が複数穿
設され、前記放熱用積層基板上に接合される信号
配線積層基板とを備え、テープキヤリアボンデイ
ングによつてリードが設けられた半導体チツプを
、リードを前記信号配線積層基板の配線パターン
に接続させて前記貫通穴に臨ませ、この半導体チ
ツプの底面を前記放熱用積層基板に接合したこと
を特徴とする半導体装置。
a heat dissipation laminated board formed of a heat transfer material, provided with signal terminals and mounted on a motherboard;
A signal wiring laminated substrate is provided with a wiring pattern connected to the signal terminal, a plurality of through holes are drilled into which semiconductor chips are inserted, and a signal wiring laminated substrate is bonded onto the heat dissipation laminated substrate, and is formed by tape carrier bonding. A semiconductor chip provided with leads is connected to the wiring pattern of the signal wiring laminated board so as to face the through hole, and the bottom surface of the semiconductor chip is bonded to the heat dissipation laminated board. Semiconductor equipment.
JP11884990U 1990-11-15 1990-11-15 Semiconductor device Expired - Lifetime JP2508660Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11884990U JP2508660Y2 (en) 1990-11-15 1990-11-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11884990U JP2508660Y2 (en) 1990-11-15 1990-11-15 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0476048U true JPH0476048U (en) 1992-07-02
JP2508660Y2 JP2508660Y2 (en) 1996-08-28

Family

ID=31866817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11884990U Expired - Lifetime JP2508660Y2 (en) 1990-11-15 1990-11-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2508660Y2 (en)

Also Published As

Publication number Publication date
JP2508660Y2 (en) 1996-08-28

Similar Documents

Publication Publication Date Title
JPH01105971U (en)
JPH0476048U (en)
JPS6059561U (en) semiconductor equipment
JPS6232551U (en)
JPS6232550U (en)
JPH0265349U (en)
JPS61134039U (en)
JPS6035569U (en) Chip carrier bump connection structure
JPS61205145U (en)
JPH03120052U (en)
JPS6214751U (en)
JPH01166565U (en)
JPS6025157U (en) semiconductor equipment
JPS6096831U (en) semiconductor chip
JPS61131870U (en)
JPH01179446U (en)
JPH0345649U (en)
JPS60125735U (en) Multi-chip hybrid integrated circuit
JPS5954938U (en) Multi-stage structure of leadless package
JPH024249U (en)
JPS6096895U (en) Integrated circuit heat dissipation structure
JPS62126842U (en)
JPS63201351U (en)
JPH0341934U (en)
JPS59180427U (en) hybrid integrated circuit device