JPH01123361U - - Google Patents

Info

Publication number
JPH01123361U
JPH01123361U JP2049288U JP2049288U JPH01123361U JP H01123361 U JPH01123361 U JP H01123361U JP 2049288 U JP2049288 U JP 2049288U JP 2049288 U JP2049288 U JP 2049288U JP H01123361 U JPH01123361 U JP H01123361U
Authority
JP
Japan
Prior art keywords
semiconductor device
tiers
bumps
wiring
stacking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2049288U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2049288U priority Critical patent/JPH01123361U/ja
Publication of JPH01123361U publication Critical patent/JPH01123361U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を説明するための半
導体装置の断面図、第２図は従来の一例を説明す
るための半導体装置の斜視図である。 １…フレキシブル配線基板、２…ＩＣベアチツ
プ、３…半田バンプ、４，４′…配線端部。 FIG. 1 is a sectional view of a semiconductor device for explaining an embodiment of the present invention, and FIG. 2 is a perspective view of a semiconductor device for explaining a conventional example. DESCRIPTION OF SYMBOLS 1... Flexible wiring board, 2... IC bare chip, 3... Solder bump, 4, 4'... Wiring end.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 厚さ０．２mm以下のＩＣベアチツプをフエイス
ダウンで搭載しバンプ接続したフレキシブルな有
機材からなる配線基板を二段以上に積み重ね、且
つ各基板間の必要な配線を電気的に接続したこと
を特徴とする半導体装置。 It is characterized by stacking two or more tiers of wiring boards made of flexible organic material on which IC bare chips with a thickness of 0.2 mm or less are mounted face-down and connected by bumps, and the necessary wiring between each board is electrically connected. semiconductor device.
JP2049288U 1988-02-17 1988-02-17 Pending JPH01123361U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2049288U JPH01123361U (en) 1988-02-17 1988-02-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2049288U JPH01123361U (en) 1988-02-17 1988-02-17

Publications (1)

Publication Number Publication Date
JPH01123361U true JPH01123361U (en) 1989-08-22

Family

ID=31236906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2049288U Pending JPH01123361U (en) 1988-02-17 1988-02-17

Country Status (1)

Country Link
JP (1) JPH01123361U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006028155A1 (en) * 2004-09-08 2006-03-16 Nec Corporation Module type electronic component and electronic device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6133258A (en) * 1984-07-25 1986-02-17 Matsushita Electric Ind Co Ltd Atomizer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6133258A (en) * 1984-07-25 1986-02-17 Matsushita Electric Ind Co Ltd Atomizer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006028155A1 (en) * 2004-09-08 2006-03-16 Nec Corporation Module type electronic component and electronic device

Similar Documents

Publication Publication Date Title
JPH01123361U (en)
CA2273223A1 (en) Chip-size package using a polyimide pcb interposer
JPH0270447U (en)
JPS6232551U (en)
JPS6214751U (en)
JPS6232550U (en)
JPH01176950U (en)
JPS63157934U (en)
JPS6153934U (en)
JPH0247034U (en)
JPH0229541U (en)
JPS62134254U (en)
JPH01118437U (en)
JPS62134240U (en)
JPS636742U (en)
JPS63147831U (en)
JPS59158336U (en) semiconductor equipment
JPS6413144U (en)
JPH0341934U (en)
JPS6035569U (en) Chip carrier bump connection structure
JPS62126842U (en)
JPS6359346U (en)
JPH0381643U (en)
JPS6379653U (en)
JPS62116563U (en)