CA2273223A1 - Chip-size package using a polyimide pcb interposer - Google Patents

Chip-size package using a polyimide pcb interposer Download PDF

Info

Publication number
CA2273223A1
CA2273223A1 CA002273223A CA2273223A CA2273223A1 CA 2273223 A1 CA2273223 A1 CA 2273223A1 CA 002273223 A CA002273223 A CA 002273223A CA 2273223 A CA2273223 A CA 2273223A CA 2273223 A1 CA2273223 A1 CA 2273223A1
Authority
CA
Canada
Prior art keywords
chip
size package
circuit board
printed circuit
bond pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002273223A
Other languages
French (fr)
Other versions
CA2273223C (en
Inventor
Robert W. Warren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Company
Robert W. Warren
Hughes Electronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US93983297A priority Critical
Priority to US08/939,832 priority
Application filed by Raytheon Company, Robert W. Warren, Hughes Electronics filed Critical Raytheon Company
Priority to PCT/US1998/020467 priority patent/WO1999017364A1/en
Publication of CA2273223A1 publication Critical patent/CA2273223A1/en
Application granted granted Critical
Publication of CA2273223C publication Critical patent/CA2273223C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

A chip-size package formed using a printed circuit board, preferably comprising polyimide. The chip-size package comprises an integrated circuit chip having a plurality of peripheral bond pads. The printed circuit board has a plurality of solder bumps formed on its top surface and a plurality of bond pads around its periphery. A layer of adhesive is used to secure the printed circuit board and the integrated circuit chip together. A plurality of wire bonds electrically connected between selected bond pads of the integrated circuit chip and the printed circuit board. An encapsulant encapsulates the wire bonds and bond pads of the integrated circuit chip and the printed circuit board.
CA002273223A 1997-09-29 1998-09-29 Chip-size package using a polyimide pcb interposer Expired - Lifetime CA2273223C (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US93983297A true 1997-09-29 1997-09-29
US08/939,832 1997-09-29
PCT/US1998/020467 WO1999017364A1 (en) 1997-09-29 1998-09-29 Chip-size package using a polyimide pcb interposer

Publications (2)

Publication Number Publication Date
CA2273223A1 true CA2273223A1 (en) 1999-04-08
CA2273223C CA2273223C (en) 2003-11-11

Family

ID=25473815

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002273223A Expired - Lifetime CA2273223C (en) 1997-09-29 1998-09-29 Chip-size package using a polyimide pcb interposer

Country Status (2)

Country Link
CA (1) CA2273223C (en)
WO (1) WO1999017364A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7531643B2 (en) 1997-09-11 2009-05-12 Chugai Seiyaku Kabushiki Kaisha Monoclonal antibody inducing apoptosis
US7696325B2 (en) 1999-03-10 2010-04-13 Chugai Seiyaku Kabushiki Kaisha Polypeptide inducing apoptosis
US8034903B2 (en) 2000-10-20 2011-10-11 Chugai Seiyaku Kabushiki Kaisha Degraded TPO agonist antibody
JP2004279086A (en) 2003-03-13 2004-10-07 Konica Minolta Holdings Inc Radiation image conversion panel and method for manufacturing it
JP5085322B2 (en) 2005-06-10 2012-11-28 中外製薬株式会社 Pharmaceutical composition containing sc (Fv) 2
EP1870458B1 (en) 2005-03-31 2018-05-09 Chugai Seiyaku Kabushiki Kaisha sc(Fv)2 STRUCTURAL ISOMERS
CN101237890A (en) 2005-06-10 2008-08-06 中外制药株式会社 Stabilizer for protein preparation comprising meglumine and use thereof
US7659151B2 (en) 2007-04-12 2010-02-09 Micron Technology, Inc. Flip chip with interposer, and methods of making same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3487524B2 (en) * 1994-12-20 2004-01-19 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
US5633785A (en) * 1994-12-30 1997-05-27 University Of Southern California Integrated circuit component package with integral passive component
US5714800A (en) * 1996-03-21 1998-02-03 Motorola, Inc. Integrated circuit assembly having a stepped interposer and method

Also Published As

Publication number Publication date
CA2273223C (en) 2003-11-11
WO1999017364A1 (en) 1999-04-08

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MKEX Expiry

Effective date: 20181001