TW503555B - Semiconductor package with stacked flip chip and wire bonded upper die - Google Patents

Semiconductor package with stacked flip chip and wire bonded upper die Download PDF

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Publication number
TW503555B
TW503555B TW090115097A TW90115097A TW503555B TW 503555 B TW503555 B TW 503555B TW 090115097 A TW090115097 A TW 090115097A TW 90115097 A TW90115097 A TW 90115097A TW 503555 B TW503555 B TW 503555B
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TW
Taiwan
Prior art keywords
wafer
substrate
patent application
scope
item
Prior art date
Application number
TW090115097A
Other languages
Chinese (zh)
Inventor
Melissa Siow-Liu Lee
Edwin Fontecha
Bruce Symons
Original Assignee
Advanced Micro Devices Inc
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Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of TW503555B publication Critical patent/TW503555B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

A circuit assembly is formed with a lower flip-chip die, a wire bonded upper die stacked on the lower die and a non-conductive adhesive therebetween. The combination of a lower flip-chip die and upper wire bonded die enables efficient electrical connection of both dies with a similar size to a chip carrying substrate thereby enhancing flexibility and circuit density.

Description

A7 —___ B7__ 五、發明說明（1 ) [發明領域] (請先閱讀背面之注意事項再填寫本頁) 本發明係關於一種半導體封裝結構技術。本發明具特 別用途於含有多重半導體晶片之半導體封裝結構及連接疊 層晶片至基板。 [背景技術說明] 先進固態電子裝置對具有增加功能性、密度及表現之 積體電路裝置負有連續需求。為反應此需求，發展出包括 有一系列分離組件直接黏附於印刷電路板基板之多重晶片 模組。多重晶片裝置得有利增加電路密度伴隨有信號傳遞 速度及整體裝置重量之改善。 典型積體電路裝置以接置丨或更多晶片於陶瓷或有機 如礬土電路化基板而電子化封裝，有時稱為封裝件。利用 銲線以電性連接每晶片上之輸入/輪出（ί〇)接觸墊至電路 化封裝件&板上之對應接觸墊及對應扇出電路。然後典型 接置所得封裝件於印刷電路板（pCB)上，以及利用pCB上 之電路以與其他此類封裝件及/或接置於pCB上之電子組 件電性偶合。 一經 濟 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 1知電路化基板含有2或更多扇出電路之路線層。彼 等扇出電路之層係、以熟知為貫孔之機械鑽孔彼此電性連 接，貫孔係以導電材質如鶴電鍍及/或填充而成。某些孔延 伸自扇出電路之層分別至晶片載體基板上之地區，其上接 置有鏵球以形成格栅陣列，因此產生，，球栅陣列，，一詞。銲 球係機械及電性連接至對應PCB上之銲接觸塾。 連續增加大規模積體電路晶片之尺寸導致對應增加於 91836 503555 經濟部智慧財產局員工消費合作社印製 2 A7 五、發明說明（2 ) 晶片所需製之I/O連接數。1/0連接數之增加導致製程複雜 性之增加因薄銲線需人工或機械自動置於晶片墊與封裝件 基板間以作電性連接之用。 為降低銲線製程之成本及複雜性以改善電性表現，故 發展出所謂覆晶技術。於覆晶技術中，於主要上表面具塾 «又置之塊狀積體電路係反轉其上表面朝下，即，，覆”，故使 得封裝件基板上墊與相配之構件直接偶合。直接連接係以 植長形成於積體電路1/0端上之銲塊而製成。覆塊積體電 路係不同地稱為覆晶。覆晶係對齊於封裝件基板及所有連 接係以回銲銲料而同時形成。 趨向增加功能性、密度及表現之趨勢亦導致超載半導 體片於封裝件基板之實行。此實行於相似尺寸之疊晶情 形下難以進行，因難以施行銲線至位於下晶片上表面之接 合塾。然而，若下晶片製為大於上晶片，則可容納於基板 及/或PCB上之晶片數會降低。因此，使用疊晶以達增加 功能性、密度及表現之目的會有所限制。 、因此，存有包括電路裝置並具有實質上相同尺寸疊晶 之半導體封裝件之需求。亦存有包括電路裝置並具有實質 上相同尺寸疊晶之製造封裝半導體裝置方法之需求。 [發明概述] 本發明之一優點係為包括疊層之上及下晶片之電路裝 置’其中下晶片之尺寸係實質上相同或小於上晶片之尺 寸。 本發明之另一優點係為製造包括疊層之上及下晶片 用甲國國家標準(CNS)A4規^^^^ 91836 V '· ' LL ' - - · --------^—------ (請先閱讀背面之注意事項再填寫本頁) A7 __B7 五、發明說明（3 之電路裝置之方法，其中下晶片之尺寸係實質上相同或小 於上晶片之尺寸。 本發月之額外優點及特徵將部分述於下述說明中及 部分對熟習此技術者依檢視下述而為顯而易知或可學得自 本發明之實行中。本發明之優點可了解及得於如於附 請專利範圍中所特定指出。 根據本發明，前述及其他優點部分以電路裝置達成， 該電路裝置包括：封裝件基板，具有主表面；覆晶第一晶 2 ’具有上表面、下表面及侧表面，該第_晶片之下表面 ^位於亚以回銲銲球而電性連接至基板之主表面上；以及 第一曰曰片，具有上表面、下表面及側表面，該第二晶片以 其下表面定位於第一晶片上並藉接合銲線至第二晶片上表 面之接合墊以電性連接至基板之主表面。 本發明之另一方面係為製造電路裝置之方法，該方法 包括：提供具有主表面之封裝件基板；定位覆晶第一晶片， 2第曰曰片具有上表面、具有銲球之下表面及側表面，使 銲球係於基板之主表面上；加熱以接合及藉回鋒鋒球以電 性連接第-晶片至基板之主表面上之導體；定位第二晶 片，此第二晶片具有含有接合墊之上表面、下表面及側表 面，使第二晶片之下表面係於第_晶片之上表面上；以及 藉接合銲線至接合墊以電性連接第二晶片至基板，婷線則 電性連接至基板之主表面上之導體。 本發明之實施例包括以電介接合材質如非導性樹脂 而接合第二晶片至第一晶片。本發明之實施例復包括使用 H献度適时關家標準（CNS)A4規格(2i〇7ii7^7 3 裝 91836 503555 A7 五、發明說明（4 ) 實質上具有相同於上晶片尺寸之下曰 卜曰日片，及具有小於上晶 片尺寸之下晶片。 本發明之額外優點將對熟習此枯 、 自此技術者自下述仔細說 明而為顯而易知者，其中僅以用以音 用以實施本發明之最佳模式 之說明而顯示及闡明本發明之較佳實施例。需了解，本發 明得為其他及不同實施例並其某些特點得於多方明顯方: 作修飾’其皆不悖離本發明之範疇 祀可因此，圖示及說明係 視為實際說明而非為限制之用。 [圖式簡單說明] 第1圖示本發明實施例之疊晶結構之剖視圖。 [元件符號說明] 10 基板 11 下晶片 12 銲球 13 電介質黏著劑 14 上晶片 15 銲線 16 接合墊 17 樹月旨 18 焊球 [發 明之詳細說明] 本發明發表並解決電性連接上及下晶片至封裝件基板 之問題’其中下晶片係實質上相同或甚至小於上晶片：尺 寸，使得以改善設計彈性及增加電路密度。此目的係以策 =性使用下晶片與具有接合墊於上晶片上表面之晶片之覆 晶而得。下覆晶晶片與鋒線接合上晶片之策略性組合使得 Z使用具有實質上相同尺寸之第一與第二晶片，因此於第 一與第二晶片之側表面間實質上並無重疊。本發日月之實施 關家標準（CNS) A4 ⑵〇 X 297 公复)--—--____ 91836 ---------—丨4 (請先閱讀背面之注意事項再填寫本頁) tT·---------線. 經濟部智慧財產局員工消費合作社印製 4 刈3555 *經 濟 w，部 智 慧 財 產 局 消 費 合 社 印 製 B7 五、發明說明（5 ) =至以得以使用具有尺寸小於上晶片之下晶片而提供5 彈性’因此上晶片之側表面與下晶片之側表面重疊。』 ，片可藉利用習知電介黏著劑如非導性_而接合於下蓋 ，非導性樹㈣如得自位於加州聖地牙哥之量子材料公 司之 QMI 536。 本發明之實施例包括以銲塾或塊狀接觸點之型式而定 位具有端子於其下表面之覆晶下晶片於封裝件基板上表面 上。然後進行銲料回銲以接合及電性連接覆晶下晶片至電 路化封裝件基板。接著施用電介接合材質於覆晶下晶片之 上表面及接置於下晶片上表面之上銲線接合晶片。上晶片 含有多數接合塾於其上表面上。然後進行鲜線接合以電性 連接銲線至上晶片上表面上之接合塾。隨後方法依包含以 封裝樹脂包覆疊晶等習知實施法進行。 而了解除於此所述I’用；^本發明之種種實施例之材 質及接合方法俱為習知，因此為不混淆本發明，故不予此 贅述。例如’用於本發明實施例之適合習知封裝件電路化 基板典型包括貫穿其中之電鐘貫孔及於底面上之銲球以接 合至習知PCB。 本發明之實施例係示於第！圖包括電路化封裝件基板 10,此基板10具有藉由回銲銲球12而接置於其上之覆i 下晶片11。上晶片14係藉由電介質黏著劑13接合於下^ 晶晶片1卜上晶片14含有多數接合墊16於其上表面上 接合墊16係藉由接合銲線15以電性連接至電路化封裝子 基板1 〇之導體（未圖示）。疊晶係以樹脂〗7包覆。銲球^ 91836 1 ! Μ------— t---------線. (請先閱讀背面之注意事項再填寫本頁) n i ϋ - A7 五、發明說明（6 係於基板1〇之下表面上以接置於PCB。 本發月有利得以經膂有效之方式製造疊晶結構，其中 下’片係貫質上相同或小於上晶片之尺寸。本發明適用於 f何多種形式之積體電路封裝件。本發明適用於包括多重 晶片之高及低密度積體電路封裝模組。 准以上所述者，僅係用以說明本發明之具體實施例而已， 需了解舉凡熟習該項技藝者在未脫離本發明所指示之精神 與原理下所完成之一切等效改變或修飾，仍應皆由後述之 專利範圍所涵蓋。 (請先閒讀背面之注意事項再填寫本頁) I適 11,又 V 7a ♦..S - 一紙一本 NS (C 準 標 家 國 3 I祕 I楚 、、二 1297 I訂--------- Φ.A7 —___ B7__ 5. Description of the invention (1) [Field of invention] (Please read the notes on the back before filling out this page) The present invention relates to a semiconductor packaging structure technology. The present invention is particularly useful for a semiconductor package structure containing multiple semiconductor wafers and for connecting a laminated wafer to a substrate. [Background Description] Advanced solid-state electronic devices have a continuous demand for integrated circuit devices with increased functionality, density, and performance. In response to this demand, a multi-chip module including a series of discrete components directly adhered to a printed circuit board substrate has been developed. Multi-chip devices can advantageously increase circuit density with improvements in signal transmission speed and overall device weight. A typical integrated circuit device is electronically packaged by placing one or more wafers on a ceramic or organic circuit board such as alumina, sometimes called a package. The bonding pads are used to electrically connect the input / roll-out (ί) contact pads on each chip to the corresponding contact pads and corresponding fan-out circuits on the circuitized package & board. The resulting package is then typically mounted on a printed circuit board (pCB), and the circuits on the pCB are used to electrically couple with other such packages and / or electronic components placed on the pCB. Once printed by the Economic and Intellectual Property Office's Consumer Cooperatives, it is known that the circuitized substrate contains 2 or more routing layers for fan-out circuits. The layers of their fan-out circuits are electrically connected to each other by mechanical drilling, which is known as through-holes. The through-holes are made of conductive materials such as crane plating and / or filling. Some holes extend from the layers of the fan-out circuit to areas on the wafer carrier substrate, respectively, with balls attached to form a grid array, and thus the term, ball grid array, is generated. The solder balls are mechanically and electrically connected to the solder contacts 对应 on the corresponding PCB. Continuously increasing the size of the large-scale integrated circuit chip results in a corresponding increase in the number of I / O connections printed by 91836 503555 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. A description of the invention (2) The number of I / O connections required for the chip. The increase in the number of 1/0 connections leads to an increase in the complexity of the process, because the thin bonding wires need to be manually or mechanically placed between the wafer pad and the package substrate for electrical connection. In order to reduce the cost and complexity of the wire bonding process to improve electrical performance, so-called flip-chip technology has been developed. In flip-chip technology, a block integrated circuit with a «positioned on the main top surface is reversed with its top surface facing down, ie, covering", so that the pad on the package substrate is directly coupled with the matching component. The direct connection is made of a solder bump that is formed on the 1/0 end of the integrated circuit. The integrated circuit is called a flip chip. The flip chip is aligned with the package substrate and all the connection systems. Simultaneous formation of solder. The tendency to increase functionality, density, and performance has also led to the implementation of overloaded semiconductor wafers on package substrates. This implementation is difficult to perform in the case of stacked wafers of similar size, as it is difficult to implement bonding wires to the lower wafer Bonding on the upper surface. However, if the lower wafer is made larger than the upper wafer, the number of wafers that can be accommodated on the substrate and / or PCB will be reduced. Therefore, the use of stacked wafers for the purpose of increasing functionality, density, and performance will There are restrictions. Therefore, there is a need for a semiconductor package including a circuit device and having substantially the same size stacked die. There is also a manufacturing package including a circuit device and has substantially the same size stacked. Requirements for semiconductor device methods. [Summary of the Invention] One advantage of the present invention is a circuit device including stacked upper and lower wafers, where the size of the lower wafer is substantially the same or smaller than the size of the upper wafer. Another aspect of the invention The advantage is that it includes the National Standard A (CNS) A4 for the manufacture of laminated upper and lower wafers. ^^^^ 91836 V '·' LL '--· -------- ^ ------ -(Please read the precautions on the back before filling this page) A7 __B7 V. Description of the invention (3 The method of the circuit device, where the size of the lower chip is substantially the same or smaller than the size of the upper chip. Extra for this issue month The advantages and features will be described in part in the following description and part will be obvious to those skilled in the art by looking at the following or can be learned from the practice of the present invention. The advantages of the present invention can be understood and obtained as According to the invention, the foregoing and other advantages are partially achieved by a circuit device, which includes: a package substrate having a main surface; a flip-chip first crystal 2 'having an upper surface, a lower surface and Side surface, the lower surface of the first wafer ^ It is located on the main surface of the Asian-Year reflow solder ball and is electrically connected to the substrate; and the first chip has an upper surface, a lower surface and a side surface, and the second chip is positioned on the first chip with its lower surface. A bonding pad bonding the bonding wire to the upper surface of the second wafer is electrically connected to the main surface of the substrate. Another aspect of the present invention is a method for manufacturing a circuit device, the method includes: providing a package substrate having a main surface. ; Positioning the flip-chip first wafer, 2 The first chip has an upper surface, a lower surface and a side surface of the solder ball, so that the solder ball is tied to the main surface of the substrate; heating to join and borrow the front ball for electrical properties A conductor connecting the first wafer to the main surface of the substrate; positioning a second wafer having an upper surface, a lower surface, and a side surface including a bonding pad, so that the lower surface of the second wafer is tied to the first wafer On the surface; and the second chip is electrically connected to the substrate by the bonding wire to the bonding pad, and the Ting line is electrically connected to the conductor on the main surface of the substrate. An embodiment of the present invention includes bonding a second wafer to a first wafer with a dielectric bonding material such as a non-conductive resin. The embodiment of the present invention includes the use of H.degree. Timely family standard (CNS) A4 specification (2i〇7ii7 ^ 7 3 installation 91836 503555 A7. 5. Description of the invention (4) has substantially the same size as the upper wafer. Bu Yue Japanese films, and lower wafers with a size smaller than the upper wafer. The additional advantages of the present invention will be apparent to those skilled in the art from the following detailed explanation, which is only used for sound The preferred embodiments of the present invention are shown and clarified by the description of the best mode for carrying out the present invention. It should be understood that the present invention may be other and different embodiments and some of its characteristics are obvious from many parties: Modifications' Without deviating from the scope of the present invention, therefore, the illustrations and descriptions are to be regarded as practical descriptions rather than limiting. [Brief Description of the Drawings] The first diagram illustrates a cross-sectional view of a stacked structure of an embodiment of the present invention. [Element Explanation of Symbols] 10 Substrate 11 Lower wafer 12 Solder ball 13 Dielectric adhesive 14 Upper wafer 15 Welding wire 16 Bonding pad 17 Tree moon purpose 18 Solder ball [Detailed description of the invention] The present invention discloses and solves the electrical connection between the upper and lower wafers to Encapsulation The problem of the substrate 'where the lower wafer is substantially the same or even smaller than the upper wafer: size, so as to improve design flexibility and increase circuit density. This purpose is to strategically use the lower wafer and the wafer with a bonding pad on the upper surface of the upper wafer It is obtained by flip chip. The strategic combination of the lower flip chip wafer and the front wire bonding upper wafer makes Z use the first and second wafers having substantially the same size, and therefore substantially merges between the side surfaces of the first and second wafers. No overlap. This issue of the Sun and Moon implementation of the Family Standard (CNS) A4 X〇X 297 public reply) -----____ 91836 --------- 丨 4 (Please read the precautions on the back first (Fill in this page again) tT · --------- line. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 刈 3555 * Economic w, printed by the Consumer Cooperative of the Ministry of Intellectual Property Bureau B7 5. Description of the invention ( 5) = so as to be able to use a wafer having a size smaller than that of the lower wafer to provide 5 elasticity 'so the side surface of the upper wafer overlaps the side surface of the lower wafer. The film can be bonded to the lower cover by using a conventional dielectric adhesive such as non-conductive, such as the QMI 536 from Quantum Materials Corporation in San Diego, California. Embodiments of the present invention include positioning a flip-chip lower chip having terminals on its lower surface in the form of solder pads or bulk contact points on the upper surface of a package substrate. Solder reflow is then performed to bond and electrically connect the flip-chip die to the circuitized package substrate. Then, a dielectric bonding material is applied to the upper surface of the flip-chip lower wafer and a bonding wire is bonded to the upper surface of the lower wafer to bond the wafer. The upper wafer contains most bonds on its upper surface. Fresh wire bonding is then performed to electrically connect the bonding wires to the bonding pads on the upper surface of the upper wafer. The subsequent method is performed according to a conventional implementation method including encapsulating a stacked crystal with an encapsulating resin. The materials used in the various embodiments of the present invention and the joining methods are well known. Therefore, in order not to confuse the present invention, they are not repeated here. For example, a conventional circuit board for a suitable package used in an embodiment of the present invention typically includes an electrical clock penetrating hole therethrough and a solder ball on the bottom surface for connection to a conventional PCB. An embodiment of the present invention is shown at the first! The figure includes a circuitized package substrate 10 having a cover wafer 11 placed thereon by reflowing solder balls 12. The upper wafer 14 is bonded to the lower wafer by a dielectric adhesive 13. The upper wafer 14 contains a plurality of bonding pads 16 on its upper surface. The bonding pads 16 are electrically connected to the circuitized package by bonding wires 15 A conductor (not shown) of the substrate 10. The stacked crystal system is covered with a resin 7. Solder ball ^ 91836 1! Μ ------— t --------- line. (Please read the precautions on the back before filling out this page) ni ϋ-A7 V. Description of the invention (6 series It is placed on the PCB on the lower surface of the substrate 10. This month can be used to fabricate a stacked structure in an efficient and effective manner, where the lower sheet is substantially the same in size or smaller than the size of the upper wafer. The present invention is applicable to What are the various types of integrated circuit package. The present invention is suitable for high and low density integrated circuit package modules including multiple chips. The above mentioned ones are only used to explain the specific embodiments of the present invention. For example, all equivalent changes or modifications made by those skilled in the art without departing from the spirit and principles instructed by the present invention should still be covered by the scope of patents described below. (Please read the precautions on the back before filling in (This page) I suitable for 11, and V 7a ♦ ..S-one paper, one NS (C quasi-standard home country 3 I secret I, I, 1297 I order --------- Φ.

Claims (1)

503555 A8 B8 C8 D8 1. 曰曰 申δ青專利範圍 一種電路裝置，包括： 封裝基板，具有主表面； 覆晶第U，具有上表面、下表面及側表面， 該第一晶片之下表面定位於並藉回銲銲球以電性連接 至基板之主表面上；以及 第二晶片，具有上表面、下表面及側表面，該第 二晶^其下表面定位於s —晶片上並藉接合鲜線至 第二晶片上表面之接合墊以電性連接至基板之主表 面0 2·如申請專利範圍第i項之電路裝置，復包括於第 片上表面與第二晶片下表面間之電介接合材質。 3·如申請專利範圍帛·2項之電路裝置，纟中該接合 包括非導性樹脂。 4·如申請專利範圍第2項之電路裝置，其中該第一與第 一晶片係實質上尺寸相同，使該第一與第二晶片之側 表面得實質上有同等範圍而無實質重疊於其間。 5·如申請專利範圍第2項之電路裝置，其中該第一晶片 係小於第二晶片，使第二晶片之側表面與第一晶片 側表面重疊。 6· —種包括如申請專利範圍第2項之電路裝置之车 裝置，其特徵在於該基板係接合於印刷電路板。 7. —種製造電路裝置之方法，該方法係包括·· 提供一封裝基板，該基板具有主表面； 定位覆晶第一晶片，具有上表面、具有銲球之 , 表面及侧表面，使銲球得於基板之主表面上; 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Μ ------------- (請先閱讀背面之注意事項再填寫本頁) 經 ’濟 部 慧 財 產 局 員 工 消 費 合 作 社 印 製 7 91836 503555 A8 B8 CS —— ____D8_____— 六、申請專利範圍 加熱以接合及藉回銲鍀球以電性連接第一晶片至 基板之主表面上之導體； 疋位第二晶片，此第二晶片具有含有接合塾之上表 面、下表面及側表面，使第二晶片之下表面得於第一晶 片之上表面上；以及 藉接合銲線至接合墊以電性連接第二晶片至基 板’銲線則電性連接至基板之主表面上之導體。 8·如申請專利範圍第7項之方法，復包括藉電介接合材質 以接合該第二晶片至該第一晶片。 9·如申請專利範圍第8項之方法，其中該接合材質包括非 導電性樹腊。 10·如申請專利範園第8項之方法，其中該第一與第二晶片 係實質上尺寸相同，使該第一與第二晶片之侧表面得實 質上有同等範圍而無實質重疊於其間。 11，如申請專利範圍第8項之方法，其中該第一晶片係小於 第二晶片，使第二晶片之側表面與第一晶片之側表面重 叠0 經濟部智慧財產局員工消費合作钍印製 12·如申請專利範圍第11項之方法，復包括結合及電性連 接該基板至印刷電路板。 界紙張尺度適用中國國家標進（CNS)A4規格(210 X 297公爱 91836503555 A8 B8 C8 D8 1. The scope of the patent application for a delta δ patent includes: a package substrate with a main surface; a flip chip U with an upper surface, a lower surface, and a side surface; the lower surface of the first wafer is positioned The second wafer has an upper surface, a lower surface, and a side surface, and the lower surface is positioned on the s-wafer and bonded by bonding. The bonding pads from the fresh wire to the upper surface of the second wafer are electrically connected to the main surface of the substrate. 0 2 · If the circuit device of the scope of application for item i of the patent application includes a dielectric between the upper surface of the first wafer and the lower surface of the second wafer Joint material. 3. If the circuit device of the scope of patent application 帛 · 2, the joint in 纟 includes a non-conductive resin. 4. The circuit device according to item 2 of the scope of patent application, wherein the first and first wafers are substantially the same size, so that the side surfaces of the first and second wafers have substantially the same range without substantially overlapping therebetween. . 5. The circuit device according to item 2 of the scope of patent application, wherein the first wafer is smaller than the second wafer such that the side surface of the second wafer overlaps the side surface of the first wafer. 6. A vehicle device including a circuit device such as the second item in the scope of patent application, characterized in that the substrate is bonded to a printed circuit board. 7. A method of manufacturing a circuit device, the method comprising: providing a package substrate having a main surface; positioning a flip-chip first wafer having an upper surface, a solder ball, a surface, and a side surface to enable soldering The ball can be on the main surface of the substrate; this paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Μ ------------- (Please read the precautions on the back first (Fill in this page again) Printed by 'Economics and Consumer Cooperatives of the Ministry of Economic Affairs and Social Welfare Bureau 7 91836 503555 A8 B8 CS —— ____D8_____ — 6. Application for patent scope heating to bond and borrow solder balls to electrically connect the first chip to the substrate A conductor on the main surface; a second wafer having an upper surface, a lower surface, and a side surface including a bonding wafer, so that the lower surface of the second wafer is on the upper surface of the first wafer; and The bonding wire is bonded to the bonding pad to electrically connect the second chip to the substrate. The bonding wire is electrically connected to the conductor on the main surface of the substrate. 8. The method according to item 7 of the patent application, further comprising borrowing a dielectric bonding material to bond the second wafer to the first wafer. 9. The method of claim 8 in which the bonding material includes non-conductive wax. 10. The method according to item 8 of the patent application park, wherein the first and second wafers are substantially the same size, so that the side surfaces of the first and second wafers have substantially the same range without substantial overlap therebetween. . 11. The method according to item 8 of the scope of patent application, wherein the first wafer is smaller than the second wafer, so that the side surface of the second wafer overlaps the side surface of the first wafer. 12. The method according to item 11 of the scope of patent application, which includes combining and electrically connecting the substrate to the printed circuit board. Paper size is applicable to China National Standard (CNS) A4 (210 X 297 public love 91836
TW090115097A 2000-06-29 2001-06-21 Semiconductor package with stacked flip chip and wire bonded upper die TW503555B (en)

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US62158000A 2000-07-21 2000-07-21

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JPH11219984A (en) * 1997-11-06 1999-08-10 Sharp Corp Semiconductor device package, its manufacture and circuit board therefor

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