JPH0691310B2 - Wiring board manufacturing method - Google Patents
Wiring board manufacturing methodInfo
- Publication number
- JPH0691310B2 JPH0691310B2 JP27380587A JP27380587A JPH0691310B2 JP H0691310 B2 JPH0691310 B2 JP H0691310B2 JP 27380587 A JP27380587 A JP 27380587A JP 27380587 A JP27380587 A JP 27380587A JP H0691310 B2 JPH0691310 B2 JP H0691310B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- copper
- wiring board
- conductor
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は大形コンピュータなどの電子機器に使用するセ
ラミック多層配線基板の製造方法に関する。The present invention relates to a method for manufacturing a ceramic multilayer wiring board used for electronic equipment such as a large computer.
従来のこの種のセラミック多層配線基板は、その上に形
成する多層配線層における導体配線として、絶縁層形成
時には酸化せず、かつ電気抵抗が低いという特性を有す
る金が使用されているか、または電気抵抗を更に低くす
るため、銅が使用されているかいずれかである。In this type of conventional ceramic multilayer wiring board, gold is used as a conductor wiring in a multilayer wiring layer formed thereon, which has the characteristic that it does not oxidize when an insulating layer is formed and has a low electric resistance. Copper is either used to further reduce resistance.
第3図は従来の製造方法によって製造した配線基板の一
例を工程順に示す断面図である。FIG. 3 is a sectional view showing an example of a wiring board manufactured by a conventional manufacturing method in the order of steps.
第3図(a)に示すように、セラミック多層基板の絶縁
層23の上に銅層21を形成し、その上にニッケル層22を形
成した導体配線は、最上層に金層25を形成している。こ
れにチップ30(第3図(d)参照)を接続するため、第
3図(b)に示すように導体配線間に絶縁層29を形成
し、導体配線の上部において絶縁層29の間に形成される
ヴィアホール24にはんだ28を注入し(第3図(c)参
照)、このはんだ28にチップ30の端子を接続するという
手段を用いている。絶縁層29の材料として、イオン結合
性の感光基を導入した感光性ポリイミドが常用される。
イオン結合性の感光基を導入した感光性ポリイミドは、
感光基が熱処理工程で容易に分解するためである。感光
基が残留すると、絶縁層の機械的強度が低下してしま
う。イオン結合性の感光基を導入した感光性ポリイミド
以外の材料では、感光基が分解し難く、熱処理工程後も
感光基が残留しやすい。As shown in FIG. 3 (a), the conductor wiring in which the copper layer 21 is formed on the insulating layer 23 of the ceramic multilayer substrate and the nickel layer 22 is formed thereon, the gold layer 25 is formed on the uppermost layer. ing. In order to connect the chip 30 (see FIG. 3 (d)) to this, an insulating layer 29 is formed between the conductor wires as shown in FIG. 3 (b), and between the insulating layers 29 on the upper part of the conductor wires. The solder 28 is injected into the formed via hole 24 (see FIG. 3C), and the terminals of the chip 30 are connected to the solder 28. As a material for the insulating layer 29, a photosensitive polyimide having an ionically-bonded photosensitive group introduced therein is commonly used.
The photosensitive polyimide introduced with an ionic bonding photosensitive group,
This is because the photosensitive group is easily decomposed in the heat treatment process. If the photosensitive group remains, the mechanical strength of the insulating layer will decrease. With materials other than photosensitive polyimide having an ionic bonding photosensitive group introduced therein, the photosensitive group is difficult to decompose and the photosensitive group is likely to remain after the heat treatment step.
上述のように、従来のセラミック多層配線基板上に形成
される多層配線層における導体配線は、金または銅が使
用されているが、銅の方が価格も安価な上に電気抵抗も
低いために望ましいが、銅は酸化されやすいという欠点
があり、またイオン結合性の感光基を導入した感光性の
絶縁樹脂を使用した場合、銅と錯体を作りやすく、この
ため銅の配線の上に薄いクロムの層を設けてこれの改善
を計る必要があるが、これはヴィア部の抵抗が高くなる
という欠点がある。また部品搭載のために基板の最上層
に銅の端子を形成し、その上に、上記の感光性材料によ
る絶縁層でソルダーダムを形成してはんだをリフローし
ようとするとき、はんだの塗布性が悪いという欠点もあ
る。一方金は、高価であり、従って配線基板のコストを
上昇させるという欠点を有している。As described above, gold or copper is used for the conductor wiring in the multilayer wiring layer formed on the conventional ceramic multilayer wiring board, but copper is cheaper and has lower electric resistance. Although it is desirable, copper has a drawback that it is easily oxidized, and when a photosensitive insulating resin having an ionic bonding photosensitive group is used, it is easy to form a complex with copper, which results in thin chromium on the copper wiring. It is necessary to provide this layer to improve this, but this has a drawback that the resistance of the via portion becomes high. In addition, when a copper terminal is formed on the uppermost layer of the board for component mounting and a solder dam is formed on it with an insulating layer made of the above-mentioned photosensitive material to reflow solder, the solder coatability is poor. There is also a drawback. Gold, on the other hand, has the drawback of being expensive and thus increasing the cost of the wiring board.
本発明の配線基板の製造方法は、導体配線を形成すると
き、電気抵抗の低い銅層と、その銅層の表面に銅の酸化
を防ぐための薄い金属膜とを形成し、絶縁層を形成する
ときに、各層の導体配線間の相互の導通を確保するため
ヴィアホールを形成し、そのヴィアホールに現れている
導体配線の薄い金属膜を酸またはアルカリによるウエッ
トエッチ法またはイオンビーム等のドライエッチ法等で
除去して銅の表面を露出してから、次の層を形成するよ
うにしたものである。すなわち、本発明の配線基板の製
造方法は、配線基板の絶縁層上に銅層を形成し、前記銅
層の上に金属薄膜層を形成して導体配線を構成し、前記
導体配線間にイオン結合性の感光基を導入した感光性材
料による絶縁層を形成し、この絶縁層の間の開口部に露
出した前記導体配線の前記金属薄膜層をエッチング法に
よって除去して前記銅層を露出させることを含んで構成
される。In the method for manufacturing a wiring board of the present invention, when a conductor wiring is formed, a copper layer having a low electric resistance and a thin metal film for preventing the oxidation of copper are formed on the surface of the copper layer to form an insulating layer. At this time, a via hole is formed to ensure mutual conduction between the conductor wirings of each layer, and the thin metal film of the conductor wiring appearing in the via hole is wet-etched with an acid or alkali or dried by ion beam or the like. The next layer is formed after the copper surface is exposed by removing it by an etching method or the like. That is, the method for manufacturing a wiring board of the present invention comprises forming a copper layer on an insulating layer of the wiring board, forming a metal thin film layer on the copper layer to form a conductor wiring, and forming an ion between the conductor wirings. An insulating layer made of a photosensitive material having a bonding photosensitive group introduced is formed, and the metal thin film layer of the conductor wiring exposed in the openings between the insulating layers is removed by an etching method to expose the copper layer. It is configured to include that.
次に本発明の実施例について説明する。 Next, examples of the present invention will be described.
第1図は、本発明の第一の実施例によって製造した配線
基板の一例を工程順に示す断面図である。第1図(a)
において、セラミック多層板の絶縁層3上に銅層1を形
成し、この銅層1の上にニッケル層2を形成して構成し
た導体配線7の間を、第1図(b)に示すように、イオ
ン結合性の感光基を導入した感光性ポリイミドによる絶
縁層9によって覆ってヴィアホール4を形成する。次に
第1図(c)に示すように、導体配線7上の薄いニッケ
ル層2を酸またはアルカリでエッチングした後、イオン
ビームなどのドライエッチングを行って銅層1を露出さ
せ、次に第1図(d)に示すように、この銅層1の上に
銅層5とニッケル層8とを形成して上層導体配線8を形
成する。ニッケル層6は、銅層5の酸化防止のために設
けられる。チップは上層導体配線8に接続される。この
とき、後述する第2の実施例の工程に従い、ニッケル層
6の一部が除去される。ニッケル層6が除去された部分
にハンダが供給される。このハンダの上にチップが搭載
される。FIG. 1 is a sectional view showing an example of a wiring board manufactured according to the first embodiment of the present invention in the order of steps. Fig. 1 (a)
In Fig. 1 (b), between the conductor wiring 7 formed by forming the copper layer 1 on the insulating layer 3 of the ceramic multilayer plate and forming the nickel layer 2 on the copper layer 1 as shown in Fig. 1 (b). Then, the via hole 4 is formed by being covered with an insulating layer 9 made of a photosensitive polyimide into which an ionic bonding photosensitive group is introduced. Next, as shown in FIG. 1 (c), the thin nickel layer 2 on the conductor wiring 7 is etched with an acid or an alkali, and then a dry etching such as an ion beam is performed to expose the copper layer 1. As shown in FIG. 1D, a copper layer 5 and a nickel layer 8 are formed on the copper layer 1 to form an upper conductor wiring 8. The nickel layer 6 is provided to prevent oxidation of the copper layer 5. The chip is connected to the upper conductor wiring 8. At this time, part of the nickel layer 6 is removed according to the process of the second embodiment described later. Solder is supplied to the portion where the nickel layer 6 is removed. A chip is mounted on this solder.
第2図は、本発明の第二の実施例によって製造した配線
基板の一例を工程順に示す断面図である。FIG. 2 is a sectional view showing an example of a wiring board manufactured according to the second embodiment of the present invention in the order of steps.
本実施例では、導体配線を電子部品(チップ)等を接続
のための端子として直接用いるようにしている。すなわ
ち第2図(a)に示すように、絶縁層13の上に銅層11を
形成し、その上にニッケル層12を形成して導体配線17を
構成する。次に第2図(b)に示すように、導体配線17
の間を、イオン結合性の感光基を導入した感光性材料に
よる絶縁層19を形成し、導体配線17の上部に開口部(ヴ
ィアホール)14を形成する。次に第2図(c)に示すよ
うに導体配線17上の薄いニッケル層12をイオンビーム等
でドライエッチングして除去したのち、第2図(d)に
示すように、その上にはんだ18を供給し、次に第2図
(e)に示すようにはんだ18上にチップ30の端子を搭載
して接続する。In this embodiment, the conductor wiring is directly used as a terminal for connecting an electronic component (chip) or the like. That is, as shown in FIG. 2A, the copper layer 11 is formed on the insulating layer 13, and the nickel layer 12 is formed on the copper layer 11 to form the conductor wiring 17. Next, as shown in FIG. 2 (b), the conductor wiring 17
An insulating layer 19 made of a photosensitive material into which an ionic bonding photosensitive group is introduced is formed between the spaces, and an opening (via hole) 14 is formed above the conductor wiring 17. Next, as shown in FIG. 2 (c), the thin nickel layer 12 on the conductor wiring 17 is removed by dry etching with an ion beam or the like, and then solder 18 is formed thereon as shown in FIG. 2 (d). Then, as shown in FIG. 2 (e), the terminals of the chip 30 are mounted on the solder 18 and connected.
上述の実施例ではいずれも薄い金属膜として、ニッケル
を用いた例を示したが、ニッケルの代りにクロムまたは
パラジウムまたはチタンまたはアルミニウムを用いるこ
とができる。In each of the above-described embodiments, nickel is used as the thin metal film, but chromium, palladium, titanium, or aluminum can be used instead of nickel.
以上説明したように、本発明の配線基板の製造方法は、
銅を主体とする導体配線とイオン結合性の感光基が導入
された感光性の絶縁材料とを組合せて使用でき、このと
きの銅表面の酸化を防止することができると共に、上層
に形成した場合でも絶縁材料でソルダーダムを形成した
後にはんだがのりやすい導体配線を形成することができ
るという効果がある。As described above, the wiring board manufacturing method of the present invention is
The conductor wiring mainly composed of copper and a photosensitive insulating material having an ionic bonding photosensitive group introduced therein can be used in combination, and at the time, the copper surface can be prevented from being oxidized and formed in the upper layer. However, there is an effect that it is possible to form the conductor wiring on which the solder easily sticks after forming the solder dam with the insulating material.
第1図は本発明の第一の実施例によって製造した配線基
板の一例を工程順に示す断面図、第2図は本発明の第二
の実施例によって製造した配線基板の一例を工程順に示
す断面図、第3図は従来の製造方法によって製造した配
線基板の一例を工程順に示す断面図である。 1・5・11・21……銅層、2・6・12・22……ニッケル
層、3・9・13・19・23・29……絶縁層、4・14・24…
…ヴィアホール、7・17……導体配線、8……上層導体
配線、18・28……はんだ、25……金層、30……チップ。FIG. 1 is a sectional view showing an example of a wiring board manufactured according to the first embodiment of the present invention in the order of steps, and FIG. 2 is a sectional view showing an example of a wiring board manufactured according to the second embodiment of the present invention in the order of steps. 3 and 4 are sectional views showing an example of a wiring board manufactured by a conventional manufacturing method in the order of steps. 1, 5, 11, 21 ... Copper layer, 2, 6, 12, 22, ... Nickel layer, 3, 9, 13, 19, 23, 29, ... Insulating layer, 4, 14, 24 ...
… Via hole, 7 ・ 17 …… conductor wiring, 8 …… upper layer conductor wiring, 18 ・ 28 …… solder, 25 …… gold layer, 30 …… chip.
Claims (1)
銅層の上に金属薄膜層を形成して導体配線を構成し、前
記導体配線間にイオン結合性の感光基を導入した感光性
材料による絶縁層を形成し、この絶縁層の間の開口部に
露出した前記導体配線の前記金属薄膜層をエッチング法
によって除去して前記銅層を露出させることを含むこと
を特徴とする配線基板の製造方法。1. A conductor layer is formed by forming a copper layer on an insulating layer of a wiring board, and forming a metal thin film layer on the copper layer, and introducing an ion-bonding photosensitive group between the conductor wires. Forming an insulating layer of the photosensitive material, and removing the metal thin film layer of the conductor wiring exposed in the opening between the insulating layers by an etching method to expose the copper layer. Method of manufacturing wiring board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27380587A JPH0691310B2 (en) | 1987-10-28 | 1987-10-28 | Wiring board manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27380587A JPH0691310B2 (en) | 1987-10-28 | 1987-10-28 | Wiring board manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01115196A JPH01115196A (en) | 1989-05-08 |
JPH0691310B2 true JPH0691310B2 (en) | 1994-11-14 |
Family
ID=17532817
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27380587A Expired - Lifetime JPH0691310B2 (en) | 1987-10-28 | 1987-10-28 | Wiring board manufacturing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0691310B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2760360B2 (en) * | 1990-03-17 | 1998-05-28 | 富士通株式会社 | Solder bump and its manufacturing method |
JP5540276B2 (en) * | 2011-03-31 | 2014-07-02 | Tdk株式会社 | Electronic component built-in substrate and manufacturing method thereof |
-
1987
- 1987-10-28 JP JP27380587A patent/JPH0691310B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH01115196A (en) | 1989-05-08 |
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