CN110120355A - A method of reducing fan-out package warpage - Google Patents
A method of reducing fan-out package warpage Download PDFInfo
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- CN110120355A CN110120355A CN201910446517.6A CN201910446517A CN110120355A CN 110120355 A CN110120355 A CN 110120355A CN 201910446517 A CN201910446517 A CN 201910446517A CN 110120355 A CN110120355 A CN 110120355A
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- Prior art keywords
- stress relief
- fan
- out package
- hole
- relief grooves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/02—Positioning or observing the workpiece, e.g. with respect to the point of impact; Aligning, aiming or focusing the laser beam
- B23K26/06—Shaping the laser beam, e.g. by masks or multi-focusing
- B23K26/067—Dividing the beam into multiple beams, e.g. multifocusing
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/38—Removing material by boring or cutting
- B23K26/382—Removing material by boring or cutting by boring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
A method of fan-out package warpage is reduced, after the injection step of fan-out package, before injected plastics material solidification, gets stress relief hole or stress relief grooves array in packaging body designated position.The present invention proposes a kind of method for reducing fan-out package warpage according to above content, by in the prefabricated stress relief hole in packaging body designated position or stress relief grooves array, to block the lateral stress transmission path during injected plastics material cooling meat, reach control internal stress, and then reduces encapsulating structure warpage.
Description
Technical field
The present invention relates to chip encapsulation technology field more particularly to a kind of methods and knot for reducing fan-out package warpage
Structure.
Background technique
With miniaturization of electronic products and integrated trend, the densification of microelectronic packaging technology is in electricity of new generation
Mainstream is increasingly becoming on sub- product.In order to comply with the hair of the products such as the development of electronic product of new generation, especially mobile phone, notebook
Exhibition, chip is higher to density, speed faster, smaller, the more low direction of cost develops.Fan-out square chip level package technology
The appearance of (Fan-out Panel Level Package, FOPLP), as fan-out-type Wafer level packaging (Fanout
Wafer Level Package, FOWLP) upgrade technique, possess broader development prospect.With traditional wire bonding core
Piece is compared, and fan-out package greatly increases the number of pins of chip, reduces package dimension, is simplified encapsulation step, is shortened core
The distance between piece and support plate improve chip functions.It is short, high with support 10nm or less manufacturing process chip, interconnection path
Integrated level, ultrathin, high reliability, the advantages such as high heat-sinking capability.
The basic working procedure of fan-out package are as follows: interim bonding glue is covered on support plate, chip is molded and is consolidated
Change, remove interim bonding glue and support plate, covers dielectric layer (ABF) and again wiring layer (RDL).Such process, which is also brought, to be fanned out to
Two big basic problems of type encapsulation, i.e. die drift and buckling behavior.In injection phase, if temporarily bonding glue is connect with chip
Pine is crossed, will result in die drift.If in conjunction with tension, and can be brought to the process of the interim bonding glue of subsequent removal and support plate tired
Difficulty, and will cause more high internal stress and warpage.In encapsulation process, due to the coefficient of thermal expansion of the materials such as plastic cement, silicon and metal
Difference, will cause warpage and internal stress.Wherein, the difference of chip and injected plastics material thermal expansion coefficient keeps injected plastics material cooled
The warpage generated in journey is the main reason that big plate grade is fanned out to that warpage generates in encapsulation technology.
How to improve warpage issues becomes the major issue of current fan-out package and High Density Integration microelectronics system,
Need Development of Novel is fanned out to packaging method and technology.
Summary of the invention
It is an object of the invention to propose a kind of method for reducing fan-out package warpage, by packaging body designated position
Prefabricated stress relief hole or stress relief grooves array, so that the lateral stress during blocking injected plastics material cooling meat is transmitted
Path reaches control internal stress, and then reduces encapsulating structure warpage.
To achieve this purpose, the present invention adopts the following technical scheme:
A method of fan-out package warpage is reduced, after the injection step of fan-out package, is solidified in injected plastics material
Before, stress relief hole or stress relief grooves array are got in packaging body designated position.
Preferably, the interval of chip or module is arranged in the position of the stress relief hole or stress relief grooves, i.e.,
Subsequent cutting position.
Preferably, the stress relief hole be through-hole or blind hole.
Preferably, the stress relief grooves are through slot or shallow slot.
Preferably, the stress relief hole or stress relief grooves pass through high energy density laser processing or total focusing principle
It laser machines, confocal laser processing is suitable for carrying out precise positioning punching to package interior, and laser is to single stress
The mode of the punching of relief hole or stress relief grooves includes primary punching or repeatedly punching.
Preferably, the range of the fan-out package is that plate grade or wafer scale are fanned out to encapsulation.
Preferably, the stress relief grooves are straight troughs or with cambered curved groove.
Preferably, the distribution of the stress relief hole or stress relief grooves is symmetrical array, divergence expression or non-
Symmetrical pattern
Preferably, the depth bounds of the stress relief hole or stress relief grooves be in 0 to 100% package thickness into
Row adjustment.
Preferably, be when getting stress relief hole or stress relief grooves array respectively in packaging body injected plastics material side and
The side of wiring layer carries out two sides and punches or beat simultaneously slot again；
The side of the side of packaging body injected plastics material and again wiring layer is different pattern.
Beneficial effects of the present invention: 1, by getting stress release in packaging body designated position before injected plastics material solidifies
The mode of hole or stress relief grooves array realizes improvement warpage of packaging assembly, reduces the purpose of encapsulation internal stress, improves encapsulation matter
Amount and reliability；2, the interval of chip or module is arranged in the position of stress relief hole or stress relief grooves array, will not
Subsequent cutting and chip performance are impacted.
Detailed description of the invention
Fig. 1 is a kind of process cross section structure schematic diagram for the method for reducing fan-out package warpage of the present invention.
Fig. 2 is using a kind of array slot three-dimensional structure schematic diagram for the method for reducing fan-out package warpage of the present invention.
Fig. 3 is to be shown using the cross recess three-dimensional structure of the manufacture of another method for reducing fan-out package warpage of the invention
It is intended to.
Fig. 4 is to be shown using the well word slot three-dimensional structure of the manufacture of another method for reducing fan-out package warpage of the invention
It is intended to.
Fig. 5 is to be shown using the circle hole groove three-dimensional structure of the manufacture of another method for reducing fan-out package warpage of the invention
It is intended to.
Wherein: the hot releasing layer 3- dielectric layer 4- of 1- support plate 2- wiring layer 5- chip 6- injected plastics material 7- stress relief grooves again
71- stress relief hole 8- soldered ball
Specific embodiment
To further illustrate the technical scheme of the present invention below with reference to the accompanying drawings and specific embodiments.
As shown in Figs. 1-5, a method of fan-out package warpage is reduced, after the injection step of fan-out package,
Before injected plastics material 6 solidify, stress relief hole 71 or stress relief grooves 7 are got in packaging body designated position, reaches release stress,
The purpose for reducing warpage, improves package quality and reliability.
Packaging body designated position, including in the side of injected plastics material 6, perhaps again in the side of wiring layer 4 or packaging body
Portion's specific position is punched.The form packet of stress relief hole 71 or stress relief grooves 7 on punching direction expands continuous hole
A series of or discontinuous holes.
Preferably, the interval of chip 5 or module is arranged in the position of the stress relief hole 71 or stress relief grooves 7
Place, i.e., subsequent cutting position will not impact 5 performance of chip.
Preferably, the stress relief hole 71 be through-hole perhaps the blind hole stress relief grooves 7 be through slot or shallowly
Slot, the setting of depth depend on the geometry and physical property that are fanned out to encapsulation chip 5 Yu injected plastics material 6.
Preferably, the stress relief hole 71 or stress relief grooves 7 are processed by high energy density laser, are not drawn as far as possible
Enter extra energy and residual stress.
The method of the prefabricated stress relief hole 71 or stress relief grooves 7 is equally applicable under the conditions of other similar encapsulation
Stress release and reduce warpage.
The structure manufactured using a kind of method of reduction fan-out package warpage,
6 one side position of injected plastics material is equipped with stress relief hole 71 or stress relief grooves 7.
Preferably, the interval of chip or module is arranged in the position of the stress relief hole 71 or stress relief grooves 7,
I.e. subsequent cutting position.
Preferably, the stress relief hole 71 be through-hole or blind hole.
Preferably, the stress relief grooves 7 are through slot or shallow slot.
Preferably, the stress relief hole 71 or stress relief grooves 7 are processed or are copolymerized by high energy density laser and is burnt
Principle laser machines, and confocal laser processing is suitable for carrying out precise positioning punching to package interior, and laser is to single
The mode of the punching of stress relief hole 71 or stress relief grooves 7 includes primary punching or repeatedly punching.
The stress relief hole 71 or stress relief grooves 7 are processed by high energy density laser.
Preferably, the range of the fan-out package is that plate grade or wafer scale are fanned out to encapsulation.
Preferably, the stress relief grooves 7 are straight troughs or with cambered curved groove.
Preferably, the distribution of the stress relief hole 71 or stress relief grooves 7 be symmetrical array, divergence expression or
The pattern of asymmetric
Preferably, the depth bounds of the stress relief hole 71 or stress relief grooves 7 are in 0 to 100% package thickness
Inside it is adjusted.
It preferably, is respectively in packaging body injected plastics material one when getting 7 array of stress relief hole 71 or stress relief grooves
The side of side and again wiring layer carries out two sides and punches or beat simultaneously slot；
The side of the side of packaging body injected plastics material and again wiring layer is different pattern.
The shape of stress relief hole 71 and stress relief grooves 7, depth, density and pattern distribution can be customized；
The density of stress relief hole 71 and stress relief grooves 7 can require to be designed with arrangement according to specific encapsulation, can
To be selection different density and pattern distribution.
Embodiment one
Consider that an area is the big plate grade fan-out package process of 320 × 320mm2, wherein the area of one single chip 5 is
5 × 5mm2, one single chip 5 include that the area of fan-out area is the package example of 8 × 8mm2.In the Shooting Technique of fan-out package
Afterwards, before the solidification of injected plastics material 6, (structure at this time is followed successively by support plate 1, hot releasing layer 2, dielectric layer 3, again cloth from top to bottom
Line layer 4, chip 5, melting injected plastics material 6), stress is got at 6 back side of injected plastics material of each 5 interval of chip using laser
7 array of release groove, 6 layers of depth penetrates injected plastics material, single slot length is 6mm, and width is 100 microns.It is solid in injected plastics material 6
After change, carry out support plate 1 separate (debonding), deposition Underbump metallization layer (UBM deposition), etching (etching),
A series of subsequent encapsulating process such as ball bar grid array (BGA mount) are embedded in, final fan-out package structure is formed.
Embodiment two
Consider that an area using die first method (being routed in after injection moulding process again) is 120 × 120mm2's
Big plate grade fan-out package process, wherein the area of one single chip 5 is 5 × 5mm2, and one single chip 5 includes the area of fan-out area
For the package example of 8 × 8mm2.After the Shooting Technique of fan-out package, before the solidification of injected plastics material 6, (structure at this time
It is followed successively by support plate 1, hot releasing layer 2, chip 5, melting injected plastics material 6 from top to bottom), using laser between every 3 chips 5
7 array of stress relief grooves is got every 6 back side of injected plastics material at place, and 6 layers of depth penetrates injected plastics material, single slot length is
20mm, width are 100 microns.After the solidification of injected plastics material 6, subsequent grinding (grinding) is carried out, support plate 1 separates
(debonding), patterning is passivated (Patterned passivation), is routed (RDL), deposition Underbump metallization layer again
A series of subsequent encapsulation works such as (UBM deposition), etching (etching), insertion ball bar grid array (BGA mount)
Skill forms final fan-out package structure.
Embodiment three
Consider that an area using die first method (being routed in after injection moulding process again) is 120 × 120mm2's
Big plate grade fan-out package process, wherein the area of one single chip 5 is 5 × 5mm2, and one single chip 5 includes the area of fan-out area
For the package example of 8 × 8mm2.After the Shooting Technique of fan-out package, before the solidification of injected plastics material 6, (structure at this time
It is followed successively by support plate 1, hot releasing layer 2, chip 5, melting injected plastics material 6 from top to bottom), using laser between each chip 5
Stress release circle hole groove array is got every 6 back side of injected plastics material at place, 6 layers of depth penetrates injected plastics material, single circle hole groove is straight
Diameter is 2 millimeters.After the solidification of injected plastics material 6, subsequent grinding (grinding) is carried out, support plate 1 separates (debonding), figure
Caseization is passivated (Patterned passivation), again wiring layer 4 (RDL), deposition Underbump metallization layer (UBM
Deposition), a series of subsequent encapsulating process such as (etching), insertion ball bar grid array (BGA mount), shape are etched
At final fan-out package structure.
The technical principle of the invention is described above in combination with a specific embodiment.These descriptions are intended merely to explain of the invention
Principle, and shall not be construed in any way as a limitation of the scope of protection of the invention.Based on the explanation herein, the technology of this field
Personnel can associate with other specific embodiments of the invention without creative labor, these modes are fallen within
Within protection scope of the present invention.
The technical principle of the invention is described above in combination with a specific embodiment.These descriptions are intended merely to explain of the invention
Principle, and shall not be construed in any way as a limitation of the scope of protection of the invention.Based on the explanation herein, the technology of this field
Personnel can associate with other specific embodiments of the invention without creative labor, these modes are fallen within
Within protection scope of the present invention.
Claims (8)
1. a kind of method for reducing fan-out package warpage, it is characterised in that: after the injection step of fan-out package, be molded
Before material solidification, stress relief hole or stress relief grooves array are got in packaging body designated position.
2. a kind of method for reducing fan-out package warpage according to claim 1, it is characterised in that: the stress release
The interval of chip or module, i.e., subsequent cutting position is arranged in hole or the position of stress relief grooves.
3. a kind of method for reducing fan-out package warpage, it is characterised in that: the stress relief hole is through-hole or blind hole, institute
Stating stress relief grooves is that perhaps the depth bounds of the shallow slot stress relief hole or stress relief grooves are 0 to 100% to through slot
It is adjusted in package thickness.
4. a kind of method for reducing fan-out package warpage according to claim 1, it is characterised in that:
The stress relief hole or stress relief grooves are processed by high energy density laser or focusing principle laser machines altogether
At confocal laser processing is suitable for carrying out precise positioning punching to package interior, and laser is to single stress relief hole or answers
The mode of the punching of power release groove includes primary punching or repeatedly punching.
5. a kind of method for reducing fan-out package warpage according to claim 1, it is characterised in that: the fan-out-type envelope
The range of dress is that plate grade or wafer scale are fanned out to encapsulation.
6. a kind of method for reducing fan-out package warpage according to claim 1, it is characterised in that:
The stress relief grooves are straight troughs or with cambered curved groove.
7. a kind of method for reducing fan-out package warpage according to claim 1, it is characterised in that: the stress release
The distribution of hole or stress relief grooves is the pattern of symmetrical array, divergence expression or asymmetric.
8. a kind of method for reducing fan-out package warpage according to claim 1, it is characterised in that:
The mode for getting stress relief hole or stress relief grooves array includes respectively in packaging body injected plastics material side and cloth again
The side of line layer carries out two sides and punches or beat simultaneously slot；
Stress relief hole or stress relief grooves packaging body injected plastics material side and again the side of wiring layer is identical patterns
Or the different pattern separately designed.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910446517.6A CN110120355A (en) | 2019-05-27 | 2019-05-27 | A method of reducing fan-out package warpage |
| PCT/CN2019/112777 WO2020237987A1 (en) | 2019-05-27 | 2019-10-23 | Method for reducing fan-out package warpage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910446517.6A CN110120355A (en) | 2019-05-27 | 2019-05-27 | A method of reducing fan-out package warpage |
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| Publication Number | Publication Date |
|---|---|
| CN110120355A true CN110120355A (en) | 2019-08-13 |
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| CN201910446517.6A Pending CN110120355A (en) | 2019-05-27 | 2019-05-27 | A method of reducing fan-out package warpage |
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| WO (1) | WO2020237987A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020237987A1 (en) * | 2019-05-27 | 2020-12-03 | 广东工业大学 | Method for reducing fan-out package warpage |
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2019
- 2019-05-27 CN CN201910446517.6A patent/CN110120355A/en active Pending
- 2019-10-23 WO PCT/CN2019/112777 patent/WO2020237987A1/en active Application Filing
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| CN102169879A (en) * | 2011-01-30 | 2011-08-31 | 南通富士通微电子股份有限公司 | Highly integrated wafer fan-out packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020237987A1 (en) * | 2019-05-27 | 2020-12-03 | 广东工业大学 | Method for reducing fan-out package warpage |
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| WO2020237987A1 (en) | 2020-12-03 |
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Application publication date: 20190813 |