CN101131992A - Multi-chip stacking type packaging structure - Google Patents
Multi-chip stacking type packaging structure Download PDFInfo
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- CN101131992A CN101131992A CNA2006101119225A CN200610111922A CN101131992A CN 101131992 A CN101131992 A CN 101131992A CN A2006101119225 A CNA2006101119225 A CN A2006101119225A CN 200610111922 A CN200610111922 A CN 200610111922A CN 101131992 A CN101131992 A CN 101131992A
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
The present invention provides a multi-chip-stacked package, and includes: a substrate set with several metal terminals and a multi-chip-stacked package are provided; the multi-chip-stacked package is fixed on substrate, of which active surface of each chip is set with several welding pads, and each chip is set with insulating layer on its back; a clinging layer combines the active surface of each chip and the insulating layer set on the back of the other chip to form stack structure; several metal wires joins the several welding pads on the several chips and the several metal terminals on the substrate.
Description
Technical field
The present invention relates to a kind of multi-chip stack packaging structure, and be particularly related to a kind of radian that in multi-chip stack structure, reduces plain conductor, and in the adhesion layer of multi-chip stack structure, add encapsulating structure with approximate sphere with contrary wire bonding process and insulating barrier.
Background technology
In recent years, semi-conductive last part technology is all carrying out three dimensions (Three Dimension; Encapsulation 3D) reaches big relatively semiconductor integrated level (Integrated) or capacity of memory etc. in the hope of utilizing minimum area.In order to reach this purpose, the mode that present stage has been developed use chip stack (chip stacked) is reached three dimensions (Three Dimension; Encapsulation 3D).
In known technology, the storehouse mode of chip is that a plurality of chips are stacked on the substrate mutually, uses wire bonding process (wire bonding process) that a plurality of chips are connected with substrate then.Fig. 1 represents known generalized section with storehouse cake core encapsulating structure of identical or close chip size.As shown in Figure 1, known storehouse cake core encapsulating structure 100 comprises base plate for packaging (packagesubstrate) 110, chip 120a, chip 120b, sept (spacer) 130, many leads 140 and packing colloid (encapsulant) 150.Have a plurality of weld pads 112 on the base plate for packaging 110, and also have a plurality of weld pad 122a and 122b respectively on chip 120a and the 120b, wherein weld pad 122a and 122b are arranged on chip 120a and the 120b with kenel (peripheral type) on every side.Chip 120a is arranged on the base plate for packaging 110, and chip 120b is arranged at the top of chip 120a by sept 130.The two ends of part lead 140 are connected to weld pad 112 and 122a by wire bonding process, so that chip 120a is electrically connected on base plate for packaging 110.And the two ends of other parts lead 140 also are connected to weld pad 112 and 122b by wire bonding process, so that chip 120b is electrically connected on base plate for packaging 110.Be arranged on the base plate for packaging 110 as for 150 of packing colloids, and coat these leads 140, chip 120a and 120b.
Because weld pad 122a and 122b are arranged on chip 120a and the 120b with kenel on every side, therefore the direct carries chips 120b of chip 120a, so sept 130 must be set between chip 120a and 120b, make between chip 120a and the 120b at a distance of suitable distance, in order to the carrying out of follow-up wire bonding process.Yet the use of sept 130 but causes the thickness of known storehouse cake core encapsulating structure 100 to reduce further.
In addition, similarly known technology as shown in Figure 2, the same use has certain thickness wall 130, so that between two chips at a distance of suitable distance, carrying out in order to follow-up wire bonding process, in addition, in order to reduce the radian of plain conductor 140, more weld pad 13 ends at chip form salient point 141 (stud bump).Clearly, the storehouse packaged type of this adding wall 130 can't reduce the thickness of storehouse encapsulation, thus its chip-count of energy storehouse be restricted.
In the stack package structure among Fig. 1 and Fig. 2, also having a common problem, is exactly the position is set can't goes up square chip (120b of sept 130; 20) whole support is so when carrying out wire bonding (wire bonding), if when chip is too thin, may make chip cause fragmentation (wafer broken) in the wire bonding process.Therefore, use chip in the stack package structure of sept 130 be need have certain thickness, so make that more this stack package structure can't the too many chip of storehouse.In addition, in the process of carrying out chip stack, also square chip (120b might take place; 20) contact with following Square wire 140 and cause problem of short-circuit.In addition, in stack package structure with sept 130, after the technology of finishing the wire bonding connection, just carry out sealing (molding), but because up and down the distance of chip chamber only has the thickness of sept 130 or wall 50, therefore may in the spacing of chip up and down, form bubble (void), when this bubble is expanded by high temperature, then can cause the be full of cracks (crack) of adhesive body.
Summary of the invention
In view of the shortcoming and the problem of the chip stack mode described in the background of invention, the invention provides a kind of mode of multi-chip stack, the akin chip stack of a plurality of sizes is become a kind of three-dimensional encapsulating structure.
Main purpose of the present invention provides a kind of encapsulating structure of multi-chip stack, promptly form insulating barrier at the back side of each chip, so can be on lead with chip and storehouse, and the thickness that makes multi-chip stack encapsulation of the present invention have higher encapsulation integrated level and approach.
Another main purpose of the present invention provides a kind of multi-chip stack packaging structure, makes chip be difficult for causing fragmentation in wire bonding process.
A main purpose more of the present invention provides a kind of multi-chip stack packaging structure, makes the gap between the stack chip can not produce bubble behind sealing adhesive process.
Of the present invention also have a main purpose providing have the structure that is similar to spherical insulator a kind of adding in the multi-chip stack encapsulation, in order to keep the spacing between stack chip in adhesion layer.
In view of the above, the invention provides a kind of encapsulating structure of multi-chip stacking type, comprise: a substrate and a multi-chip stack structure that is formed by a plurality of chip stacks that is provided with a plurality of metal endpoints is provided, and multi-chip stack structure is fixed on the substrate, wherein the active surface of each chip in the multi-chip stack structure is provided with on the back side of a plurality of weld pads and each chip insulating barrier is set, then the active surface of each chip is engaged with insulating barrier on another chip back between a plurality of chips simultaneously, also a plurality of weld pads on a plurality of chips are electrically connected with a plurality of metal endpoints on the substrate by many strip metals lead with the formation stack architecture by an adhesion layer.
The present invention then provides a kind of encapsulating structure of multi-chip stacking type, comprise: provide one to be provided with a plurality of metal endpoints substrates and a multi-chip stack structure that forms by a plurality of chip stacks, and multi-chip stack structure is fixed on the substrate, wherein the active surface of each chip in the multi-chip stack structure is provided with on the back side of a plurality of weld pads and each chip insulating barrier is set, simultaneously then be mixed with a plurality of approximate spherical bodies between a plurality of chips and the active surface of each chip engaged with insulating barrier on another chip back, also a plurality of weld pads on a plurality of chips are electrically connected with a plurality of metal endpoints on the substrate by many strip metals lead with the formation stack architecture in wherein adhesion layer by one.
The present invention then provides a kind of encapsulating structure of multi-chip stacking type again, comprise: lead frame, be the interior pin and the chip bearing of relatively arranging, and the chip bearing is between the interior pin of a plurality of relative arrangements, and the chip bearing have upper surface and lower surface by a plurality of one-tenth; And multi-chip stack structure that forms by a plurality of chip stacks, and multi-chip stack structure is fixed in the upper surface of lead frame, wherein the active surface of each chip in the multi-chip stack structure is provided with on the back side of a plurality of weld pads and each this chip insulating barrier is set, simultaneously between a plurality of chips by being mixed with a plurality of approximate spherical bodies in adhesion layer wherein, the active surface of this each chip engaged with insulating barrier on another chip back to form stack architecture also passes through many strip metals lead a plurality of weld pads on a plurality of chips are electrically connected with the interior pin of this lead frame.
The present invention continues to provide a kind of encapsulating structure of multi-chip stacking type again, comprise: lead frame, be the interior pin and the chip bearing of arranging relatively by a plurality of one-tenth, and the chip bearing is between the interior pin of a plurality of relative arrangements, and the chip bearing has upper surface and with respect to the lower surface of this upper surface; And a plurality of multi-chip stack structures, each multi-chip stack structure forms by a plurality of chip stacks, and a plurality of multi-chip stack structures are fixed in the upper surface and the lower surface of lead frame respectively, wherein the active surface of each chip in the multi-chip stack structure back side that is provided with a plurality of weld pads and each chip is provided with insulating barrier, and the active surface of each chip is engaged with insulating barrier on another chip back to form stack architecture and by many strip metals lead pin in a plurality of weld pads on a plurality of chips and lead frame a plurality of to be electrically connected in wherein adhesion layer by being mixed with a plurality of approximate spherical bodies between a plurality of chip.
The present invention then provides a kind of method of chip stack encapsulation, and its step is as follows: at first, provide substrate, and substrate is provided with a plurality of metal endpoints; First chip then is provided, the active surface of first chip be provided with a plurality of weld pads and overleaf on insulating barrier is set, and the insulating barrier on the chip is connected with substrate; Then, provide heater to carry out baking process after, to solidify the insulating barrier of first chip back; Then, re-use contrary wire bonding process many strip metals lead is provided, and be electrically connected a plurality of weld pads on first chip and a plurality of metal endpoints on the substrate with many strip metals lead; Follow again, form first adhesion layer on the active surface of first chip; Then provide second chip again, its back side is provided with insulating barrier, and insulating barrier is engaged with first adhesion layer; Then, provide heater, in order to solidify first adhesion layer; Follow again, many strip metals lead is provided, make many strip metals lead be electrically connected a plurality of weld pads on second chip and a plurality of metal endpoints on the substrate; Then, repeat abovementioned steps again, promptly can form multi-chip stack structure of the present invention.
The present invention then provides the method for another kind of chip stack encapsulation again, its step is as follows: at first, lead frame is provided, and interior pin and a chip bearing that this lead frame is arranged relatively by a plurality of one-tenth are formed, and the chip bearing is between the interior pin that a plurality of one-tenth are arranged relatively; First chip then is provided, the active surface of first chip be provided with a plurality of weld pads and overleaf on insulating barrier is set, affixed with the insulating barrier and the chip bearing of chip back then; Provide heater to carry out the baking program then, in order to solidify the insulating barrier of first chip back; Use contrary wire bonding process that many strip metals lead is provided afterwards, and be electrically connected pin in a plurality of on a plurality of weld pads on first chip and the lead frame with many strip metals lead; Follow again, form first adhesion layer on the active surface of first chip, simultaneously, in this first adhesion layer, can optionally add a plurality of approximate spheres; Then provide second chip again, and the active surface of second chip be provided with a plurality of weld pads and overleaf on insulating barrier is set, and this insulating barrier is engaged with first adhesion layer; Then, provide heater, in order to solidify first adhesion layer; Then, re-use contrary wire bonding process many strip metals lead is provided, make many strip metals lead be electrically connected pin in a plurality of on a plurality of weld pads on second chip and the lead frame; Repeat abovementioned steps so again, promptly can form multi-chip stack structure of the present invention.
The present invention then provides the method for another kind of chip stack encapsulation again, its step is as follows: at first, lead frame is provided, interior pin and a chip bearing that this lead frame is arranged relatively by a plurality of one-tenth are formed, and the chip bearing is between the interior pin that a plurality of one-tenth are arranged relatively, simultaneously, the chip bearing has upper surface and lower surface; First chip then is provided, the active surface of first chip be provided with a plurality of weld pads and overleaf on insulating barrier is set, affixed with the upper surface of the insulating barrier of chip back and chip bearing then; Provide heater to carry out the baking program then, in order to solidify the insulating barrier of first chip back; Use contrary wire bonding process that many strip metals lead is provided afterwards, and be electrically connected pin in a plurality of on a plurality of weld pads on first chip and the lead frame with many strip metals lead; Follow again, form first adhesion layer on the active surface of first chip; Then provide second chip again, and insulating barrier is set on the back side of second chip, and this insulating barrier is engaged with first adhesion layer; Then, provide heater, in order to solidify first adhesion layer; Then, re-use contrary wire bonding process many strip metals lead is provided, make many strip metals lead be electrically connected pin in a plurality of on a plurality of weld pads on second chip and the lead frame; At this moment, with the anti-turnback of lead frame; Then, provide the 3rd chip again, the active surface of the 3rd chip be provided with a plurality of weld pads and overleaf on insulating barrier is set, and affixed with the lower surface of the insulating barrier of chip back and chip bearing; Equally, provide heater,, then, use contrary wire bonding process that many strip metals lead is provided, and be electrically connected pin in a plurality of on a plurality of weld pads on the 3rd chip and the lead frame with many strip metals lead in order to solidify insulating barrier; Follow again, form second adhesion layer on the active surface of the 3rd chip; Then provide the four-core sheet again, insulating barrier is set on the back side of four-core sheet, the insulating barrier of chip back is engaged with second adhesion layer; Then, provide heater, in order to solidify second adhesion layer; Then, re-use contrary wire bonding process many strip metals lead is provided, make many strip metals lead be electrically connected pin in a plurality of on a plurality of weld pads on the four-core sheet and the lead frame; Repeat abovementioned steps so again, promptly can form multi-chip stack structure of the present invention.
Description of drawings
Fig. 1 is the schematic diagram of prior art;
Fig. 2 is the schematic diagram of prior art;
Fig. 3 A～Fig. 3 B is the plane and the generalized section of chip of the present invention;
Fig. 4 is the cutaway view of stack architecture of the present invention;
Fig. 5 is the stack architecture cutaway view with approximate sphere of the present invention;
Fig. 6 for of the present invention be the stack architecture cutaway view of substrate with the lead frame;
Fig. 7 for of the present invention be the stack architecture cutaway view of substrate with the lead frame;
Fig. 8 for of the present invention be the stack architecture cutaway view of substrate with the lead frame;
Fig. 9 for of the present invention be the stack architecture cutaway view of substrate with the lead frame;
Figure 10 for of the present invention be the stack architecture cutaway view of substrate with the lead frame;
The main element description of symbols
13: weld pad
100: storehouse cake core encapsulating structure
110: base plate for packaging
112,122a, 122b: weld pad
120a, 120b: chip
130: sept
140: lead
141: metal salient point
150: packing colloid
200 (a, b, c, d): chip
210: the chip active surface
220: chip back
230: adhesion layer
240: weld pad
30: chip stack structure
300: substrate
310: metal endpoints
320: plain conductor
330: salient point
340 (a, b, c): adhesion layer
360: approximate sphere
370: packing colloid
40: chip stack structure
400: lead frame
410: interior pin
420: the chip bearing
422: the upper surface of chip bearing
424: the lower surface of chip bearing
50: chip stack structure
60: chip stack structure
70: chip stack structure
Embodiment
The present invention is a kind of mode of using multi-chip stack in this direction of inquiring into, and the akin chip stack of a plurality of sizes is become a kind of three-dimensional encapsulating structure.In order to understand the present invention up hill and dale, detailed packaging structure and encapsulation step thereof will be proposed in following description.Apparently, execution of the present invention does not limit the specific details that the person of ordinary skill in the field had the knack of of the mode of chip stack.On the other hand, the detailed step of last part technologies such as well-known chip generation type and chip thinning is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet, for preferred embodiment of the present invention, can be described in detail as follows, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention not limited, it is as the criterion with claim.
In the semiconductor packaging process in modern times, all be a wafer (wafer) of having finished FEOL (FrontEnd Process) to be carried out thinning earlier handle (Thinning Process), the thickness of chip is ground between 2～20mil; Then, coating (coating) or wire mark (printing) one deck macromolecule (polymer) material are in the back side of chip again, and this macromolecular material can be a kind of resin (resin), particularly a kind of B rank (B-Stage) resin.By a baking or irradiation technology, make macromolecular material present a kind of semi-curing glue again with stickiness; Follow again, an adhesive tape that can remove (tape) is attached on the macromolecular material of semi-solid preparation shape; Then, carry out the cutting (sawing process) of wafer, make wafer become many chip (die); At last, just many chip can be connected with substrate and chip is formed the stack chip structure.
At first, please refer to shown in Fig. 3 A and Fig. 3 B, is floor map and the generalized section of finishing the chip 200 of aforementioned technology.Shown in Fig. 3 B, chip 200 has the back side 220 of active surface 210 and relative active surface, and has formed insulating barrier 230 on the chip back 220; To emphasize that at this insulating barrier 230 of the present invention is not defined as the resin material of aforesaid B rank semi-curing glue etc., the main purpose of this insulating barrier 230 is in the conduct insulation, in addition, insulating barrier 230 also can select to have the insulating material of stickiness, forms the purpose that engages in order to reach with substrate; Therefore so long as have above-mentioned these materials with function, for example: glued membrane (die attached film) all can be used as embodiments of the present invention.In addition, in an embodiment of the present invention, the active surface 210 of chip 200 is provided with a plurality of weld pads 240, and a plurality of weld pad 240 can be arranged on the periphery of chip 200.
Then, please refer to shown in Figure 4ly, is the generalized section of stack type encapsulation structure of the present invention.As shown in Figure 4, in the present embodiment, provide substrate 300, it is provided with a plurality of metal endpoints 310 (terminal), wherein substrate can be circuit board (PCB) or lead frame (Leadframe) etc., and when this substrate was circuit board, it can be further used as the support plate of BGA.Then, chip 200a is being pasted on substrate 300, and exposing metal endpoints 310, reaching the effect of pasting and engaging between chip 200a and the substrate 300 is insulating barrier 230 by being positioned on the chip 200a back side.Then, heat or dry by the fire and copy technology, be positioned at insulating barrier 230 on chip back 220 and the substrate 300 with curing; Then carry out wire bonding process (wire bonding proess), connect metal endpoints 310 on weld pad 240 and the substrate 300 on the chip 200a with many strip metals lead 320.Be stressed that at this mode that wire bonding process of the present invention is to use a kind of contrary wire bonding process (Reversed wirebonding) will form being connected of chip 200a and substrate 300; Wherein when carrying out against wire bonding process, can on the weld pad 240 of chip 200a, form salient point 330 (stud bump) earlier, then the metal endpoints on plain conductor 320 and the substrate 310 is formed is connected after, the ending of plain conductor 320 is consolidated be connected again with salient point 330.Form earlier the purpose of this salient point 330, can make plain conductor 320 not too large, except can avoiding in subsequent technique, producing the problem of breasting the tape, and can effectively reduce the thickness of follow-up encapsulation at the radian at weld pad 240 places of chip 200a.
And then, use coating or typography, adhesion layer 340a is coated on the active surface 210 of chip 200a, and cover whole active surface 210, so the ending of plain conductor 320 and salient point 330 also can be capped.This adhesion layer 340a can be macromolecular material, particularly a kind of B b stage resin b; And the thickness of this adhesion layer 340a is greater than the height of the maximum radian of plain conductor 320, so the thickness of adhesion layer 340a is between between the 2mil to 10mil.Follow again, can selectively carry out the baking program, in order to solidify adhesion layer 340a.
Then, again another chip 200b is sticked on the adhesion layer 340a, make the insulating barrier 230 that is positioned on the chip 200b back side be attached on the adhesion layer 340a.Because by coating or the also out-of-flatness of the surface of the adhesion layer 340a of typography, but because the insulating barrier 230 on the chip back can be a kind of B b stage resin b of semi-solid preparation, so insulating barrier 230 can form driving fit with the adhesion layer 340a of surface irregularity.Follow again, heat or the baking program, make the chip 200b can be affixed with adhesion layer 340a.Follow again, carry out the contrary wire bonding process of another time, so that many strip metals lead 320 connects the metal endpoints 310 on weld pad 240 and the substrate 300 on the chip 200b.Same, contrary wire bonding process in the present embodiment also can form salient point 330 (stud bump) earlier on the weld pad 240 of chip 200b, then the metal endpoints on plain conductor 320 and the substrate 310 is formed is connected after, the ending of plain conductor 320 is consolidated be connected again with salient point 330.Then, repeat aforesaid operation, adhesion layer 340b is coated on the active surface 210 of chip 200b, and cover whole active surface 210, after can selectively carrying out baking process then, again other chip 200c is sticked on the adhesion layer 340b, so repeat aforementioned baking and wire bonding process, can finish multi-chip stack structure 30.Carry out sealing adhesive process at last, with adhesive body 370 end points on multi-chip stack structure 30, many strip metals lead 320 and the substrate 310 is covered, as shown in Figure 4.
In the present embodiment owing to use contrary wire bonding process, so the ending end of plain conductor 320 on the weld pad 240 of chip, clearly, the radian that plain conductor 320 is held at the end of is less than the radian of the wire bonding end at metal endpoints 310 places.Therefore, in the process of carrying out chip stack, can reduce the height between chip 200a, 200b, 200c and the 200d; Also because there is insulating barrier 230 at the back side 220 of chip 200, therefore when chip stack is on the ending end of plain conductor 320 and salient point 330, can not cause short circuit yet.Simultaneously, when carrying out, can on each weld pad on the chip, all form salient point 330 earlier against wire bonding process; Even some weld pad 240 not necessarily can be connected with substrate 300, but in the present embodiment, still can on not as the weld pad of tie point, still be formed with salient point 330, this salient point is called rosin joint pad (dummy pad), its objective is the separation material that is used as (for example chip 200a and 200b) between the stack chip.In addition, also 340 covering of layer because a plain conductor 320 at two chip chambers (for example chip 200a and 200b) has got adhered, so not only can prevent the contact between the plain conductor 320, also can increase the intensity of plain conductor 320 itself simultaneously, so in the process of sealing, just be difficult for producing the problem of breasting the tape.In addition, because adhesion layer 340 has covered the active surface 210 of entire chip, so make the no gap of two chip chambers (for example chip 200a and 200b) exist, so just can not produce the situation of bubble at chip chamber after finishing sealing adhesive process, so can solve the problem that causes the chip be full of cracks.Moreover, because adhesion layer 340 has covered the active surface 210 of entire chip, so chip does not have unsettled situation, so also can solve the problem of fragmentation in the lump.By above-mentioned result, the technical characterictic that the present invention is disclosed is enough to use the encapsulating structure of relatively thin chip, so can increase the density of storehouse.
In addition, in order further to strengthen and keep the clearance distance of two chip chambers (for example chip 200a and 200b), the present invention provides another specific embodiment again, as shown in Figure 5.In the present embodiment, be in the adhesion layer 340 of Fig. 4, to mix to add a kind of approximate sphere 360, this approximate sphere 360 is a kind of rubber-like macromolecular material, for example resin.In the process of carrying out aforementioned chip stack, a plurality of approximate spheres 360 evenly mix with adhesion layer 340, so can be formed on the active surface 210 of each chip along with the coating or the process of printing.Because this approximate sphere 360 has certain volume, therefore the support of chip chamber (for example chip 200a and 200b) can be provided, simultaneously, for can be effectively as supporter, the height of approximate sphere 360 can be chosen between 35～200um.Chip stack process as for present embodiment is identical with Fig. 4 embodiment, so repeat no more.
The present invention continues another specific embodiment is provided again, as Figure 6 and Figure 7.In the present embodiment, be that the substrate among Fig. 4 and Fig. 5 is replaced with lead frame.When substrate was lead frame 400, because lead frame 400 has interior pin 410 and a chip bearing 420 that a plurality of one-tenth are arranged relatively at least, and this chip bearing 420 was between the interior pin 410 of a plurality of relative arrangements; Clearly, in the embodiment of Fig. 6, form copline between chip bearing 420 and the interior pin 410.Simultaneously, chip bearing 420 has upper surface 422 and lower surface 424.
Then, chip 200a is being pasted on the upper surface 422 of chip bearing 420, reaching the effect of pasting and engaging between the upper surface 422 of chip 200a and chip bearing 420 is insulating barrier 230 by being positioned on the chip 200a back side.Then, heat or dry by the fire and copy technology, to solidify the insulating barrier 230 between chip back 220 and chip bearing 420; Then carry out contrary wire bonding process, connect weld pad 240 and interior pin 410 on the chip 200a with many strip metals lead 320.Similarly, when carrying out contrary wire bonding process, can on the weld pad 240 of chip 200a, form salient point 330 earlier, then with plain conductor 320 with after interior pin 410 formation of lead frame 400 are connected, the ending with plain conductor 320 is connected with salient point 330 again.And then, use coating or typography, the adhesion layer 340a that is mixed with a plurality of approximate spheres 360 is coated on the active surface 210 of chip 200a, and cover whole active surface 210, so the ending of plain conductor 320 and salient point 330 also can be capped.This adhesion layer 340a can be macromolecular material, particularly a kind of B b stage resin b; Approximate sphere 360 then is a kind of rubber-like macromolecular material.In the present embodiment, the thickness of adhesion layer 340a is greater than the height of the maximum radian of plain conductor 320, so the thickness of adhesion layer 340a is between between the 2mil to 10mil.Simultaneously, in order to keep the clearance distance of two chip chambers (for example chip 200a and 200b), the height of approximate sphere 360 can be chosen between 35～200um.Follow again, can selectively carry out the baking program, in order to solidify adhesion layer 340a.
Then, again another chip 200b is sticked on the adhesion layer 340a, make that the insulating barrier 230 on the back side that is positioned at chip 200b is attached on the adhesion layer 340a.Because by coating or the also out-of-flatness of the surface of the adhesion layer 340a of typography, but because the insulating barrier 230 on the chip back can be a kind of B b stage resin b of semi-solid preparation, so insulating barrier 230 can form driving fit with the adhesion layer 340a of surface irregularity.Follow again, carry out the baking program, make the chip 200b can be affixed with adhesion layer 340a.Then, carry out the contrary wire bonding process of another time, use many strip metals lead 320 to connect weld pad 240 and interior pin 410 on the chip 200b, same, also can on the weld pad 240 of chip 200b, form salient point 330 earlier, then the interior pin 410 of plain conductor 320 and lead frame 400 is formed be connected after, the ending with plain conductor 320 is connected with salient point 330 again.Then, repeat aforesaid operation, the adhesion layer 340b that is mixed with a plurality of approximate spheres 360 is coated on the active surface 210 of chip 200b, and cover whole active surface 210, after carrying out baking process then, again another chip 200c is sticked on the adhesion layer 340b, then repeat aforementioned baking and contrary wire bonding process, can finish multi-chip stack structure 40.Carry out sealing adhesive process at last, multi-chip stack structure 40, many strip metals lead 320 and interior pin 410 are covered with adhesive body (not being shown among the figure), will be as shown in Figure 6.
In addition, referring again to Fig. 7, it also is to use lead frame is the embodiment of substrate, because the difference between Fig. 7 and Fig. 6 is only highly different being provided with of the chip bearing 420 of lead frame 400, remaining structure is all identical with Fig. 6, so the process of relevant formation chip stack just repeats no more.In the embodiment of Fig. 7, have difference in height between the chip bearing 420 of lead frame 400 and the interior pin 410, particularly chip bearing 420 is to form a kind of heavy structure of putting (DOWN-SET).What will emphasize is that in the embodiment of Fig. 6 and Fig. 7, a plurality of approximate spheres 360 are optionally to add adhesion layer 340, also are embodiments of the present invention so be not similar to the packaging structure of sphere 360 in Fig. 6 and Fig. 7 again.
It is the stack package structure of substrate with the lead frame that the present invention continues to provide a kind of again, as Fig. 8 and shown in Figure 9.Please earlier with reference to Fig. 8, when substrate was lead frame 400, because lead frame 400 has interior pin 410 and a chip bearing 420 that a plurality of one-tenth are arranged relatively, chip bearing 420 was between the interior pin 410 of a plurality of relative arrangements.Be stressed that in the present embodiment, form copline between chip bearing 420 and the interior pin 410, and chip bearing 420 has upper surface 422 and lower surface 424.Then, chip 200a is being pasted on the upper surface 422 of chip bearing 420, reaching the effect of pasting and engaging between the upper surface 422 of chip 200a and chip bearing 420 is insulating barrier 230 by being positioned on the chip 200a back side.Then, heat or dry by the fire and copy technology, to solidify the insulating barrier 230 between chip back 220 and chip bearing 420; Then carry out contrary wire bonding process, connect weld pad 240 and interior pin 410 on the chip 200a with many strip metals lead 320, wherein when carrying out against wire bonding process, can on the weld pad 240 of chip 200a, form salient point 330 earlier, then pin within plain conductor 320 and the lead frame 400 410 is formed be connected after, the ending with plain conductor 320 is connected with salient point 330 again.And then, use coating or typography, adhesion layer 340a is coated on the active surface 210 of chip 200a, and cover whole active surface 210, so the ending of plain conductor 320 and salient point 330 also can be capped.This adhesion layer 340a can be macromolecular material, particularly a kind of B b stage resin b; And the thickness of this adhesion layer 340a is greater than the height of the maximum radian of plain conductor 320, so the thickness of adhesion layer 340a is between between the 2mil to 10mil.Follow again, can selectively carry out the baking program, in order to solidify adhesion layer 340a.
Then, again another chip 200b is sticked on the adhesion layer 340a, make that the insulating barrier 230 on the back side 220 that is positioned at chip 200b is attached on the adhesion layer 340a.Because by coating or the also out-of-flatness of the surface of the adhesion layer 340a of typography, but because the insulating barrier 230 on the chip back can be a kind of B b stage resin b of semi-solid preparation, so insulating barrier 230 can form driving fit with the adhesion layer 340a of surface irregularity.Follow again, carry out the baking program, make the chip 200b can be affixed with adhesion layer 340a.Then, carry out the contrary wire bonding process of another time, use many strip metals lead 320 to connect weld pad 240 and interior pin 410 on the chip 200b, same, also can on the weld pad 240 of chip 200b, form salient point 330 earlier, then the interior pin 410 of plain conductor 320 and lead frame 400 is formed be connected after, the ending with plain conductor 320 is connected with salient point 330 again.Then, aforesaid operation can be selected to continue to repeat, the stack architecture 50 of a plurality of chips can be on the upper surface 422 of chip bearing 420, formed.
Then, with the anti-turnback of lead frame, make the facing up of lower surface 424 of chip bearing 420 of lead frame 400, carry out the previous step of this example then, the lower surface 424 of chip 200c and chip bearing 420 is affixed, and after carrying out the baking program, use contrary wire bonding process, with plain conductor 320 chip 200c is connected with interior pin 410, and then adhesion layer 340b is coated on the active surface 210 of chip 200c, then again that chip 200d and adhesion layer 340b is affixed, and after carrying out the baking program, with plain conductor 320 chip 200d is connected with interior pin 410 again.Same, also can select to continue to repeat aforesaid operation, can on the lower surface 424 of chip bearing 420, form the stack architecture 60 of another a plurality of chips.Carry out sealing adhesive process at last, with adhesive body (not being shown among the figure) multi-chip stack structure 50, multi-chip stack structure 60, many strip metals lead 320 and interior pin 410 are covered, as shown in Figure 8.In addition, in Fig. 9 embodiment, be in the embodiment of Fig. 8, in adhesion layer 340, added a plurality of approximate spheres 360, all the other are then all identical with Fig. 8, so correlated process repeats no more.
Clearly, when 420 one-tenth differences in height of interior pin 410 in the lead frame 400 and chip bearing, multi-chip stack structure 40 can form asymmetric storehouse, as shown in figure 10, one side be the odd number chip stack (for example: multi-chip stack structure 70), opposite side then be the even number chip stack (for example: multi-chip stack structure 60), do not limited in this present invention.Simultaneously, in an embodiment of the present invention, difference in height between visible die bearing 420 and the interior pin 410 (particularly forming heavy interposed structure) is carried out the storehouse of chip 200, so its stack architecture that also may form a plurality of chips at the upper surface 422 of chip bearing 420 (for example: multi-chip stack structure 70), and only connecting a chip at the lower surface 424 of chip bearing 420, this stack architecture also is embodiments of the invention.In this embodiment, the process that forms multi-chip stack is identical with the embodiment of Fig. 8 and Fig. 9, and in adhesion layer 340, also can optionally add a plurality of approximate spheres 360, so correlated process then repeats no more.
According to said process, the invention provides a kind of method of chip stack encapsulation, its step is as follows: at first, provide substrate, and substrate is provided with a plurality of metal endpoints; First chip then is provided, the active surface of first chip is provided with on a plurality of weld pads and the back side with respect to active surface insulating barrier is set, and the insulating barrier on the chip is connected with substrate, in the present invention, substrate can be a kind of circuit board, and it can be further used as the support plate of BGA; Then, provide heater to carry out baking process after, to solidify the insulating barrier of first chip back; Then, re-use contrary wire bonding process many strip metals lead is provided, and be electrically connected a plurality of weld pads on first chip and a plurality of metal endpoints on the substrate with many strip metals lead, wherein contrary wire bonding process forms salient point earlier on the weld pad of chip, then the metal endpoints of plain conductor and substrate is formed be connected after, the ending with plain conductor is connected with salient point again; Because the radian of plain conductor ending end is lower, therefore can be so that the pitch smaller between stack chip.Follow again, form first adhesion layer on the active surface of first chip; Then provide second chip, the active surface of this second chip to be provided with a plurality of weld pads again and be provided with insulating barrier, and insulating barrier is engaged with first adhesion layer with respect to the back side of active surface; Then, provide heater, in order to solidify first adhesion layer; Follow again, many strip metals lead is provided, make many strip metals lead be electrically connected a plurality of weld pads on second chip and a plurality of metal endpoints on the substrate; Then, form second adhesion layer again on the active surface of second chip; And provide the 3rd chip, the active surface of the 3rd chip to be provided with on a plurality of weld pads and the back side again insulating barrier is set, and insulating barrier is engaged with second adhesion layer with respect to active surface; Equally, provide heater, in order to solidify second adhesion layer; Then, re-use contrary wire bonding process many strip metals lead is provided, be used for being electrically connected a plurality of weld pads on the 3rd chip and a plurality of metal endpoints on the substrate; Repeat abovementioned steps so again, promptly can form multi-chip stack structure of the present invention.
In addition, in the method for packing of above-mentioned multi-chip stacking type, can in adhesion layer, be mixed into a plurality of approximate spheres, simultaneously after adhesion layer is formed on the active surface of a plurality of chips, optionally add heater to carry out the baking program, in order to solidify these adhesion layers.
The present invention then provides the method for another kind of chip stack encapsulation again, its step is as follows: at first, lead frame is provided, and interior pin and a chip bearing that this lead frame is arranged relatively by a plurality of one-tenth are formed, and the chip bearing is between the interior pin that a plurality of one-tenth are arranged relatively; First chip then is provided, and the active surface of first chip is provided with on a plurality of weld pads and the back side with respect to active surface insulating barrier is set, and is affixed with the insulating barrier and the chip bearing of chip back then; In the present embodiment, the chip bearing can be into the structure that copline also can be into difference in height with interior pin; Provide heater to carry out the baking program then, in order to solidify the insulating barrier of first chip back; Use contrary wire bonding process that many strip metals lead is provided afterwards, and be electrically connected pin in a plurality of on a plurality of weld pads on first chip and the lead frame with many strip metals lead, wherein contrary wire bonding process is to form salient point on the weld pad of chip earlier, then the interior pin on plain conductor and the lead frame is formed be connected after, the ending with plain conductor is connected with salient point again; Because the radian of plain conductor ending end is lower, therefore can be so that the pitch smaller between stack chip.Follow again, form first adhesion layer on the active surface of first chip, simultaneously, in this first adhesion layer, can optionally add a plurality of approximate spheres; Then provide second chip again, and the active surface of second chip is provided with insulating barrier is set on a plurality of weld pads and the back side with respect to active surface, and this insulating barrier is engaged with first adhesion layer; Then, provide heater, in order to solidify first adhesion layer; Then, re-use wire bonding process many strip metals lead is provided, make many strip metals lead be electrically connected pin in a plurality of on a plurality of weld pads on second chip and the lead frame; And then, form second adhesion layer again on the active surface of second chip, and also can optionally add a plurality of approximate spheres in this second adhesion layer; Then provide the 3rd chip, the active surface of the 3rd chip to be provided with on a plurality of weld pads and the back side again insulating barrier is set, and insulating barrier is engaged with second adhesion layer with respect to active surface; Equally, provide heater, in order to solidify second adhesion layer; Then, re-use contrary wire bonding process many strip metals lead is provided, be used for being electrically connected pin in a plurality of on a plurality of weld pads on the 3rd chip and the lead frame; Repeat abovementioned steps so again, promptly can form multi-chip stack structure of the present invention.
Be stressed that, in the method for packing of above-mentioned multi-chip stacking type, chip bearing and interior pin can be that copline also can be to form difference in height, particularly chip bearing to form heavy (down-set) structure of putting, setting to these two kinds of line falling framves is embodiments of the invention.In addition, present embodiment also can be mixed into a plurality of approximate spheres in adhesion layer, simultaneously after adhesion layer is formed on the active surface of a plurality of chips, optionally adds heater to carry out the baking program, in order to solidify these adhesion layers.
The present invention then provides the method for another kind of chip stack encapsulation again, its step is as follows: at first, lead frame is provided, interior pin and a chip bearing that this lead frame is arranged relatively by a plurality of one-tenth are formed, and the chip bearing is between the interior pin that a plurality of one-tenth are arranged relatively, simultaneously, the chip bearing has upper surface and lower surface; First chip then is provided, and the active surface of first chip is provided with on a plurality of weld pads and the back side with respect to active surface insulating barrier is set, and is affixed with the upper surface of the insulating barrier of chip back and chip bearing then; In the present invention, the chip bearing can be into the structure that copline also can be into difference in height with interior pin; Provide heater to carry out the baking program then, in order to solidify the insulating barrier of first chip back; Use contrary wire bonding process that many strip metals lead is provided afterwards, and be electrically connected pin in a plurality of on a plurality of weld pads on first chip and the lead frame with many strip metals lead, wherein contrary wire bonding process is to form salient point on the weld pad of chip earlier, then the interior pin on plain conductor and the lead frame is formed be connected after, the ending with plain conductor is connected with salient point again; Because the radian of plain conductor ending end is lower, therefore can be so that the pitch smaller between stack chip.Follow again, form first adhesion layer on the active surface of first chip; Then provide second chip again, and the active surface of second chip is provided with insulating barrier is set on a plurality of weld pads and the back side with respect to active surface, and this insulating barrier is engaged with first adhesion layer; Then, provide heater, in order to solidify first adhesion layer; Then, re-use wire bonding process many strip metals lead is provided, make many strip metals lead be electrically connected pin in a plurality of on a plurality of weld pads on second chip and the lead frame; At this moment, with the anti-turnback of lead frame; Then, provide the 3rd chip again, the active surface of the 3rd chip is provided with on a plurality of weld pads and the back side with respect to active surface insulating barrier is set, and affixed with the lower surface of the insulating barrier of chip back and chip bearing; Equally, provide heater,, then, use contrary wire bonding process that many strip metals lead is provided, and be electrically connected pin in a plurality of on a plurality of weld pads on the 3rd chip and the lead frame with many strip metals lead in order to solidify insulating barrier; Follow again, form second adhesion layer on the active surface of the 3rd chip; Then provide the four-core sheet again, an active surface of four-core sheet is provided with on a plurality of weld pads and the back side with respect to active surface insulating barrier is set, and the insulating barrier of chip back is engaged with second adhesion layer; Then, provide heater, in order to solidify second adhesion layer; Then, re-use contrary wire bonding process many strip metals lead is provided, make many strip metals lead be electrically connected pin in a plurality of on a plurality of weld pads on the four-core sheet and the lead frame; Repeat abovementioned steps so again, promptly can form multi-chip stack structure of the present invention.Clearly, when the interior pin in the lead frame became difference in height with the chip bearing, multi-chip stack structure can form asymmetric storehouse, and wherein a side can be the odd number chip stack, opposite side then can be the even number chip stack, is not limited in this present invention.Simultaneously, in an embodiment, difference in height between visible die bearing and the interior pin (particularly forming heavy interposed structure) is carried out the storehouse of chip, so it also may form the stack architecture of a plurality of chips at the upper surface of chip bearing, and only connect a chip at the lower surface of chip bearing, this stack architecture also is embodiments of the invention, is not limited in this present invention.
Apparently, according to the description among the top embodiment, the present invention has many improvement and change.Therefore need to be understood within the scope of the claims, except above-mentioned detailed description, the present invention can also implement widely in other embodiments.Above-mentioned is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or improvement, all should be included in the claim scope.
Claims (16)
1. the encapsulating structure of a multi-chip stacking type, comprise substrate, it is provided with a plurality of metal endpoints and multi-chip stack structure, be to form by a plurality of chip stacks, and this multi-chip stack structure is fixed on this substrate and by many strip metals lead this multi-chip stack structure is electrically connected with these a plurality of metal endpoints on this substrate, and the encapsulating structure of this multi-chip stacking type is characterised in that:
The active surface of each chip in this multi-chip stack structure is provided with on the back side with respect to this active surface of a plurality of weld pads and each this chip insulating barrier is set, and by adhesion layer this active surface of this each chip is engaged with this insulating barrier on another chip back forming this multi-chip stack structure between these a plurality of chips, and be electrically connected with these a plurality of metal endpoints on this substrate by this many strip metals lead these a plurality of weld pads on will these a plurality of chips.
2. the encapsulating structure of multi-chip stacking type according to claim 1 is characterized in that this adhesion layer is a macromolecular material.
3. the encapsulating structure of multi-chip stacking type according to claim 1 is characterized in that this adhesion layer is B rank materials.
4. the encapsulating structure of multi-chip stacking type according to claim 1 is characterized in that this insulating barrier is glued membrane or B rank material.
5. the encapsulating structure of multi-chip stacking type according to claim 1 is characterized in that this substrate is a circuit board.
6. the encapsulating structure of multi-chip stacking type according to claim 1 is characterized in that this substrate is a lead frame.
7. the encapsulating structure of a multi-chip stacking type, comprise substrate, it is provided with a plurality of metal endpoints and multi-chip stack structure, be to form by a plurality of chip stacks, and this multi-chip stack structure is fixed on this substrate and by many strip metals lead this multi-chip stack structure is electrically connected with these a plurality of metal endpoints on this substrate, and the encapsulating structure of this multi-chip stacking type is characterised in that:
The active surface of each chip in this multi-chip stack structure is provided with on the back side with respect to this active surface of a plurality of weld pads and each this chip insulating barrier is set, and between these a plurality of chips by be mixed with a plurality of approximate spherical bodies in wherein adhesion layer this active surface of this each chip is engaged with this insulating barrier on another chip back with form stack architecture and will these a plurality of chips by many strip metals lead on these a plurality of weld pads be electrically connected with these a plurality of metal endpoints on this substrate.
8. the encapsulating structure of multi-chip stacking type according to claim 7 is characterized in that this approximate spherical body is a kind of macromolecular material.
9. the encapsulating structure of multi-chip stacking type according to claim 7, the height that it is characterized in that this approximate spherical body is 35～200um.
10. the encapsulating structure of a multi-chip stacking type, comprise: lead frame, be the interior pin and the chip bearing of arranging relatively by a plurality of one-tenth, this chip bearing is between the interior pin of a plurality of relative arrangements, and this chip bearing have upper surface with respect to the lower surface and the multi-chip stack structure of this upper surface, be to form by a plurality of chip stacks, and this multi-chip stack structure is fixed on the upper surface of this chip bearing and by many strip metals lead the relative interior pin of arranging of a plurality of one-tenth of this multi-chip stack structure and this is electrically connected, and the encapsulating structure of this multi-chip stacking type is characterised in that:
The active surface of each chip in this multi-chip stack structure is provided with on the back side with respect to this active surface of a plurality of weld pads and each this chip insulating barrier is set, and by being mixed with a plurality of approximate spherical bodies, this active surface of this each chip and this insulating barrier on another chip back are engaged to form stack architecture and by a plurality of interior pin electrical connections that become relative arrangement of on many strip metals lead these a plurality of weld pads on will this a plurality of chips and this lead frame this between these a plurality of chips in adhesion layer wherein.
11. the encapsulating structure of multi-chip stacking type according to claim 10 is characterized in that this approximate spherical body is a kind of macromolecular material.
12. the encapsulating structure of multi-chip stacking type according to claim 10, the height that it is characterized in that this approximate spherical body is 35～200um.
13. the encapsulating structure of a multi-chip stacking type, comprise lead frame, be the interior pin and the chip bearing of arranging relatively by a plurality of one-tenth, this chip bearing is between the interior pin of a plurality of relative arrangements, and this chip bearing have upper surface with respect to lower surface and a plurality of multi-chip stack structure of this upper surface, each this multi-chip stack structure is to be formed by a plurality of chip stacks, and these a plurality of multi-chip stack structures are fixed in the upper surface and the lower surface of this lead frame respectively, and by the interior pin electrical connection of many strip metals lead with the relative arrangement with these a plurality of one-tenth of these a plurality of multi-chip stack structures, the encapsulating structure of this multi-chip stacking type is characterised in that:
The active surface of each this chip in these a plurality of multi-chip stack structures is provided with on the back side with respect to this active surface of a plurality of weld pads and each this chip insulating barrier is set, and between these a plurality of chips by be mixed with a plurality of approximate spherical bodies in wherein adhesion layer this active surface of this each chip and this insulating barrier on another chip back are engaged with form stack architecture and will this a plurality of chips by many strip metals lead on a plurality of interior pin electrical connections that become relative arrangement of these a plurality of weld pads and this lead frame.
14. the encapsulating structure of multi-chip stacking type according to claim 13 is characterized in that this chip bearing has difference in height between the interior pin of these a plurality of relative arrangements.
15. the encapsulating structure of multi-chip stacking type according to claim 13, this upper surface and the number of chips on this lower surface that it is characterized in that being stacked over this chip bearing are inequality.
16. the encapsulating structure of multi-chip stacking type according to claim 15, the number of chips that it is characterized in that this lower surface are 1 chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101119225A CN101131992A (en) | 2006-08-24 | 2006-08-24 | Multi-chip stacking type packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2006101119225A CN101131992A (en) | 2006-08-24 | 2006-08-24 | Multi-chip stacking type packaging structure |
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| CN101131992A true CN101131992A (en) | 2008-02-27 |
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| CNA2006101119225A Pending CN101131992A (en) | 2006-08-24 | 2006-08-24 | Multi-chip stacking type packaging structure |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102194779A (en) * | 2010-03-02 | 2011-09-21 | 日月光半导体制造股份有限公司 | Packaging structure |
| CN102445674A (en) * | 2010-09-22 | 2012-05-09 | 特斯拉工程有限公司 | Gradient coil sub-assemblies |
| CN103367366A (en) * | 2012-03-31 | 2013-10-23 | 南亚科技股份有限公司 | Semiconductor packaging member |
| CN105489569A (en) * | 2015-12-24 | 2016-04-13 | 合肥祖安投资合伙企业(有限合伙) | Packaging structure and manufacturing method for pressure sensor |
| CN111785827A (en) * | 2020-06-30 | 2020-10-16 | 深圳振华富电子有限公司 | Manufacturing method of piezoelectric actuator |
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- 2006-08-24 CN CNA2006101119225A patent/CN101131992A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194779A (en) * | 2010-03-02 | 2011-09-21 | 日月光半导体制造股份有限公司 | Packaging structure |
| CN102194779B (en) * | 2010-03-02 | 2013-04-17 | 日月光半导体制造股份有限公司 | Packaging structure |
| CN102445674A (en) * | 2010-09-22 | 2012-05-09 | 特斯拉工程有限公司 | Gradient coil sub-assemblies |
| CN102445674B (en) * | 2010-09-22 | 2016-01-20 | 特斯拉工程有限公司 | MRIS gradient coil sub-assemblies, manufacture its method and comprise its assembly |
| US10031194B2 (en) | 2010-09-22 | 2018-07-24 | Tesla Engineering Limited | Gradient coil sub-assemblies |
| CN103367366A (en) * | 2012-03-31 | 2013-10-23 | 南亚科技股份有限公司 | Semiconductor packaging member |
| CN105489569A (en) * | 2015-12-24 | 2016-04-13 | 合肥祖安投资合伙企业(有限合伙) | Packaging structure and manufacturing method for pressure sensor |
| CN105489569B (en) * | 2015-12-24 | 2020-01-07 | 合肥矽迈微电子科技有限公司 | Packaging structure of pressure sensor and manufacturing method thereof |
| CN111785827A (en) * | 2020-06-30 | 2020-10-16 | 深圳振华富电子有限公司 | Manufacturing method of piezoelectric actuator |
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