CN101131993A - Packaging structure of conducting wire holder on multi-chip stacking structure - Google Patents
Packaging structure of conducting wire holder on multi-chip stacking structure Download PDFInfo
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- CN101131993A CN101131993A CN 200610111923 CN200610111923A CN101131993A CN 101131993 A CN101131993 A CN 101131993A CN 200610111923 CN200610111923 CN 200610111923 CN 200610111923 A CN200610111923 A CN 200610111923A CN 101131993 A CN101131993 A CN 101131993A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention provides a package of line frame on stacked chips, and includes: a line frame consisted of several pairs of outer pins and several pairs of inner pins formed by several lines, and the several inner pins are divided into first inner pins group and second inner pins group, of which length of the first group is much longer than it of the second group; several semiconductor chip devices, and active surface of each chip is placed forward and interval to form offset-stack arrangement; the semiconductor chip device on top of the stack is fixed under the first inner pins group, and several semiconductor chip devices are electrically connected by the first inner pins group and the second inner pins group on small side.
Description
Technical field
The present invention relates to a kind of multi-chip stack packaging structure, particularly a kind of structure of using lead frame to carry out the multi-chip stack encapsulation.
Background technology
In recent years, semi-conductive last part technology is all carrying out three dimensions (Three Dimension; Encapsulation 3D) reaches higher density or capacity of internal memory etc. in the hope of utilizing minimum area.In order to reach this purpose, present stage has developed and has used the mode of chip stack (chip stacked) to reach three dimensions (Three Dimension; Encapsulation 3D).
In known technology, the storehouse mode of chip is that a plurality of chips are stacked on the substrate mutually, uses the technology (wire bonding process) of wire-bonded that a plurality of chips are connected with substrate then.It is the chip stack package structure of substrate with the lead frame that Fig. 1 (comprising Figure 1A, 1B) promptly discloses a kind of, and wherein Figure 1A is the floor map of Figure 1A for generalized section Figure 1B.Shown in Figure 1A, lead frame 5 can be divided into the interior 5a of pin portion, the outer pin 5b of portion and platform part 5c, and wherein platform part 5c and the interior pin 5a of portion and the outer pin 5b of portion have difference in height.At first with three chip stacks on the interior pin 5a of lead frame 5, then with plain conductor 10,11,12 weld pad on three chips 7,8,9 is connected on the platform part 5c of lead frame 5 again, then, carry out packaging technology (molding process) with the interior pin 5a of three stack chips and lead frame 5 and the platform part 5c sealing of part, but expose the outer pin 5b of portion, with pin as other interface of connection.
In the above-mentioned known chip stack package structure, because plain conductor 10,11,12 length and radian between the platform part 5c of each chip and lead frame 5 are all inequality, so except in carrying out encapsulation process, the long plain conductor of length and radian easily produces displacement and causes outside the short circuit of chip, also can be inequality because of plain conductor 10,11,12 length, cause the phase place of signal of telecommunication problem such as change.
Summary of the invention
In view of the shortcoming and the problem of the chip stack mode described in the background of invention, the invention provides a kind of mode of using the chip offset storehouse, the akin chip stack of a plurality of sizes is become a kind of three-dimensional encapsulating structure.
Main purpose of the present invention provides a kind of storehouse cake core encapsulating structure, makes it have higher encapsulation integration and thin thickness.
Another purpose of the present invention provides a kind of stack package structure of System on Chip/SoC, makes it have higher encapsulation integration and thin thickness.
Another object of the present invention provides a kind ofly puts the structure that conductor layer (Redistribution Layer) forms storehouse encapsulation with the weld pad on the chip to reset, and it has higher encapsulation integration and thin thickness.
In view of the above, the invention provides the encapsulating structure of a kind of lead frame on stack chip, comprise: a lead frame, formed by outer pin and the relative interior pin of arranging of a plurality of one-tenth that the formed a plurality of one-tenth of a plurality of leads are arranged relatively, wherein these a plurality of interior pin area are divided into the pin group and the second interior pin group in first, and this first interior pin group's length is much larger than this second interior pin group; Multi-chip stack structure, form by a plurality of chip stacks, and the active face of each chip up and form the structure of skew stack arrangement with dislocation, wherein the chip of stack arrangement the top is fixed under the first interior pin group, and multi-chip stack structure is electrically connected by pin group in the pin group and second in same side and first; Reach a packaging body, coat semiconductor chiop and this lead frame of these a plurality of formation stack arrangement, these a plurality of outer pins stretch out in outside this packaging body.
The present invention provides the encapsulating structure of a kind of lead frame on stack chip again, comprise: a lead frame, be made up of the formed a plurality of outer pins of a plurality of leads and a plurality of interior pin, wherein these a plurality of interior pin area are divided into pin group in first, and the first interior pin group's lower surface is provided with viscose; Multi-chip stack structure, form by a plurality of chip stacks, and the back side of each chip is provided with viscose, to stick together the structure that forms active supine skew stack arrangement in twos, wherein the chip of stack arrangement the top sticks together and is fixed under the first interior pin group, and multi-chip stack structure is electrically connected by pin group in the pin group and second in same side and first; Reach packaging body, coat semiconductor chiop and this lead frame of these a plurality of formation stack arrangement, these a plurality of outer pins stretch out in outside this packaging body.
The present invention also provides the encapsulating structure of a kind of lead frame on stack chip, comprise: lead frame, formed by the formed a plurality of outer pins of a plurality of leads and a plurality of interior pin, wherein these a plurality of interior pin area are divided into the pin group and the second interior pin group in first, and this first interior pin group's length is much larger than this second interior pin group; Multi-chip stack structure, form by a plurality of chip stacks, and the active face of each chip is provided with viscose, to stick together the structure that forms active supine skew stack arrangement in twos, wherein the chip of stack arrangement the top sticks together and is fixed under this first interior pin group, and a plurality of chips are electrically connected by pin group in the pin group and second in same side and first; Reach packaging body, coat semiconductor chiop and this lead frame of these a plurality of formation stack arrangement, these a plurality of outer pins stretch out in outside this packaging body.
Description of drawings
Fig. 1 (comprising Figure 1A, 1B) is the schematic diagram of prior art;
Fig. 2 A is the top view of chip structure of the present invention;
Fig. 2 B is the cutaway view of chip structure of the present invention;
Fig. 2 C～2D is the cutaway view of multi-chip migration stack architecture of the present invention;
Fig. 3 A～3C puts the schematic diagram of layer process process for the present invention resets;
Fig. 4 A～4B puts the cutaway view in wire bonds district in the floor for the present invention resets;
Fig. 5 A～5B resets the cutaway view of the multi-chip migration stack architecture of putting layer for the present invention has;
Fig. 6 is the top view of multi-chip migration stack architecture encapsulation of the present invention;
Fig. 7 A～7C is the cutaway view of multi-chip migration stack architecture encapsulation of the present invention;
Fig. 8 is the cutaway view of another embodiment of multi-chip migration stack architecture encapsulation of the present invention;
The main element description of symbols:
1A, 1B: known stacked semiconductor element
2,3,4: semiconductor element
5: the lead frame lead-in wire
5a: pin portion in the lead frame
5b: the outer pin of lead frame
5c: leadframe pad portion
7,8,9: electrode
10,11,12: plain conductor
200: chip
210: the chip active face
220: chip back
230: adhesion layer
240: weld pad
250: the wire bonds district
260: the wire bonds area edge
270: adhesion layer
30: the multi-chip migration stack architecture
310: the chip body
312a: first weld pad
312b: second weld pad
320: the wire bonds district
322: the wire bonds area edge
330: the first protective layers
332: the first openings
340: reset and put line layer
344: the three weld pads
350: the second protective layers
352: the second openings
300: chip structure
400: reset and put conductor layer
50: the multi-chip migration stack architecture
500 (a, b, c, d): chip
520: adhesive tape
600: lead frame
601: the dotted line that inside and outside pin is distinguished
610: interior pin
620: outer pin
640 (a～e): plain conductor
650: metal coupling
Embodiment
The present invention is a kind of mode of using the chip offset storehouse in this direction of inquiring into, and the akin chip stack of a plurality of sizes is become a kind of three-dimensional encapsulating structure.In order to understand the present invention up hill and dale, detailed encapsulation step and encapsulating structure thereof will be proposed in following description.Apparently, execution of the present invention does not limit the specific details that the person of ordinary skill in the field understood of the mode of chip stack.On the other hand, the detailed step of last part technologies such as well-known chip generation type and chip thinning is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet, for preferred embodiment of the present invention, can describe in detail, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention do not limited, be as the criterion with claim.
In the semiconductor packaging process in modern times, all be a wafer (wafer) of having finished FEOL (FrontEnd Process) to be carried out thinning earlier handle (Thinning Process), the thickness of chip is ground between 2～20mil; Then, coating (coating) or wire mark (printing) one deck macromolecule (polymer) material are in the back side of chip again, and this macromolecular material can be a kind of resin (resine), particularly a kind of B-Stage resin.Via a baking or irradiation technology, make macromolecular material present a kind of semi-curing glue again with stickiness; Follow again, an adhesive tape that can remove (tape) is attached on the macromolecular material of semi-solid preparation shape; Then, carry out the cutting (sawing process) of wafer, make wafer become many chip (die); At last, just many chip can be connected with substrate and chip is formed the stack chip structure.
Shown in Fig. 2 A, 2B, finish the floor map and the generalized section of the chip 200 of aforementioned technology.Shown in Fig. 2 B, chip 200 has the back side 220 of active face 210 and relative active face, and has formed adhesion layer 230 on the chip back 220; To emphasize at this, adhesion layer 230 of the present invention is not defined as above-described semi-curing glue, the purpose of this adhesion layer 230 is to form with substrate or chip to engage, therefore, so long as have the adhesion material of this function, be embodiments of the present invention, for example: glued membrane (die attached film).
Then, please refer to Fig. 2 C, 2D, the present invention finishes the generalized section of multi-chip migration stack architecture 30.Shown in Fig. 2 C, the active face 210 of chip 200 is provided with a plurality of weld pads 240, and a plurality of weld pads 240 have been arranged on the same side of chip 200, therefore, the adhesion layer on the chip back 220 230 and the active face 210 of another chip 200 are offset after (OFFSET) engage, can form multi-chip migration stack architecture 30, the structure 30 of wherein this multi-chip migration storehouse is that the arrangement benchmark of reference forms with the edge 260 in wire bonds district 250, therefore can form similar stair-stepping multi-chip migration stack architecture 30, be noted that at this, it is not exist on the chip 200 that edge 260 is implemented, and it is only as line of reference.
In addition, the juncture of the structure 30 of chip offset storehouse of the present invention also can be coated on adhesion layer on the active face 210 of chip 200, shown in Fig. 2 D, adhesion layer 270 is coated on the active face 210 of chip 200, and allow wire bonds district 250 expose, therefore, with the adhesion layer 270 on the active face 210 of chip 200 with after another chip back 220 engages, can form a kind of multi-chip migration stack architecture 30, the structure 30 of wherein this multi-chip migration storehouse is that the benchmark of reference is arranged storehouse and formed with the edge 260 in wire bonds district 250, therefore can form similar stair-stepping multi-chip migration stack architecture 30.Still to emphasize at this, the adhesion layer 230 and the adhesion layer 270 of present embodiment are not defined as above-described semi-curing glue, the purpose of this adhesion layer 230 and adhesion layer 270 is to form with substrate or chip to engage, therefore, so long as have the adhesion material of this function, be embodiments of the present invention.
The present invention uses a kind of reseting to put layer (Redistribution Layer in another embodiment of multi-chip migration storehouse; RDL) folding of each chip on wafer weld pad is set on the side of chip, so that can form the structure of multi-chip migration storehouse, and this resets the execution mode of putting layer and is described as follows.
Fig. 3 A～3C resets the manufacture process schematic diagram of the chip structure of putting layer for the present invention has.As shown in Figure 3A, chip body 310 at first is provided, and cook up wire bonds district 320 at a side that is adjacent to chip body 310, and active lip-deep a plurality of weld pads 312 of chip body 310 are divided into the first weld pad 312a and the second weld pad 312b, wherein the first weld pad 312a is positioned at wire bonds district 320, the second weld pad 312b and then is positioned at outside the wire bonds district 320.Then please refer to Fig. 3 B, form first protective layer 330 on chip body 310, wherein first protective layer 330 has a plurality of first openings 332, to expose the first weld pad 312a and the second weld pad 312b.On first protective layer 330, form to reset then and put line layer 340.Put line layer 340 and comprise many leads 342 and a plurality of the 3rd weld pads 344 and reset, wherein the 3rd weld pad 344 is positioned at wire bonds district 320, and these leads 342 extend to the 3rd weld pad 344 from the second weld pad 312b respectively, so that the second weld pad 312b is electrically connected on the 3rd weld pad 344.In addition, reset the material of putting line layer 340, can be gold, copper, nickel, titanizing tungsten, titanium or other electric conducting material.Please refer to 3C figure again; formation reset put line layer 340 after, second protective layer 350 is covered in to reset puts on the line layer 340, and form chip structure 300; wherein second protective layer 350 has a plurality of second openings 352, to expose the first weld pad 312a and the 3rd weld pad 344.
Be stressed that, though the first above-mentioned weld pad 312a and the second weld pad 312b are arranged on the active surface of chip body 310 with kenel on every side, yet the first weld pad 312a and the second weld pad 312b can also be arranged on the chip body 310 via face array kenel (area array type) or other kenel, and certain second weld pad 312b is electrically connected on the 3rd weld pad 344 via lead 342.In addition, present embodiment does not also limit the arrangement mode of the 3rd weld pad 344, though the 3rd weld pad 344 and the first weld pad 312a are arranged in two row in 3B figure, and the single side along chip body 310 is arranged, but the 3rd weld pad 344 and the first weld pad 312a can also with single-row, multiple row or other mode be arranged in the wire bonds district 320.
Please continue with reference to Fig. 4 A and Fig. 4 B, among Fig. 3 C respectively along hatching A-A ' and the represented generalized section of B-B '.Shown in Fig. 4 A and Fig. 4 B, by in the above-mentioned icon as can be known chip structure 300 mainly comprise chip body 310 and reset and put 400 on layer and form, wherein reset put layer 400 by first protective layer 330, reset and put line layer 340 and second protective layer 350 is formed.Chip body 310 has wire bonds district 320, and wire bonds district 320 is adjacent to the single side of chip body 310.In addition, chip body 310 has a plurality of first weld pad 312a and the second weld pad 312b, and wherein the first weld pad 312a is positioned at wire bonds district 320, and the second weld pad 312b is positioned at outside the wire bonds district 320.
First protective layer 330 is arranged on the chip body 310, and wherein first protective layer 330 has a plurality of first openings 332, to expose these the first weld pad 312a and the second weld pad 312b.Reset and put line layer 340 and be arranged on first protective layer 330, wherein reset and put line layer 340 and extend in the wire bonds district 320 from the second weld pad 312b, and reset and put line layer 340 and have a plurality of the 3rd weld pads 344, it is arranged in the wire bonds district 320.Second protective layer 350 is covered in to reset and puts on the line layer 340, and wherein second protective layer 350 has a plurality of second openings 352, to expose these first weld pad 312a and the 3rd weld pad 344.Because the first weld pad 312a and the 3rd weld pad 344 all are positioned at wire bonds district 320; therefore the zone beyond the wire bonds district 320 on second protective layer 350 just can provide the platform of a carrying; to carry another chip structure; therefore, can form a kind of structure 30 of multi-chip migration storehouse.
Please refer to shown in Fig. 5 A and Fig. 5 B, be the structure 50 of a kind of multi-chip migration storehouse of the present invention.Shown in Fig. 5 A and Fig. 5 B, multi-chip migration stack architecture 50 is formed by a plurality of chip structure 500 storehouses, have on its chips 500 to reset and put layer 400, so the weld pad on the chip can be arranged on the wire bonds district 320 of chip 500, therefore this multi-chip migration stack architecture 50 is that alignment line forms with the edge line 322 in wire bonds district 320.And connect with adhesion layer between a plurality of chips 500.At first, please refer to Fig. 5 A, the adhesion layer 230 between the chip 500 is the back side that is positioned at chip 500, and this adhesion layer 230 generation types are finished simultaneously with chip shown in Fig. 2 A.Because being provided with to reset, the active face of chip 500 puts layer 400, so the weld pad on the chip can be arranged on the wire bonds district 320 of chip 500, therefore, adhesion layer 230 on chip 500 back sides and reseting of another chip 500 are put layer 400 to be offset after (0FFSET) engage, can form a kind of multi-chip migration stack architecture 50, the structure 50 of wherein this multi-chip migration storehouse is that reference data is arranged storehouse formation with the edge line 322 in wire bonds district 320, therefore can form similar stair-stepping multi-chip migration stack architecture 50, shown in Fig. 5 A.
In addition, the juncture of the structure 50 of multi-chip migration storehouse of the present invention also can be coated on adhesion layer reseting of chip 500 and put on the layer 400, shown in Fig. 5 B, adhesion layer 270 is coated on reseting of chip 500 to be put on the layer 400, and allow wire bonds district 320 expose, therefore, after reseting of chip 500 put the adhesion layer 270 of layer on 400 and the back side of another chip 500 engages, can form a kind of multi-chip migration stack architecture 50, the structure 50 of wherein this multi-chip migration storehouse is that the benchmark of reference is arranged storehouse and formed with the edge 322 in wire bonds district 320, therefore can form similar stair-stepping multi-chip migration stack architecture 50.Still will emphasize that at this adhesion layer 270 in present embodiment is not defined as above-described semi-curing glue, the purpose of this adhesion layer 270 is to form with substrate or chip to engage, therefore, have the materials with function of sticking together so long as have this, be embodiments of the present invention, for example: glued membrane.
Then, the present invention also proposes a kind of stack type chip package structure according to above-mentioned multi-chip migration stack architecture 30 and 50, and is described in detail as follows.Simultaneously, in following declarative procedure, will be that example carries out, yet be stressed that multi-chip migration stack architecture 30 also is suitable for the disclosed content of present embodiment with multi-chip migration stack architecture 50.
At first, please refer to Fig. 6, the lead frame floor map of stack type chip package structure of the present invention.As shown in Figure 6, stack type chip package structure comprises that lead frame 600 and multi-chip migration stack architecture 50 form, wherein interior pin 610 and the outer pin 620 relatively arranged by a plurality of one-tenth of lead frame 600 formed, and the length of pin 610 (the abbreviation first pin group) that wherein is positioned at the relative edge is greater than another relative edge's pin 610 (the abbreviation second pin group).In the present embodiment, stacking-type chip structure 50 is arranged on the first interior pin group 610, and via plain conductor 640 multi-chip migration stack architecture 50 is connected with the interior pin 610 of lead frame 600.In addition, the dotted line 601 among Fig. 6 is in order to the zone of pin in indicating 610 and outer pin 620, and this dotted line in fact is not exist on the lead frame 600.
Then please refer to Fig. 7 A to Fig. 7 C, the generalized section of multi-chip migration stack package structure of the present invention.At first, shown in Fig. 7 A, between the interior pin 610 of lead frame 600 and the multi-chip migration stack architecture 50 by with adhesion layer 270 as the material that engages.This adhesion layer 270 can be arranged on the interior pin group 610 of lead frame 600, is connected with multi-chip migration stack architecture 50 then; In addition, adhesion layer 270 also can be selected to be arranged on reseting of the uppermost chip 500 of Fig. 7 A and put on the layer 400, and the interior pin group 610 with lead frame 600 is connected with stack chip structure 50 then.Clearly, when stack chip structure 50 is Fig. 7 B, because being coated on reseting of chip 500, puts on the layer 400 adhesion layer 270, and after allowing wire bonds district 320 expose, so stack chip structure 50 directly can be engaged with the interior pin 610 of lead frame 600, shown in Fig. 7 B.
In addition, in the present embodiment, for the interior pin 610 of lead frame 600 and the juncture between the multi-chip migration stack architecture 50, also can select to use adhesive tape 520 as connecting material, particularly a kind of two-sided adhesive tape 520 with tackness, and adhesive tape 520 can be the structure of an integral body, can certainly be to be divided into a plurality of fragments, shown in Fig. 7 C.Adhesive tape 520 is attached at the back side (promptly be or reset the face that layer engages of putting) of pins 610 in the lead frame 600 earlier with the chip active face, and then with the chip active face or reset and put laminating and close, so can finish being connected of lead frame 600 and multi-chip migration stack architecture 50.Certainly, can earlier adhesive tape 520 be attached at the chip active face earlier yet or reset and put on the layer 400, and then fit with the interior pin 610 of lead frame 600, can reach identical purpose yet, to this, the present invention is not limited.
After finishing being connected of lead frame 600 and multi-chip migration stack architecture 50, carry out the connection of plain conductor immediately.Shown in Fig. 7 A, lead frame 600 is connected with many leads 640 with multi-chip migration stack architecture 50, and wherein lead frame 600 is made up of the interior pin 610 and the outer pin 620 of a plurality of relative arrangements.Lead 640 is connected in the end of lead 640a with wire bonding technique the weld pad of chip 500a, the first weld pad 312a or the 3rd weld pad 344 among for example above-mentioned Fig. 3, the other end of lead 640a then is connected on the first weld pad 312a or the 3rd weld pad 344 of chip 500b, then the end of lead 640b is connected in the first weld pad 312a or the 3rd weld pad 344 of chip 500b, the other end of lead 640b then is connected on the first weld pad 312a or the 3rd weld pad 344 of chip 500c, repeat the process of lead 640b again, chip 500c and 500d are finished electrical connection with lead 640c.Then, with lead 640d and 640e chip 500d is finished electrical connection with the interior pin 610 of a plurality of relative arrangements of lead frame 600.Thus, successively finish connection via lead 640a, 640b, 640c, 640d, 640e etc. after, just chip 500a, 500b, 500c and 500d can be electrically connected on lead frame 600, wherein the material of these leads 640 can be used gold.At last, the multi-chip migration stack package structure that to finish electrical connection again is covered on the interior pin 610 of multi-chip migration stack architecture 50 and lead frame 600 with the packing colloid (not shown), and the outer pin of lead frame 600 is exposed to the outer (not shown) of packing colloid, can forms stack type chip package structure.
In addition, the mode that connects lead frame 600 and multi-chip migration stack architecture 50 with plain conductor, except said process, after also can being chosen in the structure of finishing multi-chip migration stack architecture 50, promptly carry out chip 500a earlier, 500b, the plain conductor of 500c and 500d is electrically connected technology, the process of its connection is identical with said process, then, after the multi-chip migration stack architecture 50 that will finish electrical connection again and lead frame 600 stick together and are integral, carry out the technology of a plain conductor connection again, multi-chip migration stack architecture 50 finished with the interior pin 610 of lead frame 600 be connected, so also can finish Fig. 7 and (comprise Fig. 7 A, 7B, structure 7C).
Please continue with reference to Fig. 8, the present invention for lead frame 600 and multi-chip migration stack architecture 50 with another embodiment in the lead connection procedure.As shown in Figure 8, present embodiment lead frame 600 and multi-chip migration stack architecture 50 finish be connected after, and be before carrying out plain conductor 640 connections, earlier on the first weld pad 312a and the 3rd weld pad 344 in the wire bonds district 320 of chip 500, form metal coupling 650 (stud bump) earlier, and then carry out the connection procedure of above-mentioned lead 640a, 640b, 640c, 640d, 640e, chip 500a, 500b, 500c and 500d are electrically connected on lead frame 600.Add the purpose of this metal coupling 650,, can reduce the radian of lead 640a, 640b, 640c, 640d, 640e as sept (spacer).Be stressed that at this, the process that forms this metal coupling 650 can be implemented with the process that forms lead 640, that is to say that forming metal coupling 650 is to use same equipment just can reach with formation lead 640, therefore, the setting of increase metal coupling 650 can't increase the difficulty of technology with complicated.
Via above explanation, the embodiment described in the present invention does not limit the quantity of stack chip 500, and the person of ordinary skill in the field should be according to above-mentioned disclosed method, and produces the stack type chip package structure of the chip 500 that has more than three.Simultaneously, the multi-chip migration stack architecture 50 in Fig. 7 embodiment of (comprising Fig. 7 A, 7B, 7C) also can change multi-chip migration stack architecture 30 into, so multi-chip migration stack architecture 30 and schematic diagram after lead frame 600 engages are as shown in Figure 8.Because therefore these two multi-chip migration stack architectures 30 and multi-chip migration stack architecture 50 repeat no more all identical with plain conductor connection procedure after lead frame 600 engages.
In sum, chip structure proposed by the invention is except being in FEOL, just a plurality of weld pads on the chip are arranged at outside the side of chip, also disclose and comprise another way, it mainly is via the planning in suitable wire bonds district and resets and put line layer, first weld pad and the 3rd weld pad are concentrated on the single side of chip structure, make chip structure be suitable for via direct other chip structure of carrying in the zone beyond the wire bonds district.Therefore,, compare, just can have thin thickness, and have higher encapsulation integration with known technology via the stack type chip package structure that the said chip structure stack forms.
Apparently, according to the description among the top embodiment, the present invention has many corrections and difference.Therefore need be understood in the scope of its additional claim item, except above-mentioned detailed description, the present invention can also implement widely in other embodiments.Above-mentioned is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or improvement, all should be included in the claim.
Claims (10)
1. the encapsulating structure of a lead frame on multi-chip stack structure, comprise lead frame, formed by outer pin and the relative interior pin of arranging of a plurality of one-tenth that the formed a plurality of one-tenth of a plurality of leads are arranged relatively, wherein these a plurality of interior pin area are divided into the pin group and the second interior pin group in first, and this first interior pin group's length is greater than this second interior pin group, multi-chip stack structure, form and coat a plurality of outer pins of this multi-chip stack structure and this lead frame and this by a plurality of chip stacks and stretch out in outside this packaging body, it is characterized in that by packaging body:
The active face of each this chip in this multi-chip stack structure up and form the structure of skew stack arrangement with dislocation, wherein the chip of this stack arrangement the top is fixed under this first interior pin group, and this multi-chip stack structure is electrically connected with this second interior pin group with this first interior pin group by same side.
2. encapsulating structure according to claim 1 is characterized in that this multi-chip stack structure directly is electrically connected with this second interior pin group with this first interior pin group by the same side of the semiconductor chiop of stack arrangement the top.
3. encapsulating structure according to claim 1 is characterized in that directly being electrically connected each other by same side between each this chip in this multi-chip stack structure.
4. encapsulating structure according to claim 1, it is characterized in that in this multi-chip stack structure each chip by reset put the layer pad on this chip is arranged at same side.
5. encapsulating structure according to claim 1 is characterized in that each chip structure in this multi-chip stack structure comprises:
The chip body has the wire bonds zone, and this wire bonds zone is arranged at a side of this chip body, and wherein this chip body has a plurality of first weld pad and a plurality of extra-regional second weld pads of this wire bonds that are positioned at that are positioned at this wire bonds zone;
First protective layer is arranged on this chip body, and wherein this first protective layer has a plurality of first openings, to expose above-mentioned these first weld pads and above-mentioned these second weld pads;
Reset and put line layer, be arranged on this first protective layer, wherein this is reseted and puts line layer and extend in this wire bonds zone from above-mentioned these second weld pads, and this is reseted and puts line layer and have a plurality of the 3rd weld pads that are positioned at this wire bonds zone; And
Second protective layer is covered in this and resets and put on the line layer, and wherein this second protective layer has a plurality of second openings, to expose above-mentioned these first weld pads and above-mentioned these the 3rd weld pads.
6. encapsulating structure according to claim 1 is characterized in that this first interior pin group's lower surface is provided with viscose, is fixed under this first interior pin group so that the chip of stack arrangement the top sticks together.
7. encapsulating structure according to claim 5 is characterized in that further having the structure of projection on this first weld pad and the 3rd weld pad.
8. the encapsulating structure of a lead frame on multi-chip stack structure, comprise lead frame, formed by outer pin and the relative interior pin of arranging of a plurality of one-tenth that the formed a plurality of one-tenth of a plurality of leads are arranged relatively, it is characterized in that these a plurality of interior pin area are divided into the pin group and the second interior pin group in first, and this first interior pin group's length is greater than this second interior pin group, multi-chip stack structure, form and stick together by a plurality of chip stacks and be fixed in this in first under pin group and coat a plurality of outer pins of this multi-chip stack structure and this lead frame and this by packaging body and stretch out in outside this packaging body, it is characterized in that by the chip of the top:
The back side of respectively this chip in this multi-chip stack structure is provided with viscose, form the structure of active supine skew stack arrangement by the dislocation storehouse, wherein the chip of this stack arrangement the top be fixed in this in first under pin group and this multi-chip stack structure by same side with this in first pin group be electrically connected with this second interior pin group.
9. encapsulating structure according to claim 8, it is characterized in that in this multi-chip stack structure each chip by reset put the layer pad on this chip is arranged at same side.
10. encapsulating structure according to claim 8 is characterized in that each chip structure in this multi-chip stack structure comprises:
The chip body has the wire bonds zone, and this wire bonds zone is arranged at a side of this chip body, and wherein this chip body has a plurality of first weld pad and a plurality of extra-regional second weld pads of this wire bonds that are positioned at that are positioned at this wire bonds zone;
First protective layer is arranged on this chip body, and wherein this first protective layer has a plurality of first openings, to expose above-mentioned these first weld pads and above-mentioned these second weld pads;
Reset and put line layer, be arranged on this first protective layer, wherein this is reseted and puts line layer and extend in this wire bonds zone from above-mentioned these second weld pads, and this is reseted and puts line layer and have a plurality of the 3rd weld pads that are positioned at this wire bonds zone; And
Second protective layer is covered in this and resets and put on the line layer, and wherein this second protective layer has a plurality of second openings, to expose above-mentioned these first weld pads and above-mentioned these the 3rd weld pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610111923 CN101131993A (en) | 2006-08-24 | 2006-08-24 | Packaging structure of conducting wire holder on multi-chip stacking structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610111923 CN101131993A (en) | 2006-08-24 | 2006-08-24 | Packaging structure of conducting wire holder on multi-chip stacking structure |
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| CN101131993A true CN101131993A (en) | 2008-02-27 |
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| CN 200610111923 Pending CN101131993A (en) | 2006-08-24 | 2006-08-24 | Packaging structure of conducting wire holder on multi-chip stacking structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101740530A (en) * | 2008-11-25 | 2010-06-16 | 三星电子株式会社 | Integrated circuit substrate |
| CN102136467A (en) * | 2010-01-22 | 2011-07-27 | 三星电子株式会社 | Stacked package of semiconductor device |
| WO2017166325A1 (en) * | 2016-04-02 | 2017-10-05 | Intel Corporation | Semiconductor package with supported stacked die |
-
2006
- 2006-08-24 CN CN 200610111923 patent/CN101131993A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101740530A (en) * | 2008-11-25 | 2010-06-16 | 三星电子株式会社 | Integrated circuit substrate |
| CN102136467A (en) * | 2010-01-22 | 2011-07-27 | 三星电子株式会社 | Stacked package of semiconductor device |
| WO2017166325A1 (en) * | 2016-04-02 | 2017-10-05 | Intel Corporation | Semiconductor package with supported stacked die |
| US10796975B2 (en) | 2016-04-02 | 2020-10-06 | Intel Corporation | Semiconductor package with supported stacked die |
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