CN104465585A - Wafer level package structure and technological method thereof - Google Patents
Wafer level package structure and technological method thereof Download PDFInfo
- Publication number
- CN104465585A CN104465585A CN201410828468.XA CN201410828468A CN104465585A CN 104465585 A CN104465585 A CN 104465585A CN 201410828468 A CN201410828468 A CN 201410828468A CN 104465585 A CN104465585 A CN 104465585A
- Authority
- CN
- China
- Prior art keywords
- lead frame
- package structure
- level package
- disk
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention relates to a wafer level package structure and a technological method thereof. The wafer level package structure comprises a lead frame (1). A chip (2) is arranged on the lead frame (1) in an inversion mode. A metal bump (3) is arranged on the front face of the chip (2). The metal bump (3) is connected with the chip (2) through a solder ball (4). Non-conducting glue (5) is arranged on the periphery of the metal bump (3) and the periphery of the solder ball (4). A molding compound (6) is packaged on the periphery of the lead frame (1). A metal layer (7) is electroplated on the back face of the lead frame (1). According to the wafer level package structure and the technological method of the wafer level package structure, the drawing design on a wafer completely corresponds to a drawing of the lead frame, the whole chip is installed on the lead frame in the inversion mode and then is cut, separated and packaged, and wafer level package that the single chip size is equal to a single unit of the lead frame is achieved.
Description
Technical field
The present invention relates to a kind of wafer-level package structure and process thereof, belong to technical field of semiconductor encapsulation.
Background technology
Existing wafer level packaging, first scribing is carried out to disk, the chip front side be separated after completing scribing is pasted onto on support plate, again plastic packaging is carried out to the side of support plate adhering chip, remove support plate, exposed chip front, carries out Fanout to chip front side electrode and reroutes and make metallic circuit and the electrical output of product.After disk scribing, single chips arrangement is pasted onto on support plate and carries out encapsulating, making Fanout metallic circuit, the efficiency of arrangements of chips contraposition is low on the one hand, and separating chips arrangement contraposition easily produces offset deviation, this will cause the skew of follow-up chip front side Fanout metallic circuit; Carry out because disk Fanout is encapsulated in encapsulation factory, but carrying out for encapsulation factory the close pitch lines that Fanout technique relates to makes, difficulty is higher, and easily occur the problem that line short, circuit are peeled off, yield is on the low side.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, a kind of wafer-level package structure and process thereof are provided, plan design on disk is completely corresponding with the drawing of lead frame, realize the upside-down mounting of full wafer disk in lead frame, carry out cutting and separating and the encapsulation of disk again, realize the wafer-level packaging that single chips size is equal to lead frame single Unit.
The object of the present invention is achieved like this: a kind of wafer-level package structure, it comprises lead frame, on described lead frame, upside-down mounting has chip, described chip front side is provided with metal salient point, described metal salient point is connected by tin ball with between chip, be provided with non-conductive glue around described metal salient point and tin ball, be encapsulated with plastic packaging material around described lead frame, the described lead frame back side is electroplate with metal level.
A process for wafer-level package structure, said method comprising the steps of:
Step one, get a disk, disk front line design corresponds to lead frame drawing completely, and single chips size is equal to package dimension;
Step 2, on disk front electrode, make metal salient point;
Step 3, on metal salient point, make tin ball;
Step 4, be coated to the non-conductive glue of one deck completing the disk front that tin ball makes, and carry out the solidification of non-conductive glue;
Step 5, mill glue is carried out to disk front, expose the tin layers on metal pillar;
Step 6, will complete mill glue disk upside-down mounting in lead frame;
Step 7, the product completing upside-down mounting is put into solder reflow device carry out Reflow Soldering;
Step 8, plastic packaging is carried out to the product completing Reflow Soldering;
Step 9, carry out the plating of the lead frame back side to completing the product after plastic packaging;
Step 10, the product completing plating to be cut, be separated single product.
Described disk front circuit can carry out Fanout design according to lead frame drawing;
Described lead frame drawing can carry out matched design according to disk front circuit.
Described non-conductive glue is coated to the mode that mode adopts brush coating or whirl coating.
Compared with prior art, the present invention has following beneficial effect:
1, chip reroutes to make and is completed by the wafer FAB factory of being good at separately and encapsulation factory respectively with encapsulation, and product yield is higher;
2, lead frame single Unit size is equal to independent chip size, not only make use of die-attach area substantially, and can shorten product sizes, improves the utilance of lead frame, reduces material cost;
3, the upside-down mounting of full wafer disk completes, substantially increases production efficiency, reduces production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of wafer-level package structure of the present invention.
Fig. 2 ~ Figure 11 is each operation schematic diagram of a kind of wafer-level package structure of the present invention process.
Wherein:
Lead frame 1
Chip 2
Metal salient point 3
Tin ball 4
Non-conductive glue 5
Plastic packaging material 6
Metal level 7.
Embodiment
See Fig. 1, a kind of wafer-level package structure of the present invention, it comprises lead frame 1, on described lead frame 1, upside-down mounting has chip 2, described chip 2 front is provided with metal salient point 3, and described metal salient point 3 is connected by tin ball 4 with between chip 2, is provided with non-conductive glue 5 around described metal salient point 3 and tin ball 4, be encapsulated with plastic packaging material 6 around described lead frame 1, described lead frame 1 back side is electroplate with metal level 7.
Its process is as follows:
Step one, see Fig. 2, get a disk, disk front line design corresponds to lead frame drawing completely, and single chips size is equal to package dimension;
Step 2, see Fig. 3, disk front electrode makes metal salient point;
Step 3, see Fig. 4, metal salient point makes tin ball;
Step 4, see Fig. 5, be coated to the non-conductive glue of one deck completing the disk front that tin ball makes, and carry out the solidification of non-conductive glue, coating mode can adopt brush coating, whirl coating;
Step 5, see Fig. 6, mill glue is carried out to disk front, expose the tin layers on metal pillar;
Step 6, see Fig. 7, will complete mill glue disk upside-down mounting in lead frame;
Step 7, see Fig. 8, the product completing upside-down mounting is put into solder reflow device and carries out Reflow Soldering;
Step 8, see Fig. 9, plastic packaging is carried out to the product completing Reflow Soldering;
Step 9, see Figure 10, carry out the plating of the lead frame back side to completing the product after plastic packaging;
Step 10, see Figure 11, the product completing plating to be cut, be separated single product.
Described disk front circuit can carry out Fanout design according to lead frame drawing;
Described lead frame drawing can carry out matched design according to disk front circuit.
Claims (4)
1. a wafer-level package structure, it is characterized in that: it comprises lead frame (1), the upper upside-down mounting of described lead frame (1) has chip (2), described chip (2) front is provided with metal salient point (3), be connected by tin ball (4) between described metal salient point (3) with chip (2), described metal salient point (3) and tin ball (4) are provided with non-conductive glue (5) around, described lead frame (1) is encapsulated with plastic packaging material (6) around, and described lead frame (1) back side is electroplate with metal level (7).
2. a process for wafer-level package structure, is characterized in that said method comprising the steps of:
Step one, get a disk, disk front line design corresponds to lead frame drawing completely, and single chips size is equal to package dimension;
Step 2, on disk front electrode, make metal salient point;
Step 3, on metal salient point, make tin ball;
Step 4, be coated to the non-conductive glue of one deck completing the disk front that tin ball makes, and carry out the solidification of non-conductive glue;
Step 5, mill glue is carried out to disk front, expose the tin layers on metal pillar;
Step 6, will complete mill glue disk upside-down mounting in lead frame;
Step 7, the product completing upside-down mounting is put into solder reflow device carry out Reflow Soldering;
Step 8, plastic packaging is carried out to the product completing Reflow Soldering;
Step 9, carry out the plating of the lead frame back side to completing the product after plastic packaging;
Step 10, the product completing plating to be cut, be separated single product.
3. the process of a kind of wafer-level package structure according to claim 2, is characterized in that: described non-conductive glue is coated to the mode that mode adopts brush coating or whirl coating.
4. the process of a kind of wafer-level package structure according to claim 2, is characterized in that: described disk front circuit carries out Fanout design according to lead frame drawing or lead frame drawing carries out matched design according to disk front circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410828468.XA CN104465585A (en) | 2014-12-26 | 2014-12-26 | Wafer level package structure and technological method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410828468.XA CN104465585A (en) | 2014-12-26 | 2014-12-26 | Wafer level package structure and technological method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104465585A true CN104465585A (en) | 2015-03-25 |
Family
ID=52911397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410828468.XA Pending CN104465585A (en) | 2014-12-26 | 2014-12-26 | Wafer level package structure and technological method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104465585A (en) |
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| CN103474358A (en) * | 2013-09-29 | 2013-12-25 | 华进半导体封装先导技术研发中心有限公司 | Multi-circle QFN package lead frame manufacturing method |
| CN103745931A (en) * | 2013-12-05 | 2014-04-23 | 南通富士通微电子股份有限公司 | Lead frame and packaging structure forming methods |
| CN103824785A (en) * | 2013-12-05 | 2014-05-28 | 南通富士通微电子股份有限公司 | Package structure forming method |
| CN103903989A (en) * | 2014-02-24 | 2014-07-02 | 南通富士通微电子股份有限公司 | Method for forming semiconductor packaging structure |
| CN103972113A (en) * | 2014-05-22 | 2014-08-06 | 南通富士通微电子股份有限公司 | Packaging method |
| CN103972218A (en) * | 2014-04-26 | 2014-08-06 | 华进半导体封装先导技术研发中心有限公司 | Integrated passive device fan-out-type wafer-level packaging structure and manufacturing method thereof |
| CN204375738U (en) * | 2014-12-26 | 2015-06-03 | 江苏长电科技股份有限公司 | Wafer-level package structure |
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2014
- 2014-12-26 CN CN201410828468.XA patent/CN104465585A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103280449A (en) * | 2013-05-16 | 2013-09-04 | 华进半导体封装先导技术研发中心有限公司 | Method for manufacturing backside illuminated (BSI) CMOS image sensor |
| CN103474358A (en) * | 2013-09-29 | 2013-12-25 | 华进半导体封装先导技术研发中心有限公司 | Multi-circle QFN package lead frame manufacturing method |
| CN103745931A (en) * | 2013-12-05 | 2014-04-23 | 南通富士通微电子股份有限公司 | Lead frame and packaging structure forming methods |
| CN103824785A (en) * | 2013-12-05 | 2014-05-28 | 南通富士通微电子股份有限公司 | Package structure forming method |
| CN103903989A (en) * | 2014-02-24 | 2014-07-02 | 南通富士通微电子股份有限公司 | Method for forming semiconductor packaging structure |
| CN103972218A (en) * | 2014-04-26 | 2014-08-06 | 华进半导体封装先导技术研发中心有限公司 | Integrated passive device fan-out-type wafer-level packaging structure and manufacturing method thereof |
| CN103972113A (en) * | 2014-05-22 | 2014-08-06 | 南通富士通微电子股份有限公司 | Packaging method |
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|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150325 |