CN204375734U - Framework is utilized to encapsulate the wire bonding and packaging structure rerouted - Google Patents

Framework is utilized to encapsulate the wire bonding and packaging structure rerouted Download PDF

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Publication number
CN204375734U
CN204375734U CN201420839159.8U CN201420839159U CN204375734U CN 204375734 U CN204375734 U CN 204375734U CN 201420839159 U CN201420839159 U CN 201420839159U CN 204375734 U CN204375734 U CN 204375734U
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China
Prior art keywords
framework
pin
chip
dao
substrate
Prior art date
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Active
Application number
CN201420839159.8U
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Chinese (zh)
Inventor
郭小伟
龚臻
于睿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to CN201420839159.8U priority Critical patent/CN204375734U/en
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Publication of CN204375734U publication Critical patent/CN204375734U/en
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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Abstract

The utility model relates to a kind of framework that utilizes and encapsulates the wire bonding and packaging structure rerouted, and belongs to integrated circuit or discrete component encapsulation technology field.It comprises substrate (1), described substrate (1) back side is provided with the first tin ball (2), described substrate (1) front is provided with packaging body (3) by the second tin ball (4), described packaging body (3) comprises Ji Dao (5) and pin (6), described Ji Dao (5) front is provided with chip (7), be connected by metal wire (8) between described chip (7) front with pin (6) front, described Ji Dao (5), pin (6) and chip (7) are encapsulated with plastic packaging material (9) around, described Ji Dao (5) and pin (6) back side flush with plastic packaging material (9) back side.A kind of framework that utilizes of the utility model encapsulates the wire bonding and packaging structure rerouted, and it can utilize framework to realize rerouting of chip.

Description

Framework is utilized to encapsulate the wire bonding and packaging structure rerouted
Technical field
The utility model relates to a kind of framework that utilizes and encapsulates the wire bonding and packaging structure rerouted, and belongs to integrated circuit or discrete component encapsulation technology field.
Background technology
1, to be encapsulated in IO number more for conventional routing substrate, and when 2 laminar substrates cannot meet wiring space, common solution uses 4 laminar substrates instead.But compare 2 laminar substrates, 4 laminar substrates have that complex process, cost are high, yield is low, shortcoming that design, manufacturing cycle are long.Or utilize 4 laminar substrates to replace 6 laminar substrates that yield is lower, cost is higher;
2, the chip of some particular design does not mate with common skeleton, cannot realize encapsulation, then need the circuit carrying out chip to reroute.This part technique needs to complete in FAB factory, and common encapsulation factory cannot independently carry out, and cost is very high, and industry production capacity is low.
Utility model content
The purpose of this utility model is to overcome above-mentioned deficiency, and provide a kind of framework that utilizes to encapsulate the wire bonding and packaging structure rerouted, it can utilize framework to realize rerouting of chip.
The purpose of this utility model is achieved in that a kind of framework that utilizes encapsulates the wire bonding and packaging structure rerouted, it comprises substrate, described substrate back is provided with the first tin ball, described substrate front side is provided with packaging body by the second tin ball, described packaging body comprises Ji Dao and pin, described Ji Dao front is provided with chip, be connected by metal wire between described chip front side with pin front, described Ji Dao, pin and chip circumference are encapsulated with plastic packaging material, and described Ji Dao and the pin back side flush with the plastic packaging material back side.
Compared with prior art, the utility model has following beneficial effect:
1, frame metal circuit is utilized, RDL(Redistribution Layer is provided) layer to be to realize the multilayer winding of substrate or to evade the function of short circuit, save substrate design space, it is made namely to reach the wiring effect of 4 laminar substrates with 2 laminar substrates, not only can simplify substrate manufacture technique, improve the yield of substrate, and save substrate cost;
2, the RDL utilizing framework encapsulation procedure to realize circuit makes, and makes the chip of some particular design utilize common skeleton can also realize encapsulation, can complete the technique that reroutes needing just can provide in specific vendor.
Accompanying drawing explanation
Fig. 1 is a kind of schematic diagram utilizing framework to encapsulate the wire bonding and packaging structure rerouted of the utility model.
Fig. 2 ~ Figure 12 is a kind of each operation schematic diagram utilizing framework to encapsulate the wire bonding and packaging structure manufacture method rerouted of the utility model.
Wherein:
Substrate 1
First tin ball 2
Packaging body 3
Second tin ball 4
Base island 5
Pin 6
Chip 7
Metal wire 8
Plastic packaging material 9.
Embodiment
See Fig. 1, a kind of framework that utilizes of the utility model encapsulates the wire bonding and packaging structure rerouted, it comprises substrate 1, described substrate 1 back side is provided with the first tin ball 2, described substrate 1 front is provided with packaging body 3 by the second tin ball 4, described packaging body 3 comprises base island 5 and pin 6, front, described base island 5 is provided with chip 7, described chip 7 front is connected by metal wire 8 with between pin 6 front, be encapsulated with plastic packaging material 9 around described base island 5, pin 6 and chip 7, described base island 5 and pin 6 back side flush with plastic packaging material 9 back side.
Its manufacture method is as follows:
Step one, see Fig. 2 or Fig. 3, get a metal framework, framework upper strata is line layer, and lower floor is supporting layer, and the line layer on upper strata can provide coiling or short-circuit function,
Step 2, see Fig. 4, in the enterprising luggage sheet of the framework of step one;
Step 3, see Fig. 5, the framework of load carries out routing, if the line terminal of metal framework as shown in Figure 3, line layer surface portion coating solder mask (line layer is covered green paint) then need exposed, only reserve and need windowing (as shown in figure 12) of scolding tin, overflow to prevent tin cream extensions road; If round for shown in Fig. 2 of metal framework line terminal, then do not cover green paint, also can play the effect preventing tin cream extensions road from overflowing;
Step 4, see Fig. 6, routing product to be encapsulated;
Step 5, see Fig. 7, packaged products is removed framework lower support layer, exposes line layer;
Step 6, see Fig. 8, thinning for whole piece product is cut into independently unit;
Step 7, see Fig. 9, the separate unit of cutting is mounted on substrate;
Step 8, see Figure 10, carry out planting ball at substrate back;
Step 9, see Figure 11, obtain independently encapsulation unit by die-cut for the substrate of planting ball.

Claims (1)

1. one kind utilizes framework to encapsulate the wire bonding and packaging structure rerouted, it is characterized in that: it comprises substrate (1), described substrate (1) back side is provided with the first tin ball (2), described substrate (1) front is provided with packaging body (3) by the second tin ball (4), described packaging body (3) comprises Ji Dao (5) and pin (6), described Ji Dao (5) front is provided with chip (7), be connected by metal wire (8) between described chip (7) front with pin (6) front, described Ji Dao (5), pin (6) and chip (7) are encapsulated with plastic packaging material (9) around, described Ji Dao (5) and pin (6) back side flush with plastic packaging material (9) back side.
CN201420839159.8U 2014-12-26 2014-12-26 Framework is utilized to encapsulate the wire bonding and packaging structure rerouted Active CN204375734U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201420839159.8U CN204375734U (en) 2014-12-26 2014-12-26 Framework is utilized to encapsulate the wire bonding and packaging structure rerouted

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201420839159.8U CN204375734U (en) 2014-12-26 2014-12-26 Framework is utilized to encapsulate the wire bonding and packaging structure rerouted

Publications (1)

Publication Number Publication Date
CN204375734U true CN204375734U (en) 2015-06-03

Family

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Country Status (1)

Country Link
CN (1) CN204375734U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104485322A (en) * 2014-12-26 2015-04-01 江苏长电科技股份有限公司 Routing packaging structure for packaging and re-routing by utilizing frame and manufacturing method of routing packaging structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104485322A (en) * 2014-12-26 2015-04-01 江苏长电科技股份有限公司 Routing packaging structure for packaging and re-routing by utilizing frame and manufacturing method of routing packaging structure

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