CN103199075A - Wafer level semiconductor encapsulation structure with stacking chips and manufacturing method thereof - Google Patents

Wafer level semiconductor encapsulation structure with stacking chips and manufacturing method thereof Download PDF

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Publication number
CN103199075A
CN103199075A CN2013100802050A CN201310080205A CN103199075A CN 103199075 A CN103199075 A CN 103199075A CN 2013100802050 A CN2013100802050 A CN 2013100802050A CN 201310080205 A CN201310080205 A CN 201310080205A CN 103199075 A CN103199075 A CN 103199075A
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chip
terminal
lead frame
active surface
wafer level
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Inventor
唐和明
洪志斌
赵兴华
刘昭源
陈国华
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN2013100802050A priority Critical patent/CN103199075A/en
Publication of CN103199075A publication Critical patent/CN103199075A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention provides a wafer level semiconductor encapsulation structure with stacking chips and a manufacturing method of the wafer level semiconductor encapsulation structure. The wafer level semiconductor encapsulation structure comprises a first chip, a plurality of wire frame terminals, a second chip and encapsulation colloid, wherein the first chip is provided with a downward active surface, the wire frame terminals surround the first chip, the second chip is stacked on the first chip in an insulation mode and provided with an upward active surface, the active surface of the second chip is electrically connected to the wire frame terminals through metal wires, the encapsulation colloid covers the first chip, the wire frame terminals and the second chip, and the active surface of the first chip and the bottom faces of the wire frame terminals are exposed. According to the wafer level semiconductor encapsulation structure with the stacking chips, chip stacking is achieved through connection of the wire frame terminals and the metal wires, the size of a product and structural stress can be effectively reduced.

Description

Wafer level semiconductor packaging structure and the manufacture method thereof of tool stacked chips
Technical field
The present invention relates to a kind of semiconductor packaging structure, particularly relevant for a kind of wafer level semiconductor packaging structure and manufacture method thereof of tool stacked chips.
Background technology
Be directly to carry out again wafer being made cutting operation afterwards in the packaging operation at wafer in general wafer-level packaging manufacturing process, finish the making of semiconductor die package structure.Because wafer-level packaging can be by finish all component configuration processing procedures before the wafer cutting, can effectively reduce the cost of entire product CT Cycle Time, and can reach the smaller szie encapsulation, accomplish compact requirement, its electric connection aspect possesses shorter transmission line, so wafer-level packaging is a kind of packaged type that can effectively save space and cost.
For design requirement, fan-out wafer scale (Fan out WLP) semiconductor packages structure can be designed to not only comprise a chips at present.Yet the general way that realizes having fan-out wafer scale (Fan out WLP) the semiconductor packages structure of multiple chips is to adopt side by side (side by side) to arrange chip or piling up (stacking) arranges.Wherein, the product horizontal size after the mode that adopts (side by side) side by side that chip is set can cause encapsulating significantly increases and its encapsulating structure can be subjected to bigger stress influence; In addition, what setting was piled up in employing is by straight-through silicon perforation (through silicon via) manufacture craft as rule, so that the upper strata chip can be electrically connected to the bottom circuit of lower floor's chip by via, so the shortcoming of the practice is that the cost of through hole forming technology is too high.
So, be necessary to provide a kind of wafer level semiconductor packaging structure and manufacture method thereof, to solve the existing in prior technology problem.
Summary of the invention
Main purpose of the present invention is to provide a kind of wafer level semiconductor packaging structure of tool stacked chips, and it reaches chip-stacked by lead frame and lead, can effectively reduce product size and the structural stress of wafer level semiconductor packaging structure.
For reaching aforementioned purpose, one embodiment of the invention provides a kind of wafer level semiconductor packaging structure of tool stacked chips, and described wafer level semiconductor packaging structure comprises: one first chip has down an active surface; A plurality of lead frame terminals, described lead frame terminal is around described first chip; One second chip, insulation is stacked on described first chip, and has up an active surface, and the active surface of described second chip is electrically connected to described lead frame terminal by lead; One packing colloid coats described first chip, described lead frame terminal and described second chip, and the active surface of exposed described first chip and the bottom surface of described lead frame terminal; And the layer that reroutes, forming in the active face side of described first chip and electrically connect described first chip and described lead frame terminal, the described layer bottom surface of rerouting is provided with several metallic conduction spares.
Moreover, another embodiment of the present invention provides a kind of manufacture method of wafer level semiconductor packaging structure of tool stacked chips, described manufacture method comprises step: a conductive wire frame strip is set on a carrier, wherein said conductive wire frame strip comprises a plurality of lead frame unit, and each described lead frame unit comprises a plurality of lead frame terminals; Corresponding each lead frame unit arranges one first chip on described carrier, makes described lead frame terminal around described first chip, and an active surface of wherein said first chip down; Arrange on one second chip on each described first chip, an active surface of wherein said second chip up; Electrically connect active surface and the described lead frame terminal of described second chip by lead; Form packing colloid, to coat described first chip, described second chip and described lead frame terminal; Remove described carrier, make the active surface of described first chip exposed with described lead frame terminal; And form the layer that reroutes, make the described layer that reroutes electrically connect active surface and the described lead frame terminal of described first chip.
The wafer level semiconductor packaging structure of tool stacked chips of the present invention uses does not have a lead frame of chip bearing to cooperate routing technology to realize in the framework of wafer level semiconductor packaging structure chip-stacked at the design requirement that descends chip, can effectively reduce product size and the structural stress of wafer level semiconductor packaging structure, and do not need to save packaging cost relatively by the higher through hole manufacture craft of cost.
Description of drawings
Fig. 1 is the structural representation of wafer level semiconductor packaging structure of the tool stacked chips of one embodiment of the invention.
Fig. 2 is the structural representation of wafer level semiconductor packaging structure of the tool stacked chips of another embodiment of the present invention.
Fig. 3 is the structural representation of wafer level semiconductor packaging structure of the tool stacked chips of further embodiment of this invention.
Fig. 4 is the floor map in order to the conductive wire frame strip of the wafer level semiconductor packaging structure of making the tool stacked chips of one embodiment of the invention.
Fig. 5 A～5F is the manufacturing process schematic diagram of wafer level semiconductor packaging structure of the tool stacked chips of one embodiment of the invention.
Embodiment
For allowing above-mentioned purpose of the present invention, feature and advantage become apparent, preferred embodiment of the present invention cited below particularly, and conjunction with figs. are described in detail below.Moreover, the direction term that the present invention mentions, for example " on ", D score, " preceding ", " back ", " left side ", " right side ", " interior ", " outward ", " side " etc., only be the direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the present invention, but not in order to limit the present invention.
Please refer to shown in Figure 1ly, Fig. 1 is the structural representation of wafer level semiconductor packaging structure of the tool stacked chips of one embodiment of the invention.The wafer level semiconductor packaging structure of the tool stacked chips that Fig. 1 discloses mainly comprises one first chip 1, a plurality of lead frame terminal 200, one second chip 3 and a packing colloid 4.
Described first chip 1 has down active surperficial 10, and namely described first chip 1 belongs to a flip chip type (flip chip).
Described lead frame terminal 200 similar existing square surfaces do not have the conducting wire frame structure that pin package structure (QFN) uses, but do not possess the chip bearing, only comprise the part of splicing ear.Described first chip 1 namely is positioned at the position of chip bearing originally, and 200 of described a plurality of splicing ears center on described first chip 1.
3 insulation of described second chip are stacked on described first chip 1 and (for example attach by the glue material), and have one up active surperficial 30, active surperficial 30 of described second chip 3 is provided with connection pad, and its connection pad is electrically connected to described lead frame terminal 200 by plain conductor 300.Described second chip 3 belongs to a routing (wire bonding) cake core.
Described packing colloid 4 can be epoxy resin or similar resin material, and it coats described first chip 1, described lead frame terminal 200 and described second chip 3, and the bottom surface of active surperficial 10 and described lead frame terminal 200 of exposed described first chip 1.
As shown in Figure 1, in one embodiment, described wafer level semiconductor packaging structure further comprises the layer 5 that reroutes.The described layer 5 that reroutes forms in the active face side of described first chip 1 and electrically connects described first chip 1 and described lead frame terminal 200, reach the encapsulation of fan-out formula to rearrange I/O port layout by the described layer 5 that reroutes, described layer 5 bottom surface of rerouting are provided with several metallic conduction spares 50, for example the tin ball.
The wafer level semiconductor packaging structure of above-mentioned tool stacked chips uses does not have the lead frame terminal complexed metal lead technology of chip bearing and has realized chip-stacked at the design requirement of chip down in the framework of wafer level semiconductor packaging structure, thus, can not increase the horizontal size of packaging structure and the structural stress at place, bottom surface, do not need to save the packaging cost of wafer level semiconductor packaging structure relatively by the higher through hole manufacture craft of cost yet.
Please further with reference to shown in Figure 2, Fig. 2 is the structural representation of wafer level semiconductor packaging structure of the tool stacked chips of another embodiment of the present invention, follow layout designs according to different I/O number demands, described lead frame terminal 200 can for example comprise a plurality of the first terminal 200a and a plurality of second terminal 200b that are positioned at the outer ring that are positioned at inner ring, and active surperficial 30 of described second chip 3 are electrically connected to described the first terminal 200a and the second terminal 200b by many strip metals lead 300.
Moreover the present invention also is not limited to chip-stacked number, and for example, embodiment as shown in Figure 3, described wafer level semiconductor packaging structure further comprise at least one the 3rd chip 6.Wherein, described lead frame terminal 200 comprises a plurality of the first terminal 200a and a plurality of second terminal 200b that are positioned at the outer ring that are positioned at inner ring, and active surperficial 30 of described second chip 3 is electrically connected to described the first terminal 200a by plain conductor 300; 6 insulation of described the 3rd chip are stacked on described second chip 3, and have up active surperficial 60, and active surperficial 60 of described the 3rd chip 6 is electrically connected to the described second terminal 200b by plain conductor 600.
The wafer level semiconductor packaging structure of tool stacked chips of the present invention mainly is the setting that adds lead frame and plain conductor in the wafer-level packaging process.Please further with reference to shown in figure 4 and Fig. 5 A～5F, Fig. 5 A～5F is the manufacturing process schematic diagram of making the wafer level semiconductor packaging structure of tool stacked chips as shown in Figure 1 to detailed manufacture method.It is as follows that described manufacture method comprises step:
Please refer to shown in Fig. 5 A, a conductive wire frame strip 2 at first is set on a carrier 7, wherein as shown in Figure 4, described conductive wire frame strip 2 comprises the lead frame unit 20 that a plurality of one-tenth matrixes are arranged, and each described lead frame unit 20 comprises a plurality of lead frame terminals 200; On the described carrier 7 adhesive tape 70 can be set earlier, then described conductive wire frame strip 2 just be set on described carrier 7.It should be noted that described conductive wire frame strip 2 and described carrier 7 preferably all have the size of a similar heavy distribution wafer and circular edge.
Please refer to shown in Fig. 5 B, then the center corresponding to each lead frame unit 20 arranges one first chip 1 on described carrier 7, makes described lead frame terminal 200 around described first chip 1, wherein said first chip 1 one active surperficial 10 down.
Please refer to Fig. 5 C, then further on each described first chip 1, arrange on one second chip 3, wherein said second chip 3 one active surperficial 30 up; And by routing technology plain conductor 300 is set, makes it electrically connect active surperficial 30 and described lead frame terminal 200 of described second chip 3.
Please refer to Fig. 5 D, then carry out packaging operation, form packing colloid 4, to coat described first chip 1, described second chip 3 and described lead frame terminal 200.
Please refer to Fig. 5 E, then remove described carrier 7 (comprising the adhesive tape 70 on the carrier 7), make active surperficial 10 of described first chip 1 follow described lead frame terminal 200 to expose.
Please refer to Fig. 5 F, (RDL) technology reroutes, form the layer 5 that reroutes at active surperficial 10 of exposed described first chip 1 with described lead frame terminal 200, make the described layer 5 that reroutes electrically connect active surperficial 10 and described lead frame terminal 200 of described first chip 1, and in described layer 5 bottom surface of rerouting metallic conduction spare 50 is set, for example the tin ball.
At last, be that unit carries out cutting operation again with the lead frame unit, can form the wafer level semiconductor packaging structure of a plurality of independent tool stacked chips.
The visual different packaging structures design of above-mentioned manufacture method is adjusted, for example the lead frame terminal 200 of each described lead frame unit can comprise a plurality of the first terminal 200a and a plurality of second terminal 200b that are positioned at the outer ring that are positioned at inner ring, makes that active surperficial 30 of described second chip 3 are electrically connected to described the first terminal 200a and the second terminal 200b by plain conductor 300.Or active surperficial 30 of described second chip 3 is electrically connected to described the first terminal 200a by plain conductor 300; Before forming the step of packing colloid, further in each described second chip 3 at least one the 3rd chip 6 is set subsequently, wherein said the 3rd chip 6 have one up active surperficial 60; Electrically connect active surperficial 60 and the described second terminal 200b of described the 3rd chip 6 again by plain conductor 600.
In sum, compared to the wafer level semiconductor packaging structure of existing tool stacked chips, adopting the mode that is arranged side by side chip to have horizontal size significantly increases and stress problem; And adopt straight-through silicon perforation to pile up to arrange chip to make the rule cost too high, the present invention is not had a lead frame of chip bearing to cooperate routing technology to realize in the framework of wafer level semiconductor packaging structure chip-stacked at the design requirement that descends chip by using, can effectively reduce product size and the structural stress of wafer level semiconductor packaging structure, and do not need to save packaging cost relatively by the higher through hole manufacture craft of cost.Simultaneously if last chip based on analogy integrated circuit, power IC, then the setting of plain conductor is for these wafer level semiconductor packaging structure products, and the conducting path of power supply preferably or ground connection also can be provided.
The present invention is described by above-mentioned related embodiment, yet above-described embodiment is only for implementing example of the present invention.Must be pointed out that disclosed embodiment does not limit the scope of the invention.On the contrary, being contained in the spirit of claims and modification and impartial setting of scope is included in the scope of the present invention.

Claims (9)

1. the wafer level semiconductor packaging structure of a tool stacked chips, it is characterized in that: it comprises:
One first chip has down an active surface;
A plurality of lead frame terminals, described lead frame terminal is around described first chip;
One second chip, insulation is stacked on described first chip, and has up an active surface, and the active surface of described second chip is electrically connected to described lead frame terminal by lead;
One packing colloid coats described first chip, described lead frame terminal and described second chip, and the active surface of exposed described first chip and the bottom surface of described lead frame terminal; And
One layer that reroutes forms in the active face side of described first chip and electrically connects described first chip and described lead frame terminal, and the described layer bottom surface of rerouting is provided with several metallic conduction spares.
2. the wafer level semiconductor packaging structure of tool stacked chips as claimed in claim 1, it is characterized in that: described lead frame terminal comprises a plurality of the first terminal and a plurality of second terminals that are positioned at the outer ring that are positioned at inner ring, and the active surface electrical behavior of described second chip is connected to described the first terminal; Described wafer level semiconductor packaging structure further comprises at least one the 3rd chip, and insulation is stacked on described second chip, and has up an active surface, and the active surface of described the 3rd chip is electrically connected to described second terminal by lead.
3. the wafer level semiconductor packaging structure of tool stacked chips as claimed in claim 1, it is characterized in that: described lead frame terminal comprises a plurality of the first terminal and a plurality of second terminals that are positioned at the outer ring that are positioned at inner ring, and the active surface of described second chip is electrically connected to described the first terminal and second terminal by lead.
4. the manufacture method of the wafer level semiconductor packaging structure of a tool stacked chips, it is characterized in that: described manufacture method comprises step:
One conductive wire frame strip is set on a carrier, wherein said conductive wire frame strip comprises a plurality of lead frame unit, and each described lead frame unit comprises a plurality of lead frame terminals;
Corresponding each lead frame unit arranges one first chip on described carrier, makes described lead frame terminal around described first chip, and an active surface of wherein said first chip down;
Arrange on one second chip on each described first chip, an active surface of wherein said second chip up;
Electrically connect active surface and the described lead frame terminal of described second chip by lead;
Form packing colloid, to coat described first chip, described second chip and described lead frame terminal;
Remove described carrier, make the active surface of described first chip exposed with described lead frame terminal; And form the layer that reroutes, make the described layer that reroutes electrically connect active surface and the described lead frame terminal of described first chip.
5. the manufacture method of the wafer level semiconductor packaging structure of tool stacked chips as claimed in claim 4 is characterized in that: further comprise step: in the described layer bottom surface of rerouting metallic conduction spare is set.
6. the manufacture method of the wafer level semiconductor packaging structure of tool stacked chips as claimed in claim 5 is characterized in that: further comprise step: be that unit carries out cutting operation with the lead frame unit, to form a plurality of packaging structures.
7. the manufacture method of the wafer level semiconductor packaging structure of tool stacked chips as claimed in claim 4, it is characterized in that: the lead frame terminal of each described lead frame unit comprises a plurality of the first terminal and a plurality of second terminals that are positioned at the outer ring that are positioned at inner ring, and the active surface of wherein said second chip is electrically connected to described the first terminal and second terminal by lead.
8. the manufacture method of the wafer level semiconductor packaging structure of tool stacked chips as claimed in claim 4, it is characterized in that: the lead frame terminal of each described lead frame unit comprises a plurality of the first terminal and a plurality of second terminals that are positioned at the outer ring that are positioned at inner ring, and the active surface of wherein said second chip is electrically connected to described the first terminal by lead.
9. the manufacture method of the wafer level semiconductor packaging structure of tool stacked chips as claimed in claim 8, it is characterized in that: before the step that forms packing colloid, described manufacture method also comprises step: on each described second chip at least one the 3rd chip is set, wherein said the 3rd chip has up an active surface; And the active surface and described second terminal that electrically connect described the 3rd chip by lead.
CN2013100802050A 2013-03-13 2013-03-13 Wafer level semiconductor encapsulation structure with stacking chips and manufacturing method thereof Pending CN103199075A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867913A (en) * 2015-03-30 2015-08-26 中国电子科技集团公司第三十八研究所 Three-dimensional packaging structure for multi-chip mixing integration and processing method thereof
CN106531715A (en) * 2015-09-11 2017-03-22 联发科技股份有限公司 System-in-package and fabrication method thereof
CN107871732A (en) * 2016-09-23 2018-04-03 深圳市中兴微电子技术有限公司 Encapsulating structure
US10074628B2 (en) 2013-10-04 2018-09-11 Mediatek Inc. System-in-package and fabrication method thereof
US10103128B2 (en) 2013-10-04 2018-10-16 Mediatek Inc. Semiconductor package incorporating redistribution layer interposer
US11189500B2 (en) 2018-11-20 2021-11-30 AT&S (Chongqing) Company Limited Method of manufacturing a component carrier with an embedded cluster and the component carrier

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Application publication date: 20130710