CN204375729U - A kind of novel wafer-level package structure - Google Patents

A kind of novel wafer-level package structure Download PDF

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Publication number
CN204375729U
CN204375729U CN201420844996.XU CN201420844996U CN204375729U CN 204375729 U CN204375729 U CN 204375729U CN 201420844996 U CN201420844996 U CN 201420844996U CN 204375729 U CN204375729 U CN 204375729U
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China
Prior art keywords
substrate
chip
disk
wafer
package structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201420844996.XU
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Chinese (zh)
Inventor
梁志忠
王亚琴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201420844996.XU priority Critical patent/CN204375729U/en
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Publication of CN204375729U publication Critical patent/CN204375729U/en
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The utility model relates to a kind of novel wafer-level package structure, described structure comprises substrate (1), described substrate (1) front upside-down mounting has chip (2), described chip (2) front is provided with metal salient point (3), be connected by tin ball (4) between described metal salient point (3) with substrate (1), underfill (5) is provided with between described chip (2) front and substrate (1), described chip (2) back side is encapsulated with plastic packaging material (6), and described substrate (1) back side is electroplate with metal level (7).A kind of novel wafer-level package structure of the utility model, plan design on disk is completely corresponding with the drawing of lead frame, realize the upside-down mounting of full wafer disk in lead frame, then carry out cutting and separating and the encapsulation of disk, realize the wafer-level packaging that single chips size is equal to lead frame single Unit.

Description

A kind of novel wafer-level package structure
Technical field
The utility model relates to a kind of novel wafer-level package structure, belongs to technical field of semiconductor encapsulation.
Background technology
Existing wafer level packaging, first scribing is carried out to disk, the chip front side be separated after completing scribing is pasted onto on support plate, again plastic packaging is carried out to the side of support plate adhering chip, remove support plate, exposed chip front, carries out Fanout to chip front side electrode and reroutes and make metallic circuit and the electrical output of product.After disk scribing, single chips arrangement is pasted onto on support plate and carries out encapsulating, making Fanout metallic circuit, the efficiency of arrangements of chips contraposition is low on the one hand, and separating chips arrangement contraposition easily produces offset deviation, this will cause the skew of follow-up chip front side Fanout metallic circuit; Carry out because disk Fanout is encapsulated in encapsulation factory, but carrying out for encapsulation factory the close pitch lines that Fanout technique relates to makes, difficulty is higher, and easily occur the problem that line short, circuit are peeled off, yield is on the low side.
Summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, a kind of novel wafer-level package structure and process thereof are provided, plan design on disk is completely corresponding with the drawing of lead frame, realize the upside-down mounting of full wafer disk in lead frame, carry out cutting and separating and the encapsulation of disk again, realize the wafer-level packaging that single chips size is equal to lead frame single Unit.
The purpose of this utility model is achieved in that a kind of novel wafer-level package structure, it comprises substrate, described substrate front side upside-down mounting has chip, described chip front side is provided with metal salient point, described metal salient point is connected by tin ball with between substrate, be provided with underfill between described chip front side and substrate, described chip back is encapsulated with plastic packaging material, and described substrate back is electroplate with metal level.
Compared with prior art, the utility model has following beneficial effect:
1, chip reroutes to make and is completed by the wafer FAB factory of being good at separately and encapsulation factory respectively with encapsulation, and product yield is higher;
2, lead frame single Unit size is equal to independent chip size, not only make use of die-attach area substantially, and can shorten product sizes, improves the utilance of lead frame, reduces material cost;
3, the upside-down mounting of full wafer disk completes, substantially increases production efficiency, reduces production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of novel wafer-level package structure of the utility model.
Fig. 2 ~ Figure 11 is each operation schematic diagram of a kind of Novel circular of the utility model chip size package structural manufacturing process method.
Wherein:
Substrate 1
Chip 2
Metal salient point 3
Tin ball 4
Underfill 5
Plastic packaging material 6
Metal level 7.
Embodiment
See Fig. 1, a kind of novel wafer-level package structure of the utility model, it comprises substrate 1, described substrate 1 front upside-down mounting has chip 2, described chip 2 front is provided with metal salient point 3, and described metal salient point 3 is connected by tin ball 4 with between substrate 1, is provided with underfill 5 between described chip 2 front and substrate 1, described chip 2 back side is encapsulated with plastic packaging material 6, and described substrate 1 back side is electroplate with metal level 7.
Its process is as follows:
Step one, see Fig. 2, get a disk, disk front line design corresponds to lead frame drawing completely, and single chips size is equal to package dimension;
Step 2, see Fig. 3, disk front electrode makes metal salient point;
Step 3, see Fig. 4, metal salient point makes tin ball;
Step 4, see Fig. 5, disk is by the tin ball upside-down mounting on metal salient point in substrate, and substrate single product size is equal to single chips size;
Step 5, see Fig. 6, the disk and substrate that complete upside-down mounting are put into solder reflow device and carries out Reflow Soldering;
Step 6, see Fig. 7, front cutting is carried out to the product completing Reflow Soldering, is switched to substrate front side, cuts and wear disk;
Step 7, see Fig. 8, inject underfill in the cutting groove completing disk cutting, utilize capillarity to fill clear area between chip and substrate;
Step 8, see Fig. 9, to complete underfill fill after product carry out plastic packaging;
Step 9, see Figure 10, carry out substrate back plating to completing the product after plastic packaging;
Step 10, see Figure 11, the product completing plating to be cut, be separated single product.
Described disk front circuit can carry out Fanout design according to lead frame drawing;
Described lead frame drawing can carry out matched design according to disk front circuit.

Claims (1)

1. a novel wafer-level package structure, it is characterized in that: it comprises substrate (1), described substrate (1) front upside-down mounting has chip (2), described chip (2) front is provided with metal salient point (3), be connected by tin ball (4) between described metal salient point (3) with substrate (1), underfill (5) is provided with between described chip (2) front and substrate (1), described chip (2) back side is encapsulated with plastic packaging material (6), and described substrate (1) back side is electroplate with metal level (7).
CN201420844996.XU 2014-12-26 2014-12-26 A kind of novel wafer-level package structure Active CN204375729U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201420844996.XU CN204375729U (en) 2014-12-26 2014-12-26 A kind of novel wafer-level package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201420844996.XU CN204375729U (en) 2014-12-26 2014-12-26 A kind of novel wafer-level package structure

Publications (1)

Publication Number Publication Date
CN204375729U true CN204375729U (en) 2015-06-03

Family

ID=53331924

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201420844996.XU Active CN204375729U (en) 2014-12-26 2014-12-26 A kind of novel wafer-level package structure

Country Status (1)

Country Link
CN (1) CN204375729U (en)

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