CN104617002A - Semiconductor packaging method and structure - Google Patents
Semiconductor packaging method and structure Download PDFInfo
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- CN104617002A CN104617002A CN201410856800.3A CN201410856800A CN104617002A CN 104617002 A CN104617002 A CN 104617002A CN 201410856800 A CN201410856800 A CN 201410856800A CN 104617002 A CN104617002 A CN 104617002A
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- chip
- metal forming
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- semiconductor chip
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 108
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 74
- 239000000463 material Substances 0.000 claims abstract description 33
- 239000003822 epoxy resin Substances 0.000 claims abstract description 12
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 12
- 239000003292 glue Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 239000011889 copper foil Substances 0.000 claims description 10
- 239000012528 membrane Substances 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 239000004033 plastic Substances 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 239000006071 cream Substances 0.000 claims description 4
- 239000011888 foil Substances 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a semiconductor packaging method and structure. The method comprises the steps of fixing metal foil on a carrying plate; etching a preset circuit on the metal foil; dispensing glue on the metal foil to form a combined material; fixing semiconductor chips on the metal foil through the combined material; electrically connecting pins of semiconductor chips with the metal foil through leads; enabling the semiconductor chips to be injected and molded through epoxy resin; stripping the carrying plate. By means of the method and the structure, the metal foil is used for replacing the lead frame, the semiconductor packaging structure thickness is reduced, the manufacturing cost is reduced, packaged products can be arranged densely, and mass production is facilitated.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of method for packaging semiconductor and structure.
Background technology
Along with the development of semiconductor technology, require that the size of semiconductor device is more and more less.At semiconductor packaging industry, lead frame directly affects packaging cost as an indispensable main material.But because lead frame needs to obtain enough mechanical strengths, so thickness cannot be too thin, the size making semiconductor package be contained in thickness direction is difficult to reduce.The lead frame that thickness is large has brought high manufacturing cost during semiconductor packages.
Summary of the invention
The present invention completes to solve above-mentioned deficiency of the prior art, the object of the invention is to propose a kind of method for packaging semiconductor and structure, can solve when encapsulating in prior art adopts lead frame as carrier, causes the thickness of semiconductor package large and the problem that manufacturing cost is high.
For reaching this object, the present invention by the following technical solutions:
On the one hand, embodiments provide a kind of method for packaging semiconductor, comprise the steps:
Metal forming is fixed on support plate;
Described metal forming etches preinstalled circuit;
Described metal forming puts glue, is formed in conjunction with material;
Semiconductor chip is fixed in described metal forming by described in conjunction with material;
The pin of described semiconductor chip and described metal forming is electrically connected by lead-in wire;
Described semiconductor chip injection mo(u)lding is made with epoxy resin;
Peel off described support plate.
Further, described metal forming is fixed on described support plate by glued membrane.
Further, described metal forming etches preinstalled circuit specifically to comprise:
Described metal forming etches chip carrier and chip pin, and to make described semiconductor chip be positioned on described chip carrier, the pin of described semiconductor chip is electrically connected with described chip pin.
Further, when peeling off described support plate, peel off described glued membrane simultaneously.
Further, described chip carrier and described chip pin is etched according to the type of semiconductor chip; The type of described semiconductor chip comprises positive cartridge chip and flip-chip.
On the other hand, embodiments provide a kind of semiconductor package, comprising:
Metal forming, for loading semiconductor chip, realizing semiconductor chip and being connected with the electrical equipment of outer lead;
Be positioned at above described metal forming in conjunction with material, for semiconductor chip is fixed on described metal forming;
Be positioned at described in conjunction with the semiconductor chip above material;
Lead-in wire, for being electrically connected the pin of described semiconductor chip and described metal forming;
And epoxy resin, for making described semiconductor chip injection mo(u)lding; Described epoxy resin is by described semiconductor chip and go between plastic packaging in described metal forming.
Further, in described metal forming, etching has chip carrier and chip pin; Described semiconductor chip is positioned on described chip carrier, and the pin of described semiconductor chip is electrically connected with described chip pin.
Further, the pattern of described chip carrier and described chip pin is determined by the type of semiconductor chip, and the type of described semiconductor chip comprises positive cartridge chip and flip-chip.
Further, the described material in conjunction with material is elargol or tin cream.
Further, described metal forming is Copper Foil.
Method for packaging semiconductor provided by the invention and structure, replace lead frame by metal forming, reduces the thickness of semiconductor package, reduce manufacturing cost, and make encapsulating products can dense arrangement, is conducive to a large amount of production.
Accompanying drawing explanation
In order to the technical scheme of exemplary embodiment of the present is clearly described, one is done to the accompanying drawing used required for describing in embodiment below and simply introduce.Obviously, the accompanying drawing introduced is the accompanying drawing of a part of embodiment that the present invention will describe, instead of whole accompanying drawings, for those of ordinary skill in the art, under the prerequisite not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the flow chart of the method for packaging semiconductor that the embodiment of the present invention one provides;
Fig. 2 a-Fig. 2 g is the schematic diagram of the semiconductor package process that the embodiment of the present invention one provides;
Fig. 3 is the structural representation of the metal forming that the embodiment of the present invention two provides;
Fig. 4 is the connection diagram of the positive cartridge chip that provides of the embodiment of the present invention two and metal forming;
Fig. 5 is the structural representation of the metal forming that the embodiment of the present invention two provides;
Fig. 6 is the connection diagram of the flip-chip that provides of the embodiment of the present invention two and metal forming.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below with reference to the accompanying drawing in the embodiment of the present invention, by embodiment, technical scheme of the present invention is intactly described.Obviously; described embodiment is a part of embodiment of the present invention, instead of whole embodiments, based on embodiments of the invention; the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making creative work, all falls within protection scope of the present invention.
Embodiment one
Fig. 1 is the flow chart of the method for packaging semiconductor that the embodiment of the present invention one provides.As shown in Figure 1, the method comprises the steps:
Step 101, metal forming to be fixed on support plate.
With reference to figure 2a, first can attach one deck glued membrane on support plate 100, then metal forming 10 is fixed on support plate 100 by glued membrane.Wherein metal forming 10 can be Copper Foil, also can be silver foil, and the present embodiment adopts Copper Foil, this is because the conductivity of Copper Foil is comparatively strong, thermal diffusivity is good and cost is low.
Step 102, in described metal forming, etch preinstalled circuit.
With reference to figure 2b, in the present embodiment, etch chip carrier 20 and chip pin according to the type of semiconductor chip 12, wherein, the type of semiconductor chip 12 comprises positive cartridge chip and flip-chip.The position of the pin of the positive cartridge chip of concrete basis or flip-chip etches chip carrier 20 and the chip pin of correspondence position, forms corresponding circuit pattern.Exemplary, the present embodiment provides the preinstalled circuit in the metal forming under positive cartridge chip, and wherein, chip pin comprises the first pin two 1, second pin two 2 and three-prong 23.
Step 103, put glue on metal foil, formed in conjunction with material.
With reference to figure 2c, metal forming 10 puts glue, formed in conjunction with material 11.Wherein, the material in conjunction with material 11 can be elargol, also can be tin cream, and the present embodiment adopts elargol, this is because the viscosity of elargol is strong, solderability good.
Step 104, by semiconductor chip by fixing on metal foil in conjunction with material.
With reference to figure 2d, by semiconductor chip 12 by conjunction with material 11 fixing on metal foil 10.Concrete, first in metal forming 10, etch chip carrier and chip pin, then in metal forming 10, semiconductor chip 12, in conjunction with material 11, is finally welded in conjunction with on material 11 by preparation, to make semiconductor chip 12 be positioned on chip carrier, the pin of semiconductor chip 12 is electrically connected with chip pin.Wherein, chip pin is at least one, the different pins of the corresponding semiconductor chip 12 of different chip pin.
Step 105, the pin and metal forming that are electrically connected semiconductor chip by going between.
With reference to figure 2e, draw lead-in wire 13 from the pin of semiconductor chip 12, the other end of lead-in wire 13 is connected on corresponding chip pin, is connected with semiconductor chip 12 by chip pin to make external connection electrical apparatus.
Step 106, make semiconductor chip injection mo(u)lding with epoxy resin.
With reference to figure 2f, by injection mold injection moulding epoxy resin 14 in metal forming 10, make epoxy resin 14 in conjunction with material 11, semiconductor chip 12 and 13 plastic packagings will be gone between in metal forming 10.
Step 107, stripping support plate.
With reference to figure 2g, after plastic packaging is shaping, peels off support plate 100, peel off glued membrane simultaneously, complete semiconductor packages.
Method for packaging semiconductor described in the embodiment of the present invention one at least has the following advantages when encapsulating: one is utilize metal forming to instead of lead frame, reduce the thickness of encapsulating structure, and the thermal diffusivity of metal forming is better; Two is semiconductor package compact conformations, can dense arrangement, is conducive to a large amount of production; Three is that metal forming adopts Copper Foil, reduces manufacturing cost; Four is that support plate can be reused, cost-saving.
Embodiment two
The schematic diagram of the semiconductor package that the embodiment of the present invention two provides is with reference to figure 2g.As shown in Figure 2 g, this encapsulating structure comprises:
Metal forming 10, for loading semiconductor chip 12, realizing semiconductor chip 12 and being connected with the electrical equipment of outer lead;
Be positioned at above described metal forming 10 in conjunction with material 11, for semiconductor chip 12 is fixed on metal forming 10;
Be positioned at the semiconductor chip 12 above in conjunction with material 11;
Lead-in wire 13, for being electrically connected pin and the metal forming 10 of semiconductor chip 12;
And epoxy resin 14, for making semiconductor chip 12 injection mo(u)lding; Epoxy resin 14 is by semiconductor chip 12 and go between 13 plastic packagings in metal forming 10.
Wherein, in metal forming 10, etching has chip carrier and chip pin; Semiconductor chip 12 is positioned on chip carrier, and the pin of semiconductor chip 12 is electrically connected with chip pin.And chip pin is at least one, for connecting the different pins of semiconductor chip 12.
Wherein, the material in conjunction with material 11 can be elargol, also can be tin cream, and the present embodiment adopts elargol, this is because the viscosity of elargol is strong, solderability good.Metal forming 10 can be Copper Foil, also can be silver foil, and the present embodiment adopts Copper Foil, this is because the conductivity of Copper Foil is comparatively strong, thermal diffusivity is good and cost is low.
In the present embodiment, the pattern of chip carrier and chip pin is determined by the type of semiconductor chip 12, and the type of semiconductor chip 12 comprises positive cartridge chip and flip-chip.The semiconductor chip 12 of the present embodiment can be formal dress chip, also can be flip-chip.When semiconductor chip 12 is positive cartridge chip, the pattern of chip carrier and chip pin and the structure of metal forming are as shown in Figure 3, exemplary, the present embodiment chips pin comprises the first chip pin 21, second chip pin 22 and the 3rd chip pin 23, wherein, first chip pin 21 and the second chip pin 22 are positioned at the side of chip carrier 20, and are not connected mutually between two between the first chip pin 21, second chip pin 22 and chip carrier 20.3rd chip pin 23 is positioned at the opposite side of chip carrier 20, and the 3rd chip pin 23 is connected with chip carrier 20.
With reference to figure 4, the positive cartridge chip 31 provided for the present embodiment and the connection diagram of metal forming 10.Positive cartridge chip 31 is by being fixed on chip carrier 20 in conjunction with material 30, the grid of positive cartridge chip 31 is connected on the first chip pin 21 by lead-in wire 32, the source electrode of positive cartridge chip 31 is connected on the second chip pin 22 by lead-in wire 32, the drain electrode of positive cartridge chip 31 is connected with chip carrier 20 in conjunction with material 30 by conduction, and then drain electrode is connected on the 3rd chip pin 23.
In the present embodiment, when semiconductor chip 12 is flip-chip, the pattern of chip carrier and chip pin and the structure of metal forming are as shown in Figure 5, exemplary, the present embodiment chips pin comprises the first chip pin 41, second chip pin 42 and the 3rd chip pin 43, wherein, the first chip pin 41 and the second chip pin 42 are positioned at the side of chip carrier 40, and are not connected mutually between two between the first chip pin 41, second chip pin 42 and chip carrier 40.On chip carrier 40, near one jiao of vacancy of the first chip pin 41, and the first chip pin 41 extend in vacancy.3rd chip pin 23 is positioned at the opposite side of chip carrier 20, and the 3rd chip pin 23 is connected with chip carrier 20.
With reference to figure 6, the flip-chip 51 provided for the present embodiment and the connection diagram of metal forming 10.Flip-chip 51 is by being fixed on chip carrier 40 in conjunction with material 50, the grid of flip-chip 51 is connected on the first chip pin 41 by conduction in conjunction with material 50, the source electrode of flip-chip 51 is connected with chip carrier 40 in conjunction with material 50 by conduction, and then making source electrode be connected on the 3rd chip pin 43, the drain electrode of flip-chip 51 52 to be connected on the second chip pin 42 by going between.
In addition, in semiconductor package process, metal forming 10 is fixed on thicker and on the support plate that intensity is higher by glued membrane, with prevent very thin metal foil 10 in encapsulation process because of the stressed distortion that is distorted, cause encapsulation difficulty.After semiconductor injection is shaping, glued membrane and support plate is peeled off, completes semiconductor packages, form semiconductor package.This support plate can continue on for other semiconductor packages.
Semiconductor package described in the embodiment of the present invention two at least has the following advantages when encapsulating: one is utilize metal forming to instead of lead frame, reduce the thickness of encapsulating structure, and the thermal diffusivity of metal forming is better; Two is semiconductor package compact conformations, can dense arrangement, is conducive to a large amount of production; Three is that metal forming adopts Copper Foil, reduces manufacturing cost; Four is that support plate can be reused, cost-saving.
The know-why that above are only preferred embodiment of the present invention and use.The invention is not restricted to specific embodiment described here, the various significant changes can carried out for a person skilled in the art, readjust and substitute all can not depart from protection scope of the present invention.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by the scope of claim.
Claims (10)
1. a method for packaging semiconductor, is characterized in that, comprises the steps:
Metal forming is fixed on support plate;
Described metal forming etches preinstalled circuit;
Described metal forming puts glue, is formed in conjunction with material;
Semiconductor chip is fixed in described metal forming by described in conjunction with material;
The pin of described semiconductor chip and described metal forming is electrically connected by lead-in wire;
Described semiconductor chip injection mo(u)lding is made with epoxy resin;
Peel off described support plate.
2. method for packaging semiconductor according to claim 1, is characterized in that, described metal forming is fixed on described support plate by glued membrane.
3. method for packaging semiconductor according to claim 1, is characterized in that, described metal forming etches preinstalled circuit and specifically comprises:
Described metal forming etches chip carrier and chip pin, and to make described semiconductor chip be positioned on described chip carrier, the pin of described semiconductor chip is electrically connected with described chip pin.
4. method for packaging semiconductor according to claim 2, is characterized in that, when peeling off described support plate, peels off described glued membrane simultaneously.
5. method for packaging semiconductor according to claim 3, is characterized in that, etches described chip carrier and described chip pin according to the type of semiconductor chip; The type of described semiconductor chip comprises positive cartridge chip and flip-chip.
6. a semiconductor package, is characterized in that, comprising:
Metal forming, for loading semiconductor chip, realizing semiconductor chip and being connected with the electrical equipment of outer lead;
Be positioned at above described metal forming in conjunction with material, for semiconductor chip is fixed on described metal forming;
Be positioned at described in conjunction with the semiconductor chip above material;
Lead-in wire, for being electrically connected the pin of described semiconductor chip and described metal forming;
And epoxy resin, for making described semiconductor chip injection mo(u)lding; Described epoxy resin is by described semiconductor chip and go between plastic packaging in described metal forming.
7. semiconductor package according to claim 6, is characterized in that, in described metal forming, etching has chip carrier and chip pin; Described semiconductor chip is positioned on described chip carrier, and the pin of described semiconductor chip is electrically connected with described chip pin.
8. semiconductor package according to claim 7, is characterized in that, the pattern of described chip carrier and described chip pin is determined by the type of semiconductor chip, and the type of described semiconductor chip comprises positive cartridge chip and flip-chip.
9., according to the arbitrary described semiconductor package of claim 6-8, it is characterized in that, the described material in conjunction with material is elargol or tin cream.
10. semiconductor package according to claim 9, is characterized in that, described metal forming is Copper Foil.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410856800.3A CN104617002A (en) | 2014-12-31 | 2014-12-31 | Semiconductor packaging method and structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410856800.3A CN104617002A (en) | 2014-12-31 | 2014-12-31 | Semiconductor packaging method and structure |
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| Publication Number | Publication Date |
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| CN104617002A true CN104617002A (en) | 2015-05-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410856800.3A Pending CN104617002A (en) | 2014-12-31 | 2014-12-31 | Semiconductor packaging method and structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108136736A (en) * | 2015-12-07 | 2018-06-08 | 三井金属矿业株式会社 | The manufacturing method of laminated body and the metal foil of tape tree lipid layer |
| CN112117251A (en) * | 2020-09-07 | 2020-12-22 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and manufacturing method thereof |
| CN112151466A (en) * | 2020-09-07 | 2020-12-29 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and manufacturing method thereof |
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| CN102044510A (en) * | 2009-10-13 | 2011-05-04 | 日月光半导体制造股份有限公司 | Chip packaging body |
| CN103219244A (en) * | 2012-01-18 | 2013-07-24 | 东琳精密股份有限公司 | Substrate process, packaging method, package and system-in-package structure of semiconductor |
| CN103579009A (en) * | 2012-08-02 | 2014-02-12 | 富葵精密组件(深圳)有限公司 | Package substrate, manufacturing method of the package substrate, chip packaging structure and manufacturing method of the chip packaging body |
| US20140085833A1 (en) * | 2012-09-25 | 2014-03-27 | Zhen Ding Technology Co., Ltd. | Chip packaging substrate, method for manufacturing same, and chip packaging structure having same |
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- 2014-12-31 CN CN201410856800.3A patent/CN104617002A/en active Pending
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| CN112117251A (en) * | 2020-09-07 | 2020-12-22 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and manufacturing method thereof |
| CN112151466A (en) * | 2020-09-07 | 2020-12-29 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and manufacturing method thereof |
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Application publication date: 20150513 |