CN102044510A - Chip packaging body - Google Patents
Chip packaging body Download PDFInfo
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- CN102044510A CN102044510A CN 200910175767 CN200910175767A CN102044510A CN 102044510 A CN102044510 A CN 102044510A CN 200910175767 CN200910175767 CN 200910175767 CN 200910175767 A CN200910175767 A CN 200910175767A CN 102044510 A CN102044510 A CN 102044510A
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- paper tinsel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
The invention provides a chip packaging body which comprises a patterning metal foil layer, a chip, a plurality of leads, a patterning dielectric layer, an adhering layer and a packaging colloid, wherein the patterning metal foil layer is provided with a first surface and a second surface which are opposite; the patterning dielectric layer is configured on the second surface of the patterning metal foil layer and provided with a plurality of openings for exposing at least part of patterning metal foil layer and also provided with a plurality of joints electrically connected with the outside; the chip is configured on the first surface; the adhering layer is configured between the chip and the patterning metal foil layer; the leads are respectively connected with the chip and the patterning metal foil layer; the patterning dielectric layer is positioned below the joint of the lead and the patterning metal foil layer, the patterning dielectric layer and the lead and the patterning metal foil layer are overlapped on a plane; and the packaging colloid is configured on the first surface and covers the chip and the leads.
Description
Technical field
The present invention relates to a kind of packaging body, and particularly relevant for a kind of chip packing-body.
Background technology
Semi-conductor industry is one of fastest high-technology industry of development in recent years, and along with making rapid progress of electronic technology, coming out one after another of high-tech electronic industry makes electronic product more humane, with better function constantly weed out the old and bring forth the new.
At present, in the middle of manufacture of semiconductor,, often protect semiconductor chip in the mode of encapsulation because semiconductor chip is quite accurate.The method of Chip Packaging be earlier with a chip configuration on a carrier, routing connects chip and carrier then, forms the packing colloid of a coating chip and lead afterwards again on carrier, to form a chip packing-body.
The major function of chip packing-body comprises: (1) provides chip a plurality of current paths that are electrically connected to exterior electrical components; (2) a plurality of highdensity contact of chip can be electrically connected to a plurality of low-density contacts of carrier respectively, and electrically connects by these low-density contacts and exterior electrical components; (3) heat energy that chip is produced is dissipated into the external world; (4) the protection chip avoids being subjected to the pollution of external environment.
Summary of the invention
The invention provides a kind of chip packing-body, its pattern metal paper tinsel layer (metal foil) is carries chips firmly.
The present invention proposes a kind of chip packing-body, comprises a pattern metal paper tinsel layer, one first pattern dielectric layer, a chip, an adhesion coating, many leads and a packing colloid.Pattern metal paper tinsel layer has a relative first surface and a second surface.First pattern dielectric layer is disposed on the second surface of pattern metal paper tinsel layer, and wherein first pattern dielectric layer has a plurality of first openings exposing partially patterned at least metal foil layer, and forms a plurality of second contacts that the below externally electrically connects.Chip configuration is on the first surface of pattern metal paper tinsel layer.Adhesion coating is disposed between chip and the pattern metal paper tinsel layer.Lead connects chip and pattern metal paper tinsel layer respectively, and wherein part first pattern dielectric layer is positioned at the below of lead and pattern metal paper tinsel layer joint, and part first pattern dielectric layer and lead and pattern metal paper tinsel layer are for being overlapped in a plane.Packing colloid is disposed on the first surface, and covers chip and lead.
The present invention proposes a kind of chip packing-body, comprises a pattern metal paper tinsel layer, one first pattern dielectric layer, a chip, an adhesion coating, many leads and a packing colloid.Pattern metal paper tinsel layer has a relative first surface and a second surface, and pattern metal paper tinsel layer comprises a chip carrier and a plurality of pin, and pin configuration is in the periphery of chip carrier.First pattern dielectric layer is disposed on the second surface of pattern metal paper tinsel layer, wherein first pattern dielectric layer has a plurality of first openings to expose partially patterned at least metal foil layer, and form a plurality of second contacts that the below externally electrically connects, and part first opening is positioned under the chip carrier and exposes chip carrier.Chip configuration and is positioned on the chip carrier on the first surface of pattern metal paper tinsel layer.Adhesion coating is disposed between chip and the pattern metal paper tinsel layer.Lead connects chip and pattern metal paper tinsel layer respectively, and is connected with pin to the small part lead.Packing colloid is disposed on the first surface, and covers chip and lead.
The present invention proposes a kind of chip packing-body, comprises a pattern metal paper tinsel layer, a pattern dielectric layer, a chip, a plurality of conductive projection and a packing colloid.Pattern metal paper tinsel layer has a relative first surface and a second surface.Pattern dielectric layer is disposed on the second surface of pattern metal paper tinsel layer, and wherein pattern dielectric layer has a plurality of openings exposing partially patterned at least metal foil layer, and forms a plurality of contacts that the below externally electrically connects.Chip configuration is on first surface.Conductive projection is disposed between chip and the pattern metal paper tinsel layer.Packing colloid is disposed on the first surface, and covers chip and conductive projection.
Based on above-mentioned, because the loading plate that pattern metal paper tinsel layer of the present invention and pattern dielectric layer are constituted is carries chips firmly, and loading plate is quite thin, thus can reduce the integral thickness of chip packing-body, and help to make chip packing-body to develop towards light, thin direction.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 to Fig. 4 and Fig. 6 to Figure 10 are respectively the profile of the chip packing-body of a plurality of embodiment of the present invention;
Fig. 5 A is the profile of the chip packing-body of one embodiment of the invention;
Fig. 5 B is the upward view of the chip packing-body of Fig. 5 A;
Figure 11 is the upward view of the chip packing-body of Figure 10;
Figure 12 is the profile of the chip packing-body of another embodiment of the present invention;
Figure 13 is the upward view of the chip packing-body of Figure 12;
Figure 14 is the profile of the chip packing-body of another embodiment of the present invention;
Figure 15 is the upward view of the chip packing-body of Figure 14.
Main element symbol description in the accompanying drawing:
100、100A、100B、100C、100D、100E、100F、100G、100H、100I、200、
The 200A-chip packing-body;
110,110I, 210-pattern metal paper tinsel layer; 112,212-first surface;
114,214-second surface; The 116-chip carrier;
118,118I, 118J, 118K, 218-pin; 120,220-chip;
130,130I, 130J-lead;
140、140A、140B、140C、140D、140E、140G、140H、140I、190、240、
The 240A-pattern dielectric layer;
142,142A, 142C, 142D, 142E, 142H, 142I, 192,242,242A-opening;
150,250-packing colloid; The 160-adhesion coating;
170,170A, 270-surface-treated layer; 180,280-soldered ball;
The 218A-bearing end; The 218B-epitaxial end;
The 230-conductive projection; The 260-primer;
A1, A2-routing portion; The B-zone;
The part that is connected of C-conductive projection and pin; D-lead and the pattern metal paper tinsel layer part of joining;
The E-contact; E1-first contact;
E2-second contact; T, T1-gross thickness.
Embodiment
Fig. 1 to Fig. 4 and Fig. 6 to Figure 10 are respectively the profile of the chip packing-body of a plurality of embodiment of the present invention.Fig. 5 A is the profile of the chip packing-body of one embodiment of the invention, and Fig. 5 B is the upward view of the chip packing-body of Fig. 5 A.Figure 11 is the upward view of the chip packing-body of Figure 10.
Please refer to Fig. 1, the chip packing-body 100 of present embodiment comprises a pattern metal paper tinsel layer 110, a chip 120, many leads 130, a pattern dielectric layer 140, a packing colloid 150 and adhesion coatings 160.The chip packing-body 100 of present embodiment can be a square flat non-pin packaging body.
Pattern metal paper tinsel layer 110 has a relative first surface 112 and a second surface 114.In the present embodiment, pattern metal paper tinsel layer 110 comprises a chip carrier 116 and a plurality of pins 118, and wherein chip carrier 116 is a continuous conducting layers.Chip 120 is disposed on the chip carrier 116 and is positioned on the first surface 112, and pin 118 is disposed at the periphery of chip carrier 116.The material of pattern metal paper tinsel layer 110 comprises copper or the good material of other conduction properties, and pattern metal paper tinsel layer 110 can have connection pad (dummy pad) (not shown) of at least one no signal and plain conductor (dummytrace) (not shown) of at least one no signal.
Pattern dielectric layer 140 is disposed on the second surface 114 and has a plurality of openings 142, and opening 142 exposes part second surface 114 and forms a plurality of second contact E2 that externally electrically connect.In the present embodiment, the scope of the gross thickness T of pattern dielectric layer 140 and pattern metal paper tinsel layer 110 is between 40 microns～130 microns.In the present embodiment, pattern dielectric layer 140 can constitute a loading plate with pattern metal paper tinsel layer 110.
In the present embodiment, for avoiding the second contact E2 to be subjected to external environmental or oxidation, can form a surface-treated layer 170 on the second contact E2, the material of surface-treated layer 170 comprises nickel/gold, changes NiPdAu, silver, tin and alloy, tin cream or organic compound.Packing colloid 150 is configurable on first surface 112, and covers chip 120, lead 130, pattern metal paper tinsel layer 110 and pattern dielectric layer 140.
It should be noted that, because the loading plate that the pattern metal paper tinsel layer 110 and the pattern dielectric layer 140 of present embodiment are constituted is carries chips 120 firmly, and loading plate is quite thin, so can reduce the integral thickness of chip packing-body 100, and help to make chip packing-body 100 to develop towards light, thin direction.Moreover the pattern metal paper tinsel layer 110 of present embodiment is also quite thin, so can reduce cost of manufacture.
Please refer to Fig. 2, the structural similarity of the chip packing-body 100A of present embodiment is in the structure of the chip packing-body 100 of Fig. 1, and both difference parts are that some opening 142A of the pattern dielectric layer 140A of present embodiment are positioned at chip 120 belows and expose chip carrier 116.Opening 142A can be positioned at chip carrier 116 under.In the present embodiment, can on the second contact E2 that opening 142A is exposed and chip carrier 116, form a surface-treated layer 170A.
Thus, the heat that chip 120 is produced in running can be transmitted to chip carrier 116, is transmitted to the external environment from the opening 142A that exposes chip carrier 116 again.In addition, when some leads 130 are connected between chip carrier 116 and the chip 120, chip 120 can be electrically connected to chip carrier 116, is electrically connected to other electronic component (for example wiring board) again via the part that is exposed by opening 142A of chip carrier 116.
Please refer to Fig. 3, the structural similarity of the chip packing-body 100B of present embodiment is in the structure of the chip packing-body 100 of Fig. 1, and both difference parts are that the partially patterned dielectric layer 140B of present embodiment is positioned at the join below of part D of lead 130 and pattern metal paper tinsel layer 110.In other words, pattern metal paper tinsel layer 110, lead 130 can be overlapped in a plane with pattern dielectric layer 140B.Thus, pattern dielectric layer 140B can support the part that is subjected to the routing surge of pattern metal paper tinsel layer 110, so that the yield that pattern metal paper tinsel layer 110 is unlikely to produce excessive distortion and improves the routing processing procedure.In addition, in the present embodiment, two leads 130 are connected on the same pin 118.
Please refer to Fig. 4, the structural similarity of the chip packing-body 100C of present embodiment is in the structure of the chip packing-body 100B of Fig. 3, and both difference parts are that some opening 142C of the pattern dielectric layer 140C of present embodiment are positioned at chip 120 belows and expose chip carrier 116.
Please be simultaneously with reference to Fig. 5 A and Fig. 5 B, the structural similarity of the chip packing-body 100D of present embodiment is in the structure of the chip packing-body 100B of Fig. 3, both difference parts are that a plurality of opening 142D of the pattern dielectric layer 140D of present embodiment are positioned at the outer rim of pattern metal paper tinsel layer 110, and these openings 142D is a plurality of perforates.
Please refer to Fig. 6, the structural similarity of the chip packing-body 100E of present embodiment is in the structure of the chip packing-body 100D of Fig. 5, and both difference parts are that some opening 142E of the pattern dielectric layer 140E of present embodiment are positioned at chip 120 belows and expose chip carrier 116.
Please refer to Fig. 7, the structural similarity of the chip packing-body 100F of present embodiment is in the structure of the chip packing-body 100 of Fig. 1, and both difference parts are that the chip packing-body 100F of present embodiment also comprises a pattern dielectric layer 190.Pattern dielectric layer 190 is disposed on the first surface 112 of pattern metal paper tinsel layer 110, and runs through pattern metal paper tinsel layer 110 and link to each other with pattern dielectric layer 140.In the present embodiment, the scope of the gross thickness T1 of pattern dielectric layer 190,140 and pattern metal paper tinsel layer 110 is between 40 microns～130 microns.
Pattern dielectric layer 190 has a plurality of openings 192, and opening 192 exposes part first surface 112, to form a plurality of first contact E1 that the top externally electrically connects.In the present embodiment, pattern dielectric layer 190 cover part chip carriers 116, and the material of pattern dielectric layer 190 be anti-welding green lacquer (solder mask, SM), liquid crystal polymer (liquid crystal polyester, LCP) or polypropylene (polypropylene, PP).Lead 130 is connected to pattern metal paper tinsel layer 110 by chip 120 through opening 192.In other embodiments, the part opening (not shown) of pattern dielectric layer 140 can be positioned under the chip carrier 116 and expose chip carrier 116.
Please refer to Fig. 8, the structural similarity of the chip packing-body 100G of present embodiment is in the structure of the chip packing-body 100F of Fig. 7, and both difference parts are that the partially patterned dielectric layer 140G of present embodiment is positioned at opening 192 belows.Thus, pattern dielectric layer 140G can support the part that pattern metal paper tinsel layer 110 is subjected to the routing surge, so that the yield that pattern metal paper tinsel layer 110 is unlikely to produce excessive distortion and improves the routing processing procedure.
In addition, in the present embodiment, pattern dielectric layer 190 can have a plurality of openings 192, and these openings 192 wherein two can expose same pin 118, and optionally make two leads 130 be connected to same pin 118 by aforementioned two openings 192 respectively.
Please refer to Fig. 9, the structural similarity of the chip packing-body 100H of present embodiment is in the structure of the chip packing-body 100G of Fig. 8, and both difference parts are that the opening 142H of the partially patterned dielectric layer 140H of present embodiment is positioned at the outer rim of pattern metal paper tinsel layer 110.
Please be simultaneously with reference to Figure 10 and Figure 11, the structural similarity of the chip packing-body 100I of present embodiment is in the structure of the chip packing-body 100 of Fig. 1, both difference parts are that the pattern metal paper tinsel layer 110I of present embodiment has a plurality of pin 118I, and chip 120 is disposed on the pin 118I.It should be noted that in Figure 11 area B is the zone that representative is positioned at chip 120 belows.
In the present embodiment, pin 118I comprises the pin 118J of inside expansion (fan in), and pin 118J is extended to the below of chip 120 by the periphery of chip 120.Specifically, chip 120 is disposed on the pin 118J, and lead 130I connects the A1 of routing portion of chip 120 and pin 118J, and wherein the opening 142I of the below that is positioned at chip 120 of pattern dielectric layer 140I (being area B) can expose the part of the carries chips 120 of pin 118J.In other words, present embodiment can be by the position of the opening 142I of the configuration mode of adjusting pin 118J and pattern dielectric layer 140I, and the contact that makes the external electric connection of chip packing-body 100I is positioned at chip 120 belows, with configurable area that increases aforementioned contact and the density that reduces aforementioned contact.
In addition, in the present embodiment, pin 118I also can comprise the pin 118K of outside expansion (fan out), and pin 118K extends towards the direction away from chip 120.Specifically, lead 130J connects the A2 of routing portion of chip 120 and pin 118K, and the opening 142I that is positioned at chip 120 peripheries of pattern dielectric layer 140I can expose pin 118K.In other words, the position of configuration mode that present embodiment can be by adjusting pin 118K and the opening 142I of pattern dielectric layer 140I, and make the contact of the external electric connection of chip packing-body 100I be positioned at chip 120 peripheries.
In addition, in the present embodiment, optionally in a plurality of opening 142I of pattern dielectric layer 140I, dispose a plurality of soldered balls 180 respectively, and soldered ball 180 and pin 118I are electrically connected.Soldered ball 180 can be soldered ball (dummy ball) (not shown) of a no signal.
Figure 12 is the profile of the chip packing-body of another embodiment of the present invention.Figure 13 is the upward view of the chip packing-body of Figure 12.Figure 14 is the profile of the chip packing-body of another embodiment of the present invention.Figure 15 is the upward view of the chip packing-body of Figure 14.
Please be simultaneously with reference to Figure 12 and Figure 13, the chip packing-body 200 of present embodiment comprises a pattern metal paper tinsel layer 210, a chip 220, a plurality of conductive projection 230, a pattern dielectric layer 240 and a packing colloid 250.Pattern metal paper tinsel layer 210 has a relative first surface 212 and a second surface 214.Chip 220 is disposed on the first surface 212.In the present embodiment, pattern metal paper tinsel layer 210 comprises a plurality of pins 218, and pin 218 has the bearing end 218A and of a carries chips 220 towards the epitaxial end 218B that extends away from the direction of chip 220.
In the present embodiment, can on contact E, form a surface-treated layer 270.In addition, in the present embodiment, a plurality of soldered balls 280 can be configured in respectively in a plurality of openings 242 of pattern dielectric layer 240, and make soldered ball 280 be electrically connected to pattern metal paper tinsel layer 210.
Please be simultaneously with reference to Figure 14 and Figure 15, the structural similarity of the chip packing-body 200A of present embodiment is in the structure of the chip packing-body 200 of Figure 12, and both difference parts are that a plurality of opening 242A of the pattern dielectric layer 240A of present embodiment all are positioned at the periphery of chip 220.In other words, all opening 242A of pattern dielectric layer 240A all are positioned at the periphery of the lower zone B of chip 220.
In the present embodiment, a plurality of pins 218 of chip packing-body 200A are all the pin of outside expansion (fanout), so that the contact that externally electrically connects of chip packing-body 200A all is positioned at chip 220 peripheries.As shown in figure 15, the lower zone B that part C all is arranged in chip 220 that is connected of conductive projection 230 and pin 218, and pin 218 extends to the direction away from chip 220, and opening 242A exposes the end away from chip 220 of pin 218.
In sum, because the loading plate that pattern metal paper tinsel layer of the present invention and pattern dielectric layer are constituted is carries chips firmly, and loading plate is quite thin, thus can reduce the integral thickness of chip packing-body, and help to make chip packing-body to develop towards light, thin direction.Moreover pattern metal paper tinsel layer of the present invention is also quite thin, so can reduce cost of manufacture.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (18)
1. chip packing-body comprises:
One pattern metal paper tinsel layer has a relative first surface and a second surface;
One first pattern dielectric layer, be disposed on this second surface of this pattern metal paper tinsel layer, wherein this first pattern dielectric layer has a plurality of first openings exposing to this pattern metal paper tinsel layer of small part, and forms a plurality of second contacts that the below externally electrically connects;
One chip is disposed on this first surface of this pattern metal paper tinsel layer;
One adhesion coating is disposed between this chip and this pattern metal paper tinsel layer;
Many leads, connect this chip and this pattern metal paper tinsel layer respectively, wherein this first pattern dielectric layer of part is positioned at the join below of part of described lead and this pattern metal paper tinsel layer, and partly this first pattern dielectric layer and described lead and this pattern metal paper tinsel layer for being overlapped in a plane; And
One packing colloid is disposed on this first surface, and covers this chip and described lead.
2. chip packing-body according to claim 1 also comprises:
One second pattern dielectric layer is disposed at this pattern metal paper tinsel layer top, and wherein these second patterned dielectric series of strata expose this pattern metal paper tinsel layer of part at least, to form a plurality of first contacts that the top externally electrically connects.
3. chip packing-body according to claim 2, wherein the total thickness of this pattern metal paper tinsel layer, this first pattern dielectric layer and this second pattern dielectric layer is between 40 microns～130 microns.
4. chip packing-body according to claim 1, wherein this pattern metal paper tinsel layer comprises:
A plurality of pins, at least one of them extends to this chip below to described pin, and one of them connects this chip and described pin to described lead at least, and one of them is positioned at this chip below to described first opening at least, to expose the part that extends to this chip below of described pin.
5. chip packing-body according to claim 1, wherein this pattern metal paper tinsel layer comprises:
A plurality of pins, described pin at least one of them to extending away from the direction of this chip, described lead at least one of them connect this chip and described pin one of them, and described first opening one of them is positioned at this chip periphery and exposes described pin at least.
6. chip packing-body according to claim 1, wherein described first opening of part is positioned at the outer rim of this pattern metal paper tinsel layer, and described first opening is a plurality of perforates.
7. chip packing-body comprises:
One pattern metal paper tinsel layer has a relative first surface and a second surface, and this pattern metal paper tinsel layer comprises:
One chip carrier;
A plurality of pins are disposed at the periphery of this chip carrier;
One first pattern dielectric layer, be disposed on this second surface of this pattern metal paper tinsel layer, wherein this first pattern dielectric layer has a plurality of first openings to expose to this pattern metal paper tinsel layer of small part, and form a plurality of second contacts that the below externally electrically connects, and described first opening of part is positioned under this chip carrier and exposes this chip carrier;
One chip is disposed on this first surface of this pattern metal paper tinsel layer, and is positioned on this chip carrier;
One adhesion coating is disposed between this chip and this pattern metal paper tinsel layer;
Many leads connect this chip and this pattern metal paper tinsel layer respectively, and are connected with described pin to the described lead of small part; And
One packing colloid is disposed on this first surface, and covers this chip and described lead.
8. chip packing-body according to claim 7, wherein this chip carrier is a continuous conducting layers.
9. chip packing-body according to claim 7 also comprises:
One surface-treated layer covers the surface and the sidewall of this chip carrier and described second contact at least.
10. chip packing-body according to claim 9, the material of this surface-treated layer comprise nickel/gold, change NiPdAu, silver, tin and alloy, tin cream or organic compound.
11. chip packing-body according to claim 7 also comprises:
One second pattern dielectric layer is disposed at this pattern metal paper tinsel layer top, and wherein these second patterned dielectric series of strata expose this pattern metal paper tinsel layer of part at least, to form a plurality of first contacts that the top externally electrically connects.
12. chip packing-body according to claim 11, wherein this chip carrier is covered by this second pattern dielectric layer of part.
13. chip packing-body according to claim 7, wherein this chip carrier is a continuous conducting layers.
14. chip packing-body according to claim 7, wherein those first openings of part are positioned at the outer rim of this pattern metal paper tinsel layer, and those first openings are a plurality of perforates.
15. a chip packing-body comprises:
One pattern metal paper tinsel layer has a relative first surface and a second surface;
One pattern dielectric layer is disposed on this second surface of this pattern metal paper tinsel layer, and wherein this pattern dielectric layer has a plurality of openings exposing to this pattern metal paper tinsel layer of small part, and forms a plurality of contacts that the below externally electrically connects;
One chip is disposed on this first surface;
A plurality of conductive projections are disposed between this chip and this pattern metal paper tinsel layer; And
One packing colloid is disposed on this first surface, and covers this chip and described conductive projection.
16. chip packing-body according to claim 15, wherein this pattern metal paper tinsel layer comprises:
A plurality of pins, respectively this pin have a carries chips bearing end and towards the epitaxial end that extends away from the direction of chip, and described opening exposes the epitaxial end of described pin respectively and is positioned at the periphery of this chip.
17. chip packing-body according to claim 15, wherein the described opening of part is positioned at this chip below.
18. chip packing-body according to claim 15, wherein said conductive projection comprise copper post, copper bump or golden projection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910175767 CN102044510A (en) | 2009-10-13 | 2009-10-13 | Chip packaging body |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910175767 CN102044510A (en) | 2009-10-13 | 2009-10-13 | Chip packaging body |
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| CN102044510A true CN102044510A (en) | 2011-05-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200910175767 Pending CN102044510A (en) | 2009-10-13 | 2009-10-13 | Chip packaging body |
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| CN (1) | CN102044510A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102064144A (en) * | 2010-11-10 | 2011-05-18 | 日月光半导体制造股份有限公司 | Quad flat non-lead package and manufacturing method thereof |
| US8502363B2 (en) | 2011-07-06 | 2013-08-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with solder joint enhancement element and related methods |
| US8531017B2 (en) | 2010-09-14 | 2013-09-10 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages having increased input/output capacity and related methods |
| US8592962B2 (en) | 2010-10-29 | 2013-11-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with protective layer and related methods |
| US8674487B2 (en) | 2012-03-15 | 2014-03-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with lead extensions and related methods |
| CN104617002A (en) * | 2014-12-31 | 2015-05-13 | 杰群电子科技（东莞）有限公司 | Semiconductor packaging method and structure |
| US9059379B2 (en) | 2012-10-29 | 2015-06-16 | Advanced Semiconductor Engineering, Inc. | Light-emitting semiconductor packages and related methods |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8531017B2 (en) | 2010-09-14 | 2013-09-10 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages having increased input/output capacity and related methods |
| US8592962B2 (en) | 2010-10-29 | 2013-11-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with protective layer and related methods |
| CN102064144A (en) * | 2010-11-10 | 2011-05-18 | 日月光半导体制造股份有限公司 | Quad flat non-lead package and manufacturing method thereof |
| US8502363B2 (en) | 2011-07-06 | 2013-08-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with solder joint enhancement element and related methods |
| US8994156B2 (en) | 2011-07-06 | 2015-03-31 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with solder joint enhancement elements |
| US8674487B2 (en) | 2012-03-15 | 2014-03-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with lead extensions and related methods |
| US9653656B2 (en) | 2012-03-16 | 2017-05-16 | Advanced Semiconductor Engineering, Inc. | LED packages and related methods |
| US10177283B2 (en) | 2012-03-16 | 2019-01-08 | Advanced Semiconductor Engineering, Inc. | LED packages and related methods |
| US9059379B2 (en) | 2012-10-29 | 2015-06-16 | Advanced Semiconductor Engineering, Inc. | Light-emitting semiconductor packages and related methods |
| CN104617002A (en) * | 2014-12-31 | 2015-05-13 | 杰群电子科技（东莞）有限公司 | Semiconductor packaging method and structure |
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