CN106373935B - A kind of island-free framework encapsulation technique and its encapsulating structure - Google Patents

A kind of island-free framework encapsulation technique and its encapsulating structure Download PDF

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Publication number
CN106373935B
CN106373935B CN201610914057.1A CN201610914057A CN106373935B CN 106373935 B CN106373935 B CN 106373935B CN 201610914057 A CN201610914057 A CN 201610914057A CN 106373935 B CN106373935 B CN 106373935B
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China
Prior art keywords
island
frame
cured film
free
chip
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CN201610914057.1A
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Chinese (zh)
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CN106373935A (en
Inventor
殷炯
王强
龚臻
刘怡
章春燕
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to CN201610914057.1A priority Critical patent/CN106373935B/en
Publication of CN106373935A publication Critical patent/CN106373935A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)

Abstract

The present invention relates to a kind of island-free framework encapsulation technique and its encapsulating structures, the structure includes island-free frame (1), island-free frame (1) front is covered with cured film (2), chip (3) are provided on the cured film (2), the chip (3) is electrically connected with island-free frame (1) by being electrically connected component (4), the island-free frame (1), cured film (2), electric connection component (4) are encapsulated with plastic packaging material (5) outside, and island-free frame (1) back side is exposed to plastic packaging material (5).A kind of island-free framework encapsulation technique of the present invention and its encapsulating structure, it pastes the chip supporting structure that Ji Dao effect is formed after cured film solidifies on island-free frame, can effectively solve the problem that chip and pins contact area are too small leads to the problem of chip lifts when the shaking of routing shakiness or routing, while also can be avoided pre-packaged frame two sides copper face product proportional difference frame warpage issues caused greatly.

Description

A kind of island-free framework encapsulation technique and its encapsulating structure
Technical field
The present invention relates to a kind of island-free framework encapsulation technique and its encapsulating structures, belong to technical field of semiconductor encapsulation.
Background technique
The lead frame island-free product formed at present by etching, when chip load are framves on pin.In fact, When chip carrier is on pin, since chip and pins contact area are too small, routing shakiness is caused to be shaken or chip stress when routing The abnormal phenomenon lifted on one side.
Although the pre-packaged frame of island-free can achieve the purpose that support chip by pre-fill plastic packaging material, island-free is pre- Frame is encapsulated since copper face product proportional difference in frame two sides is big, frame warpage issues can be generated, and load glue can be in plastic packaging material Upper diffusion stains onto frame pin, influences product yield and reliability.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of island-free framework encapsulation technique for the above-mentioned prior art And its encapsulating structure, it pastes the chip supporting structure that Ji Dao effect is formed after cured film solidifies, Neng Gouyou on island-free frame Effect, which solves the problems, such as that chip and pins contact area are too small, causes chip-side when the shaking of routing shakiness or routing to lift, while Frame warpage issues caused by can be avoided pre-packaged frame two sides copper face product proportional difference greatly.
The present invention solves the above problems used technical solution are as follows: a kind of island-free framework encapsulation technique, the technique Include the following steps:
Step 1: by cured film setting on conversion film;
Step 2: conversion film is provided on the interior pin for being attached to island-free frame on one side of cured film;
Step 3: cured film is solidified, cured film completes removal conversion film after solidification;
Step 4: chip is arranged in cured film;
Step 5: being electrically connected chip and island-free frame with electrical connecting component;
Step 6: encapsulating, with plastic packaging material cladding frame, cured film, chip, is electrically connected component.
The cured film is FOW film or FOD film.
The electric connection component is bonding wire.
A kind of island-free framework encapsulation structure, it includes island-free frame, and island-free frame front is covered with solidification Film is provided with chip in the cured film, and the chip is electrically connected with island-free frame by being electrically connected component, institute It states island-free frame, cured film, electric connection component and is encapsulated with plastic packaging material outside, the island-free frame back side is exposed to plastic packaging Material.
Compared with the prior art, the advantages of the present invention are as follows:
1, the chip supporting structure that Ji Dao effect is formed after cured film solidifies is pasted on island-free frame, it being capable of reinforced frame Enabling capabilities, can effectively solve the problem that chip and pins contact are too small causes routing shakiness to be shaken or chip-side lifts when routing The problem of, the stability and product yield of chip when improving routing;
2, compared with pre-packaged technology: (1) can be to avoid the warpage issues of frame;(2) can exist to avoid chip load glue Diffusion on plastic packaging material (it is fine that load glue spreads control effect on such film).
Detailed description of the invention
Fig. 1 is a kind of schematic diagram of island-free framework encapsulation structure of the present invention.
Fig. 2 ~ Fig. 7 is a kind of each process flow chart of island-free framework encapsulation technique of the present invention.
Wherein:
Island-free frame 1
Cured film 2
Chip 3
It is electrically connected component 4
Plastic packaging material 5.
Specific embodiment
The present invention will be described in further detail below with reference to the embodiments of the drawings.
As shown in Figure 1, one of the present embodiment island-free framework encapsulation structure, it includes island-free frame 1, the nothing Frame 1 front in base island is covered with cured film 2, and chip 3 is provided in the cured film 2, and the chip 3 and island-free frame 1 are logical It crosses electric connection component 4 to be electrically connected, the island-free frame 1, cured film 2, electric connection component 4 are encapsulated with modeling outside Envelope material 5,1 back side of island-free frame is exposed to plastic packaging material 5.
Its process is as follows:
Step 1: referring to fig. 2, by cured film setting on conversion film, needed for being dimensioned to according to island-free frame Size, cured film can be FOW film or FOD film etc.;
The characteristic of above-mentioned cured film: this film has half mobility before curing, is mounted on by conversion pad pasting, alignment method The frame back side will not be flowed to when on hollow out frame from frame gap and stains shape;When passing through heating, film is turned by half flow regime Become solid-state, the frame back side will not be flowed to from frame gap in the process, after this film is converted to solid-state, at normal temperature or again Secondary heating will not revert to half flow regime;
Step 2: conversion film is provided on the interior pin for being attached to island-free frame on one side of cured film, is made referring to Fig. 3 Cured film is attached on the interior pin of island-free frame;
Step 3: referring to fig. 4, cured film is solidified, cured film completes removal conversion film after solidification;
Step 4: carrying out positive cartridge chip by load glue in cured film referring to Fig. 5;
Step 5: being electrically connected component referring to Fig. 6 and being electrically connected chip and island-free frame, being electrically connected component is weldering Line;
Step 6: referring to Fig. 7, encapsulating with plastic packaging material cladding frame, cured film, chip, is electrically connected component, and nothing The base island frame back side is exposed to plastic packaging material.
In addition to the implementation, all to use equivalent transformation or equivalent replacement the invention also includes there is an other embodiments The technical solution that mode is formed should all be fallen within the scope of the hereto appended claims.

Claims (3)

1. a kind of island-free framework encapsulation technique, it is characterised in that the technique includes the following steps:
Step 1: by cured film setting on conversion film;The cured film has half mobility before curing, passes through converting paster Film, alignment method will not flow to the frame back side from frame gap and stain shape when being mounted on hollow out frame;When passing through heating, The cured film is changed into solid-state by half flow regime, will not flow to the frame back side from frame gap in the process, described After cured film is converted to solid-state, half flow regime will not be reverted to by heating at normal temperature or again;
Step 2: conversion film is provided on the interior pin for being attached to island-free frame on one side of cured film;The two of the cured film End is mounted on respectively on the interior pin of adjacent island-free frame;
Step 3: cured film is solidified, cured film completes removal conversion film after solidification;
Step 4: chip is arranged in cured film;
Step 5: being electrically connected component is electrically connected chip and island-free frame;
Step 6: encapsulating, with plastic packaging material cladding frame, cured film, chip and is electrically connected component.
2. a kind of island-free framework encapsulation technique according to claim 1, it is characterised in that: the cured film is FOW film Or FOD film.
3. a kind of island-free framework encapsulation technique according to claim 1, it is characterised in that: the electric connection component is Bonding wire.
CN201610914057.1A 2016-10-20 2016-10-20 A kind of island-free framework encapsulation technique and its encapsulating structure Active CN106373935B (en)

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Publication number Priority date Publication date Assignee Title
CN108171299A (en) * 2017-12-19 2018-06-15 中电智能卡有限责任公司 A kind of processing technology of smart card
CN108493169A (en) * 2018-05-31 2018-09-04 江苏长电科技股份有限公司 Packaging structure without base island frame and process method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7633144B1 (en) * 2006-05-24 2009-12-15 Amkor Technology, Inc. Semiconductor package
CN201752004U (en) * 2010-04-30 2011-02-23 江苏长电科技股份有限公司 Packaging structure for arranging chip directly
CN103390564A (en) * 2012-05-08 2013-11-13 Nxp股份有限公司 Film based IC packaging method and packaged IC device
CN104505380A (en) * 2014-12-19 2015-04-08 日月光封装测试(上海)有限公司 Semiconductor packaging body and manufacturing method thereof
CN205039143U (en) * 2015-08-20 2016-02-17 南昌欧菲生物识别技术有限公司 Electron device and electronic equipment
CN206250189U (en) * 2016-10-20 2017-06-13 江苏长电科技股份有限公司 A kind of island-free framework encapsulation structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001320007A (en) * 2000-05-09 2001-11-16 Dainippon Printing Co Ltd Frame for resin sealed semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7633144B1 (en) * 2006-05-24 2009-12-15 Amkor Technology, Inc. Semiconductor package
CN201752004U (en) * 2010-04-30 2011-02-23 江苏长电科技股份有限公司 Packaging structure for arranging chip directly
CN103390564A (en) * 2012-05-08 2013-11-13 Nxp股份有限公司 Film based IC packaging method and packaged IC device
CN104505380A (en) * 2014-12-19 2015-04-08 日月光封装测试(上海)有限公司 Semiconductor packaging body and manufacturing method thereof
CN205039143U (en) * 2015-08-20 2016-02-17 南昌欧菲生物识别技术有限公司 Electron device and electronic equipment
CN206250189U (en) * 2016-10-20 2017-06-13 江苏长电科技股份有限公司 A kind of island-free framework encapsulation structure

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