CN106373935A - Paddle-free frame package process and package structure - Google Patents

Paddle-free frame package process and package structure Download PDF

Info

Publication number
CN106373935A
CN106373935A CN201610914057.1A CN201610914057A CN106373935A CN 106373935 A CN106373935 A CN 106373935A CN 201610914057 A CN201610914057 A CN 201610914057A CN 106373935 A CN106373935 A CN 106373935A
Authority
CN
China
Prior art keywords
island
chip
paddle
free
cured film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610914057.1A
Other languages
Chinese (zh)
Other versions
CN106373935B (en
Inventor
殷炯
王强
龚臻
刘怡
章春燕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201610914057.1A priority Critical patent/CN106373935B/en
Publication of CN106373935A publication Critical patent/CN106373935A/en
Application granted granted Critical
Publication of CN106373935B publication Critical patent/CN106373935B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85002Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a removable or sacrificial coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)

Abstract

The invention relates to a paddle-free frame package process and package structure. The structure comprises a paddle-free frame (1), wherein a curing film (2) is pasted on a front surface of the paddle-free frame (1), a chip (3) is arranged on the curing film (2), the chip (3) and the paddle-free frame (1) are electrically connected by electrical connection parts (4), a plastic package material (5) wraps the paddle-free frame (1), the curing film (2) and the electrical connection parts (4), and the plastic package material (5) is exposed out of a back surface of the paddle-free frame (1). According to the paddle-free frame package process and package structure, the curing film is pasted on the paddle-free frame and is cured to form a chip support structure having a paddle effect, the problem of routing instability and swinging or chip lifting during routing caused by too small contact area of the chip and a pin can be effectively solved, and meanwhile, the problem of frame warpping caused by large proportion difference between copper areas of two sides of a pre-package frame can also be prevented.

Description

A kind of island-free framework encapsulation technique and its encapsulating structure
Technical field
The present invention relates to a kind of island-free framework encapsulation technique and its encapsulating structure, belong to technical field of semiconductor encapsulation.
Background technology
Pass through the lead frame island-free product that etching is formed at present, be frame on pin during chip load.In fact, When chip carrier is on pin, because chip is too little with pins contact area, routing shakiness is led to be rocked or chip stress during routing While the abnormal phenomena lifting.
Although the pre-packaged framework of island-free can reach, by pre-fill plastic packaging material, the purpose supporting chip, island-free is pre- Encapsulating framework amasss proportional difference greatly due to framework both sides copper face, can produce framework warpage issues, and load glue can be in plastic packaging material Upper diffusion, stains on framework pin, affects product yield and reliability.
Content of the invention
The technical problem to be solved is to provide a kind of island-free framework encapsulation technique for above-mentioned prior art And its encapsulating structure, it forms the chip supporting structure of Ji Dao effect, Neng Gouyou after pasting cured film solidification on island-free framework Effect solves the problems, such as that chip and pins contact area are too little and leads to routing shakiness to be rocked or chip-side lifts, simultaneously during routing It can be avoided that pre-packaged framework both sides copper face amasss the framework warpage issues that proportional difference leads to greatly.
The present invention the adopted technical scheme that solves the above problems is: a kind of island-free framework encapsulation technique, described technique Comprise the steps:
Step one, by cured film be arranged on conversion film on;
Step 2, the one side that conversion film is provided with cured film are attached on the interior pin of island-free framework;
Step 3, cured film is solidified, cured film removes conversion film after completing solidification;
Step 4, in cured film arrange chip;
Step 5, it is electrically connected with chip and island-free framework with electrical connection member;
Step 6, encapsulating, are coated framework, cured film, chip, are electrically connected with part with plastic packaging material.
Described cured film is fow film or fod film.
Described electric connection part is bonding wire.
A kind of island-free framework encapsulation structure, it includes island-free framework, and described island-free framework front is covered with solidification Film, described cured film is provided with chip, and described chip and island-free framework are electrically connected with by being electrically connected with part, institute State island-free framework, cured film, be electrically connected with part outside be all encapsulated with plastic packaging material, the described island-free framework back side is exposed to plastic packaging Material.
Compared with prior art, it is an advantage of the current invention that:
1st, form the chip supporting structure of Ji Dao effect after patch cured film solidification on island-free framework, be capable of propping up of reinforced frame Support ability, can effectively solve the problem that chip and pins contact are too little and leads to routing shakiness to be rocked or asking of lifting of chip-side during routing Topic, the stability of chip and product yield when improving routing;
2nd, compared with pre-packaged technology: (1) can avoid the warpage issues of framework;(2) chip load glue can be avoided in plastic packaging Diffusion (it is fine that load glue spreads management and control effect on this kind of film) on material.
Brief description
Fig. 1 is a kind of schematic diagram of present invention island-free framework encapsulation structure.
Fig. 2 ~ Fig. 7 is a kind of each operation flow chart of present invention island-free framework encapsulation technique.
Wherein:
Island-free framework 1
Cured film 2
Chip 3
It is electrically connected with part 4
Plastic packaging material 5.
Specific embodiment
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
As shown in figure 1, one of the present embodiment island-free framework encapsulation structure, it includes island-free framework 1, described nothing Base island framework 1 front is covered with cured film 2, and described cured film 2 is provided with chip 3, and described chip 3 and island-free framework 1 lead to Cross electric connection part 4 to be electrically connected with, described island-free framework 1, cured film 2, outer being all encapsulated with of electric connection part 4 are moulded Envelope material 5, described island-free framework 1 back side is exposed to plastic packaging material 5.
Its process is as follows:
Step one, referring to Fig. 2, cured film is arranged on conversion film, required size is dimensioned to according to island-free framework, Cured film can be fow film or fod film etc.;
The characteristic of above-mentioned cured film: this film has half mobility before curing, by changing pad pasting, alignment method is mounted on hollow out The framework back side will not be flowed to from frame gap when on framework and stain profile;When by heating, film is changed into by half flow regime Solid-state, also will not flow to the framework back side from frame gap in the process, after this film changes into solid-state, add at normal temperatures or again Heat also will not revert to half flow regime;
Step 2, referring to Fig. 3, the one side that conversion film is provided with cured film is attached on the interior pin of island-free framework, makes solidification Film is attached on the interior pin of island-free framework;
Step 3, referring to Fig. 4, cured film is solidified, cured film complete solidification after remove conversion film;
Step 4, referring to Fig. 5, cured film carries out positive cartridge chip by load glue;
Step 5, referring to Fig. 6, be electrically connected with part and be electrically connected with chip and island-free framework, being electrically connected with part is bonding wire;
Step 6, referring to Fig. 7, encapsulate, coated framework, cured film, chip, be electrically connected with part with plastic packaging material, and island-free The framework back side is exposed to plastic packaging material.
In addition to the implementation, present invention additionally comprises there being other embodiment, all employing equivalents or equivalence replacement The technical scheme that mode is formed, all should fall within the scope of the hereto appended claims.

Claims (4)

1. a kind of island-free framework encapsulation technique is it is characterised in that described technique comprises the steps:
Step one, by cured film be arranged on conversion film on;
Step 2, the one side that conversion film is provided with cured film are attached on the interior pin of island-free framework;
Step 3, cured film is solidified, cured film removes conversion film after completing solidification;
Step 4, in cured film arrange chip;
Step 5, electric connection part are electrically connected with chip and island-free framework;
Step 6, encapsulating, are coated framework, cured film, chip, are electrically connected with part with plastic packaging material.
2. a kind of island-free framework encapsulation technique according to claim 1 it is characterised in that: described cured film is fow film Or fod film.
3. a kind of island-free framework encapsulation technique according to claim 1 it is characterised in that: described electric connection part be Bonding wire.
4. a kind of island-free framework encapsulation structure it is characterised in that: it includes island-free framework (1), described island-free framework (1) Front is covered with cured film (2), and described cured film (2) is provided with chip (3), and described chip (3) is led to island-free framework (1) Cross electric connection part (4) to be electrically connected with, described island-free framework (1), cured film (2), electric connection part (4) are equal outward It is encapsulated with plastic packaging material (5), described island-free framework (1) back side is exposed to plastic packaging material (5).
CN201610914057.1A 2016-10-20 2016-10-20 A kind of island-free framework encapsulation technique and its encapsulating structure Active CN106373935B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610914057.1A CN106373935B (en) 2016-10-20 2016-10-20 A kind of island-free framework encapsulation technique and its encapsulating structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610914057.1A CN106373935B (en) 2016-10-20 2016-10-20 A kind of island-free framework encapsulation technique and its encapsulating structure

Publications (2)

Publication Number Publication Date
CN106373935A true CN106373935A (en) 2017-02-01
CN106373935B CN106373935B (en) 2019-04-16

Family

ID=57896407

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610914057.1A Active CN106373935B (en) 2016-10-20 2016-10-20 A kind of island-free framework encapsulation technique and its encapsulating structure

Country Status (1)

Country Link
CN (1) CN106373935B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108171299A (en) * 2017-12-19 2018-06-15 中电智能卡有限责任公司 A kind of processing technology of smart card
WO2019227918A1 (en) * 2018-05-31 2019-12-05 江苏长电科技股份有限公司 Base-island-free frame packaging structure and process method therefor

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010042904A1 (en) * 2000-05-09 2001-11-22 Chikao Ikenaga Frame for semiconductor package
US7633144B1 (en) * 2006-05-24 2009-12-15 Amkor Technology, Inc. Semiconductor package
CN201752004U (en) * 2010-04-30 2011-02-23 江苏长电科技股份有限公司 Packaging structure for arranging chip directly
CN103390564A (en) * 2012-05-08 2013-11-13 Nxp股份有限公司 Film based IC packaging method and packaged IC device
CN104505380A (en) * 2014-12-19 2015-04-08 日月光封装测试(上海)有限公司 Semiconductor packaging body and manufacturing method thereof
CN205039143U (en) * 2015-08-20 2016-02-17 南昌欧菲生物识别技术有限公司 Electron device and electronic equipment
CN206250189U (en) * 2016-10-20 2017-06-13 江苏长电科技股份有限公司 A kind of island-free framework encapsulation structure

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010042904A1 (en) * 2000-05-09 2001-11-22 Chikao Ikenaga Frame for semiconductor package
US7633144B1 (en) * 2006-05-24 2009-12-15 Amkor Technology, Inc. Semiconductor package
CN201752004U (en) * 2010-04-30 2011-02-23 江苏长电科技股份有限公司 Packaging structure for arranging chip directly
CN103390564A (en) * 2012-05-08 2013-11-13 Nxp股份有限公司 Film based IC packaging method and packaged IC device
CN104505380A (en) * 2014-12-19 2015-04-08 日月光封装测试(上海)有限公司 Semiconductor packaging body and manufacturing method thereof
CN205039143U (en) * 2015-08-20 2016-02-17 南昌欧菲生物识别技术有限公司 Electron device and electronic equipment
CN206250189U (en) * 2016-10-20 2017-06-13 江苏长电科技股份有限公司 A kind of island-free framework encapsulation structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108171299A (en) * 2017-12-19 2018-06-15 中电智能卡有限责任公司 A kind of processing technology of smart card
WO2019227918A1 (en) * 2018-05-31 2019-12-05 江苏长电科技股份有限公司 Base-island-free frame packaging structure and process method therefor

Also Published As

Publication number Publication date
CN106373935B (en) 2019-04-16

Similar Documents

Publication Publication Date Title
TWI413195B (en) Method and apparatus of compression molding for reducing viods in molding compound
TWI476877B (en) Structure and method for air cavity packaging
CN106847800A (en) QFN surface-adhered types RGB LED encapsulation modules and its manufacture method
CN207097856U (en) Potted element, circuit board and lighting device
CN106373935A (en) Paddle-free frame package process and package structure
CN206340542U (en) A kind of QFN surface-adhered types RGB LED encapsulation modules
CN206250189U (en) A kind of island-free framework encapsulation structure
CN102263077A (en) Double flat carrier-free pin-free IC chip packaging part
CN104810462B (en) ESOP8 lead frame of medium-and high-power LED driving chip
CN201262956Y (en) High-power multi-chip packaging structure of integrated circuit
CN100587946C (en) Encapsulation conformation and encapsulation method capable of balancing window top and bottom model stream
CN104617052A (en) Smart card module packaged through adhesive film pre-arranging technology and packaging method
CN102856216B (en) Method for packaging square and flat soldering lug without pin
CN101764114A (en) Inversion type encapsulation structure and manufacturing method thereof
CN104465596A (en) Lead frame, semiconductor packaging body and manufacturing method thereof
TWI459528B (en) A method of package with clip bonding
CN208938954U (en) A kind of island-free framework encapsulation structure
CN103107098B (en) The method for packing of quad flat non-pin and encapsulating structure thereof
CN202196776U (en) Flat carrier-free leadless pin exposed packaging part
CN104112811A (en) LED (light emitting diode) packaging method
CN204441277U (en) A kind of smart card module adopting preset glued membrane technique to encapsulate
CN111276590A (en) Frame type support structure LED packaging technology
CN204680667U (en) Level chip encapsulating structure
CN104600044A (en) Micro smart card and packaging method
CN204271072U (en) Lead-frame packages structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant